SKEL 4283 Analog CMOS IC Design Current Mirrors

Transcription

1 SKEL 4283 Analog CMOS IC Design Current Mirrors Dr. Nasir Shaikh Husin Faculty of Electrical Engineering Universiti Teknologi Malaysia Current Mirrors 1 Objectives Introduce and characterize the current mirrors Show how to improve the performance of the current mirrors Demonstrate the design of current mirrors Current Mirrors 2

2 Characterization of Current Mirrors Current mirror is basically a current amplifier needs current source, or current sink Ideal characteristics of current amplifier output current linearly related to input current, i out = A i i in input resistance is zero output resistance is infinity In addition, we have V MIN specs V MIN (in) range of input voltage over which input resistance is very small V MIN (out) min voltage across sink/source for which current is no longer constant Current Mirrors 3 Current Source/Sink Basic circuit V dd I out V 1 M 6 Current Source V out V b M 5 Current Sink I out Current Mirrors 4

3 Current Source/Sink cont. Ideal current source/sink current is fixed at I o voltage across the circuit can be any value from to + Actual sink output resistance R o is finite current varies as voltage across circuit varies i + I o R o v - Current Mirrors 5 Current Mirrors NMOS current mirror I in I out M b V b M 5 V out I out = (W/L) 5 /(W/L) b I in PMOS current mirror V dd M 4 V b V dd M 7 I in I out I out = (W/L) 7 /(W/L) 4 I in Current Mirrors 6

4 Multiple Current Mirrors Circuit with multiple outputs I in I out1 I out2 I out3 V out1 V out2 V out3 M b V b M 5 M 6 M 7 I out1 = (W/L) 5 /(W/L) b I in I out2 = (W/L) 6 /(W/L) b I in I out3 = (W/L) 7 /(W/L) b I in Current Mirrors 7 Gate-Source Voltage Components V GS = V GG consists of two components voltage to create channel voltage to cause current flow V GS = V T0 + V OD where V OD = V DS (sat) = V GS - V T0 Current Mirrors 8

5 NMOS Current Sink Basic circuit If transistor biased in sat. region I DS = ½K N (W/L)(V GG - V T0 ) 2 (1 + λv DS ) di DS /dv DS = ½K N (W/L)(V GG - V T0 ) 2 λ = ½K N (W/L)(V GG - V T0 ) 2 λ(1 + λv DS )/(1 + λv DS ) = λi DS /(1 + λv DS ) output resistance d vds 1 V DS rout 1 d ids I DS I DS V MIN = V DS (sat) = V OD = V GS - V T0 = V GG - V T0 = Current Mirrors 9 2 I DS ' W K N L neglecting λ effect NMOS Current Sink Simulation Design current sink for TSMC 0.25 μm process K N = 115 μa/v 2, V T0 = 0.43 V, λ = 0.06 V -1 choose r out = 250 kω r out 1/λI DS ; I DS 66.7 μa choose V MIN = V OD = 0.25 V I DS = ½K N (W/L)(V GS - V T0 ) 2 = ½K N (W/L)V OD2 ; W/L = choose L = 2 μm; W = μm choose W = μm V OD = V GS - V T0 ; V GS = V GG = 0.68 V 160µA Id(M1) Id(M1l1) I DS = 140 μa! 140µA 120µA level 49 r out = 160 kω 100µA 80µA 60µA V MIN = 0.25 V level 1 40µA 20µA Current Mirrors 10 0µA 0.0V 0.3V 0.6V 0.9V 1.2V 1.5V 1.8V 2.1V 2.4V --- C:\Temp\junk\NMOSSink\NMOSSink.s p ---

6 Generating Bias Voltage Simple method Simple current sink has two problems V MIN may be too large may reduce it by using large (W/L) output resistance r out may be too small Current Mirrors 11 Increasing r out of Current Sink Use feedback How it works assume i OUT increases v S increases v GS decreases decrease in v GS causes i OUT to decrease, opposing the original increase when current cannot increase, we have high effective resistance Current Mirrors 12

7 Increasing r out of Current Sink cont. Small signal analysis Output resistance v out = (i out - g m2 v gs2 - g mbs2 v bs2 )r ds2 + i out R = i out (r ds2 + R) (g m2 v gs2 + g mbs2 v bs2 )r ds2 v gs2 = v g2 - v s2 = 0 i out R = -i out R v bs2 = v b2 - v s2 = 0 i out R = -i out R v out = i out (r ds2 + R) + (g m2 i out R + g mbs2 i out R)r ds2 = i out [ r ds2 + R + (g m2 + g mbs2 )Rr ds2 ] r out = v out /i out = r ds2 + R + (g m2 + g mbs2 )Rr ds2 (g m2 + g mbs2 )Rr ds2 g m2 r ds2 R r out is much bigger We derived this earlier when we want to find out R out for CS Amp with Source Degeneration Current Mirrors 13 Cascode Current Sink Circuit and small signal equivalent Output resistance r out g m2 r ds2 r ds1 Current Mirrors 14

8 Design of Bias Voltages Cascode current sink Bias design Assume M1 in saturation. Select V GG1 to provide desired current. Select V GG2 to keep V DS1 as small as possible but keep M1 in saturation V GG2 = V DS1 (sat) + V GS2 = V DS1 (sat) + V T + V DS2 (sat) If (W/L) 1 = (W/L) 2, V DS2 (sat) = V DS1 (sat) = V DS (sat) V GG2 = 2V DS (sat) + V T = 2V OD + V T Current Mirrors 15 NMOS Cascode Current Sink Simulation For TSMC 0.25 μm process K N = 115 μa/v 2, V T0 = 0.43 V, λ = 0.06 V -1 from previous circuit V GG1 = 0.68 V; V OD1 = 0.25 V choose V OD2 = 0.25 V = V OD1 = V OD V GG2 = 2V OD + V T0 = 0.93 V 130µA Id(M2) Id(M2l1) I DS = 127 μa 120µA 110µA level 49 r out = 1 MΩ 100µA 90µA 80µA 70µA 60µA level 1 50µA 40µA V MIN = 0.5 V 30µA 20µA 10µA 0µA 0.0V 0.3V 0.6V 0.9V 1.2V 1.5V 1.8V 2.1V 2.4V C:\Temp\junk\NMOSCascodeSink\NMOSCascodeSink.s p Current Mirrors 16

9 R 1 R 2 Basic Cascode Current Sink Simple biasing circuit Note: Circuit from Allen textbook where V ON instead of V OD is used to denote overdrive voltage I REF 2V T + 2V OD V T + 2V OD V MIN is higher! V DS1 = V G2 V GS2 = 2V T + 2V OD (V T + V OD ) = V T + V OD V MIN = V T + V OD + V OD = V T + 2V OD Can we design so that V MIN = 2V OD? how do we reduce V DS1? Current Mirrors 17 High-Swing Cascode Current Sink Use two separate circuits to bias output transistors choose R 1 and R 2 to set reference current we must set V GG2 to V T + 2V OD Current Mirrors 18 2 I DS V OD = ' W K N L can double V OD by making W 1 W L L 4 4 V DS1 V DS3 however also known as low-voltage cascode current sink 1 2V OD

10 High-Swing Cascode Current Sink cont. Improved biasing circuit 2V OD to maintain same current, V GS1 = V GS2 = V GS3 = V GS5 = V T + V OD V DS3 = V G4 V GS5 = V T + 2V OD (V T + V OD ) = V OD V DS1 = V DS3! must keep V GS4 = V T + 2V OD as before M2 still suffers from body effect Exercise 1: Prove that V T must be greater than V OD to ensure M5 in saturation. Current Mirrors 19 High-Swing Cascode Current Sink Simulation For TSMC 0.25 μm process K N = 115 μa/v 2, V T0 = 0.43 V, λ = 0.06 V -1 from previous circuit (simple sink on p. 10) I REF = 66.7 μa; L = 2 μm; W 1 = W 2 = W 3 = W 5 = μm W 1 W since L ; W 4 = W 1 /4 = 9.25 μm 4 4 L 1 Exercise 2: determine R 1 and R 2 70 μa 77µA 70µA Id(M2) Id(Mb2) 63µA 56µA high-swing cascode 49µA 42µA 35µA 28µA 21µA basic cascode (p.17) 14µA 7µA 0µA -7µA 0.0V 0.3V 0.6V 0.9V 1.2V 1.5V 1.8V 2.1V 2.4V --- C:\Temp\junk\NMOSHi ghswin gcascodesink\nmoshi ghswin gcascodesink.s p --- Current Mirrors 20

11 Exercise 3 Choose R and (W/L) 1 to set I OUT = 5 μa assume TSMC 0.25 μm process: K N = 115 μa/v 2, V T0 = 0.43 V V DD = 2.5 V I OUT 6 μm/2 μm Current Mirrors 21 Exercise 4 Assume TSMC 0.25 μm process: K P = -30 μa/v 2, V T0 = V. determine I D3 if W 2 is doubled, find I D2 does V GS2 change? does V GS3 change? V DD = 2.5 V 380 kω 380 kω (W/L) 1 = 6 μm/2 μm (W/L) 2 = 6 μm/2 μm (W/L) 3 = 18 μm/2 μm Current Mirrors 22