Lecture 240 Cascode Op Amps (3/28/10) Page 240-1

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1 Lecture 240 Cascode Op Amps (3/28/10) Page 2401 LECTURE 240 CASCODE OP AMPS LECTURE ORGANIZATION Outline Lecture Organization Single Stage Cascode Op Amps Two Stage Cascode Op Amps Summary CMOS Analog Circuit Design, 2 nd Edition Reference Pages Lecture 240 Cascode Op Amps (3/28/10) Page 2402 Cascode Op Amps Why cascode op amps? Control of the frequency behavior Can get more gain by increasing the output resistance of a stage In the past section, PSRR of the twostage op amp was insufficient for many applications A twostage op amp can become unstable for large load capacitors (if nulling resistor is not used) The cascode op amp leads to wider ICMR and/or smaller power supply requirements Where Should the Cascode Technique be Used? First stage Good noise performance Requires level translation to second stage Degrades the Miller compensation Second stage Self compensating Increases the efficiency of the Miller compensation Increases PSRR

2 Lecture 240 Cascode Op Amps (3/28/10) Page 2403 SINGLE STAGE CASCODE OP AMPS Simple Single Stage Cascode Op Amp V PBias2 MC3 MC4 v o1 Implementation of the floating voltage VBias which must equal MB3 2V ON V T. V PBias2 MC3 MB4 MC4 MC1 MC2 M1 M2 V Bias vin 2 2 V NBias1 M5 V SS MB5 MC1 MC2 M1 M2 VBias MB1 MB2 vin 2 2 V NBias1 M5 V SS R out of the first stage is R I (g mc2 r dsc2 r ds2 ) (g mc4 r dsc4 r ds4 ) Voltage gain = v o1 = g m1 R I [The gain is increased by approximately 0.5(g MC r dsc )] As a single stage op amp, the compensation capacitor becomes the load capacitor. Lecture 240 Cascode Op Amps (3/28/10) Page 2404 Example 2401 SingleStage, Cascode Op Amp Performance Assume that all W/L ratios are 10 μm/1 μm, and that I DS1 = I DS2 = 50 μa of single stage op amp. Find the voltage gain of this op amp and the value of C I if GB = 10 MHz. Use K N = 120μA/V 2, K P = 25μA/V 2, V TN = 0.5V, V TP = 0.5V, N = 0.06V 1 and P = 0.08V 1. Solution The device transconductances are g m1 = g m2 = g mi = μs g mc1 = g mc2 = 346.4μS g mc3 = g mc4 = μs. The output resistance of the NMOS and PMOS devices is M and 0.25 M, respectively. R I = 7.86 M A v (0) = 2,722 V/V. For a unitygain bandwidth of 10 MHz, the value of C I is 5.51 pf. What happens if a 100pF capacitor is attached to this op amp? GB goes from 10MHz to 0.551MHz.

3 Lecture 240 Cascode Op Amps (3/28/10) Page 2405 Enhanced Gain, Single Stage, Cascode Op Amp M7 M8 M7 M8 M5 A A A M6 v OUT M5 V PB1 V NB1 M15 M16 VDD M13 M14 M11 M12 M6 v OUT v IN M1 V NB1 M9 M2 v IN V NB1 M1 M9 M2 M From inspection, we can write the voltage gain as, A v = v OUT v = g IN m1 R out where R out = (Ar ds6 g m6 r ds8 ) (Ar ds2 g m4 r ds4 ) Since A g m r ds /2 the voltage gain would be equal to 100,000 to 500,000. Output is not optimized for maximum signal swing. Lecture 240 Cascode Op Amps (3/28/10) Page 2406 TWOSTAGE, CASCODE OP AMPS TwoStage Op Amp with a Cascoded FirstStage MC3 R MC1 M1 2 MB3 VBias MB5 VBias MB1 MB2 M5 V SS MB4 v o1 MC4 MC2 M2 v in 2 MT2 MT1 C c M6 M7 Current MT1 and MT2 are required for level shifting from the firststage to the second. The PSRR is improved by the presence of MT1 Internal loop pole at the gate of M6 may cause the Miller compensation to fail. p 3 p2 The voltage gain of this op amp could easily be 100,000V/V I D6 V T6 W 6 /L 6 W 6 /L 6 << W 6 /L 6 V SG6 V SG6 = Volts = V SD4 V SD4 V SDC4 p 1 jω σ z 1 Fig. 6.52A

4 Lecture 240 Cascode Op Amps (3/28/10) Page 2407 TwoStage Op Amp with a Cascode SecondStage A v = g mi g mii R I R II where g mi = g m1 = g m2, g mii = g m6, and R I = 1 2 g ds2 g ds4 = ( 2 4 )I D5 R II = (g mc6 r dsc6 r ds6 ) (g mc7 r dsc7 r ds7 ) Comments: The secondstage gain has greatly increased improving the Miller compensation M1 M2 The overall gain is approximately (g m r ds )3 or very large Output pole, p 2, is approximately the same if C c is constant The zero RHP is the same if C c is constant PSRR is poor unless the Miller compensation is removed (then the op amp becomes self compensated) VBias M5 R z V SS VBP C c VBN M6 MC6 MC7 M7 C L Fig Lecture 240 Cascode Op Amps (3/28/10) Page 2408 A Balanced, TwoStage Op Amp using a Cascode Output Stage = g m1 g m8 g m3 2 g m2g m6 g m4 2 R II M6 = g m1 2 g m2 M8 V 2 kv PB2 in R II = g m1 k R II v M7 in where M1 M2 R II = (g m7 r ds7 r ds6 ) (g m12 r ds12 r ds11 ) V M9 NB2 M12 C L and k = g m8 g m3 = g M5 M10 m6 M11 g m4 V NB This op amp is balanced because the draintoground loads for M1 and M2 are identical. TABLE 1 Design Relationships for Balanced, Cascode Output Stage Op Amp. Slew rate = I out C L V in (max) = V SS I 5 1/2 3 GB = g m1g m8 g m3 C L A v = 1 g m1 g m8 2 g m2g m6 g m3 g m4 R II V TO3 (max) V T1 (min) V in (min) = V SS V DS5 1/2 1 V T1 (min) I 5

5 Lecture 240 Cascode Op Amps (3/28/10) Page 2409 Example 2402 Design of Balanced, Cascoded Output Stage Op Amp Design a balanced, cascoded output stage op amp using the procedure outlined above. The specifications of the design are as follows: = 2.5 V (V SS = 0) Slew rate = 5 V/μs with a 50 pf load GB = 10 MHz with a 25 pf load A v 5000 Input CMR = 1V to 2 V 0.5V < Output swing < 2 V Use K N =120μA/V 2, K P = 25μA/V 2, V TN = V TP = 0.5V, N = 0.06V 1, and P = 0.08V 1 and let all device lengths be 0.5 μm. Solution While numerous approaches can be taken, we shall follow one based on the above specifications. The steps will be numbered to help illustrate the procedure. 1.) The first step will be to find the maximum source/sink current. This is found from the slew rate. I source /I sink = C L slew rate = 50 pf(5 V/μs) = 250 μa 2.) Next some W/L constraints based on the maximum output source/sink current are developed. Under dynamic conditions, all of I 5 will flow in ; thus we can write Max. I out (source) = (S 6 /S 4 )I 5 and Max. I out (sink) = (S 8 /S 3 )I 5 The maximum output sinking current is equal to the maximum output sourcing current if S 3 = S 4, S 6 = S 8, and S 10 = S 11 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2402 Continued 3.) Choose I 5 as 100 μa. This current (which can be changed later) gives S 6 = 2.5S 4 and S 8 = 2.5S 3 Note that S 8 could equal S 3 if S 11 = 2.5S 10. This would minimize the power dissipation. 4.) Next design for 0.5V output capability. We shall assume that the output must source or sink the 250μA at the peak values of output. First consider the negative output peak. Since there is 0.5V difference between V SS (0V) and the minimum output, let V DS11 (sat) = V DS12 (sat) = 0.25 V (we continue to ignore the bulk effects). Under the maximum negative peak assume that I 11 = I 12 = 250 μa. Therefore 0.25 = 2I 11 K' N S 11 = 2I 12 K' N S 12 = 500μA (120μA/V2)S 11 which gives S 11 = S 12 = 67 and S 9 = S 10 = 67. For a maximum output voltage of 2V, we get 2I 6 K' P S 6 = 2I 7 K' P S 7 = 500μA 0.25 = (25μA/V2)S 6 which gives S 6 = S 7 = S 8 = 320 and S 3 = S 4 = (320/2.5) = 128.

6 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2402 Continued 5.) Now we must consider the possibility of conflict among the specifications. First consider the input CMR. S 3 has already been designed as 67. Using ICMR relationship, we find that S 3 should be at least 8. A larger value of S 3 will give a higher value of V in (max) so that we continue to use S 3 = 67 which gives V in (max) = 2.32V. Next, check to see if the larger W/L causes a pole below the gainbandwidth. Assuming a C ox of 6fF/μm 2 gives the firststage pole of g m3 2K P S 3 I 3 p 3 = C gs3 C gs8 = (0.667)(W 3 L 3 W 8 L 8 )C ox = 3.125x109 rads/sec or 497 MHz which is much greater than 10GB. 6.) Next we find g m1 (g m2 ). There are two ways of calculating g m1. (a.) The first is from the A v specification. The gain is A v = (g m1 /2g m4 )(g m6 g m8 ) R II Note, a current gain of k can be introduced by making S 6 /S 4 (S 8 /S 3 = S 11 /S 3 ) equal to k. g m6 g m4 = g m11 g m3 = 2K P S 6 I 6 2K P S 4 I 4 = k Calculating the various transconductances we get g m4 = 566 μs, g m6 = g m7 = g m8 = 1414 μs, g m11 = g m12 = 1414 μs, r ds6 = r d7 = 100 k, and r ds11 = r ds12 = 133 k. Assuming that the gain A v must be greater than 5000 and k = 2.5 gives g m1 > 221 μs. Lecture 240 Cascode Op Amps (3/28/10) Page Example 2402 Continued (b.) The second method of finding g m1 is from the GB specifications. Multiplying the gain by the dominant pole (1/C II R II ) gives GB = g m1(g m6 g m8 ) 2g m4 C L Assuming that C L = 25 pf and using the specified GB gives g m1 = 628 μs. Since this is greater than 221μS, we choose g m1 = g m2 = 628μS. Knowing I 5 gives S 1 = S 2 = ) The next step is to check that S 1 and S 2 are large enough to meet the 1V input CMR specification. Use the saturation formula we find that V DS5 is V. This gives S 5 = 15. The gain becomes A v = 14,182V/V and GB = 10 MHz for a 25 pf load. We shall assume that exceeding the specifications in this area is not detrimental to the performance of the op amp. 9.) Knowing the currents and W/L values, the bias voltages V NB1, V NB2 and V PB2 can be designed. The W/L values resulting from this design procedure are shown below. The power dissipation for this design is seen to be 350μA 2.5V = mw. S 1 = S 2 = 33 S 3 = S 4 = 128 S 5 = 15 S 6 = S 7 = S 8 = 320 S 9 = S 10 = S 11 = S 12 = 67

7 Lecture 240 Cascode Op Amps (3/28/10) Page Technological Implications of the Cascode Configuration A A B C D B C D Thin oxide Poly I Poly II n nchannel p substrate/well n Fig If a double poly CMOS process is available, internode parasitics can be minimized. As an alternative, one should keep the drain/source between the transistors to a minimum area. B C A D Thin oxide Minimum Poly A separation B C D Poly I Poly I n nchannel n nchannel n p substrate/well Fig. 6.55A Lecture 240 Cascode Op Amps (3/28/10) Page Input Common Mode Range for Two Types of Differential Amplifier Loads V SG3 V TN V SG3 Input Common Mode Range M1 V SD3 V TN V SD4 V SD3 V SD4 Input Common Mode VBP Range M2 M1 M2 V SS V DS5 V GS1 V SS V DS5 V GS1 M5 v icm M5 v icm VBias VBias V SS V SS Differential amplifier with Differential amplifier with a current mirror load. current source loads. Fig In order to improve the ICMR, it is desirable to use current source (sink) loads without losing half the gain. The resulting solution is the folded cascode op amp.

8 Lecture 240 Cascode Op Amps (3/28/10) Page The Folded Cascode Op Amp V PB1 I 4 I 5 M5 v IN I 1 I 2 M1 M2 R A V PB2 R B I 6 I 7 M6 M7 V NB2 M8 M9 v OUT C L V NB1 I3 M10 M Comments: I 4 and I 5, should be designed so that I 6 and I 7 never become zero (i.e. I 4 =I 5 =1.5I 3 ) This amplifier is nearly balanced (would be exactly if R A was equal to R B ) Self compensating Poor noise performance, the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors. (Some first stage gain can be achieved if R A and R B are greater than g m1 or g m2. Lecture 240 Cascode Op Amps (3/28/10) Page SmallSignal Analysis of the Folded Cascode Op Amp Model: g m6 v gs6 R Recalling what we A learned about the i 10 g resistance looking into m1 r 2 r ds1 r ds6 ds4 1 the source of the g m10 cascode transistor; g m7 v gs7 g m2 v gs6 r 2 r ds2 r v gs7 ds7 ds5 i 10 R II R A = r ds6(1/g m10 ) 1g m6 r ds6 1 g m6 and R B = r ds7r II R II 1g m7 r ds7 g m7 r ds7 where R II g m9 r ds9 r ds11 The voltage transfer function can be found as follows. The current i 10 is written as i 10 = g m1(r ds1 r ds4 ) 2[R A (r ds1 r ds4 )] g m1 2 and the current i 7 can be expressed as g m2 (r ds2 r ds5 ) g m2 g m2 i 7 = R 2 II = g m7 r ds7 (r ds2 r ds5 ) 2 1 R II(g ds2 g ds5 ) = 2(1k) where k = R II(g ds2 g ds5 ) g m7 r ds7 g m7 r ds7 The output voltage,, is equal to the sum of i 7 and i 10 flowing through R out. Thus, = g m1 2 g m2 2(1k) R out = 2k 22k g mir out R B i 7

9 Lecture 240 Cascode Op Amps (3/28/10) Page Intuitive Analysis of the Folded Cascode Op Amp Assume that a voltage of V is applied. We know that R A (M6) 1/g m6 and R B (M7) r ds The currents flowing to the output are, g m1 V 2 g m2v 4 The output resistance is approximately, R out (g m9 r ds9 r ds11 ) [ g m7 r ds7 (r ds2 r ds5 )] g m r ds 2 3 Therefore, the approximate voltage gain is, = g m1 2 g m2 4 R out 3g m 4 R out = g m 2r ds 2 4 While the analysis is simpler than small signal analysis, the value of k defined in the previous slide is 1. Lecture 240 Cascode Op Amps (3/28/10) Page Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as p out = 1 R out 'C out where R out = 2k 22k R out where C out is all the capacitance connected from the output of the op amp to ground. All other poles must be greater than GB = g m1 /C out. The approximate expressions for each pole is 1.) Pole at node A: p A g m6 /(C gs 2C db ) 2.) Pole at node B: p B g m7 /(C gs 2C db ) 3.) Pole at drain of M6: p 6 g m10 /(2C gs 2C db ) 4.) Pole at source of M8: p 8 (g m8 r ds8 g m10 )/(C gs C db ) 5.) Pole at source of M9: p 9 g m9 /(C gs C db ) where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node. One might feel that because RB is approximately rds that this pole also might be small. However, at frequencies where this pole has influence, Cout, causes Rout to be much smaller making p B also nondominant.

10 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2403 Folded Cascode, CMOS Op Amp Assume that all g mn = g mp = 100μS, r dsn = 2M, r dsp = 1M, and C L = 10pF. Find all of the smallsignal performance values for the foldedcascode op amp. R II = 0.4G, R A = 10k, and R B = 4M k = 0.4x10 9(0.3x106) 100 = 1.2 = (100)(57.143) = 4,156V/V R out = R II [g m7 r ds7 (r ds5 r ds2 )] = 400M [(100)(0.667M)] = M p out = 1 1 R out C out = M 10pF = 1,750 rads/sec. 278Hz GB = 1.21MHz Lecture 240 Cascode Op Amps (3/28/10) Page PSRR of the Folded Cascode Op Amp Consider the following circuit used to model the PSRR: R V ss V GSG9 C gd9 V out M9 C gd11 V ss V ss V ss r V ds11 GS11 M11 r ds9 C gd9 C out R out Vout V ss Fig. 6.59A This model assumes that gate, source and drain of M11 and the gate and source of M9 all vary with V SS. We shall examine V out /V ss rather than PSRR. (Small V out /V ss will lead to large PSRR.) The transfer function of V out /V ss can be found as V out sc gd9 R out V ss sc out R out 1 for C gd9 < C out The approximate PSRR is sketched on the next page.

11 Lecture 240 Cascode Op Amps (3/28/10) Page Frequency Response of the PSRR of the Folded Cascode Op Amp db PSRR A vd (ω) 1 C gd9 R out 0dB C gd9 C out Dominant pole frequency GB V out V ss Other sources of V ss injection, i.e. r ds9 log 10 (ω) Fig A We see that the PSRR of the cascode op amp is much better than the twostage op amp without any modifications to improve the PSRR. Lecture 240 Cascode Op Amps (3/28/10) Page Design Approach for the FoldedCascode Op Amp Step Relationship Design Equation/Constraint Comments 1 Slew Rate I 3 = SR C L 2 Bias currents in output cascodes I 4 = I 5 = 1.2I 3 to 1.5I 3 Avoid zero current in cascodes 3 Maximum output 2I 5 voltage, S 5 = (max) KP VSD5 2, S 7 = 2I 7 KP VSD7 2, (S 4 =S 5 and S 6 = S 7 ) V SD5 (sat)=v SD7 (sat) = 0.5[ V out (max)] 4 Minimum output 2I11 voltage, vout(min) S11= KN VDS11 2, S 2I9 9= KN VDS9 2, (S VDS9(sat)=VDS11(sat) 10=S11and S8=S9) = 0.5[Vout(min)VSS] 5 gm1 GB = gm1 2 CL S1=S2= KN I3 = GB2CL 2 KN I3 6 Minimum input 2I3 CM S3 = Vin(min)VSS (I3/KN S1)VT1 2 KN 7 Maximum input 2I4 CM S4 = S5 = 2 S4 and S5 must meet or KP VDDVin(max)VT1 exceed value in step 3 8 Differential vout Voltage Gain vin = gm1 2 gm2 2(1k) R out = 2k 22k g mirout k = R II(g ds2 g ds4 ) g m7 r ds7 9 Power dissipation Pdiss = (VDDVSS)(I3I10I11)

12 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2404 Design of a FoldedCascode Op Amp Design a foldedcascode op amp if the slew rate is 10V/μs, the load capacitor is 10pF, the maximum and minimum output voltages are 2V and 0.5V for a 2.5V power supply, the GB is 10MHz, the minimum input common mode voltage is 1V and the maximum input common mode voltage is 2.5V. The differential voltage gain should be greater than 3,000V/V and the power dissipation should be less than 5mW. Use K N =120μA/V 2, K P = 25μA/V 2, V TN = V TP = 0.5V, N = 0.06V 1, and P = 0.08V 1. Let L = 0.5 μm. Solution Following the approach outlined above we obtain the following results. I 3 = SR C L = 10x = 100μA Select I 4 = I 5 = 125μA. Next, we see that the value of 0.5( V out (max)) is 0.5V/2 or 0.25V. Thus, 2 125μA S 4 = S 5 = 25μA/V2 (0.25V) 2 = = 160 and assuming worst case currents in M6 and M7 gives, 2 125μA S 6 = S 7 = 25μA/V 2 (0.25V) 2 = = 160 The value of 0.5(V out (min) V SS ) is 0.25V which gives the value of S 8, S 9, S 10 and S 11 as 2 I S 8 = S 9 = S 10 = S 11 = K N V DS8 2 = 120 (0.25) 2 = 20 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2404 Continued In step 5, the value of GB gives S 1 and S 2 as S 1 = S 2 = GB 2 C L 2 K N I 3 = (20x106 )2(1011)2 120x x106 = The minimum input common mode voltage defines S 3 as 2I 3 S 3 = K N V in (min)v SS 200x10 = 6 = I 3 K N S 1 V 2 T1 120x We need to check that the values of S 4 and S 5 are large enough to satisfy the maximum input common mode voltage. The maximum input common mode voltage of 2.5 requires 2I μA S 4 = S 5 K P [ V in (max)v T1 ] 2 = 25x106μA/V2[0.5V] 2 = 40 which is less than 160. In fact, with S 4 = S 5 = 160, the maximum input common mode voltage is 2.75V. The power dissipation is found to be P diss = 2.5V(125μA125μA) = 0.625mW

13 Lecture 240 Cascode Op Amps (3/28/10) Page Example 2404 Continued The smallsignal voltage gain requires the following values to evaluate: S 4, S 5 : g m = = 1000μS and g ds = 125x = 10μS S 6, S 7 : g m = = 774.6μS and g ds = 75x = 6μS S 8, S 9, S 10, S 11 : g m = = 600μS and g ds = 75x = 4.5μS S 1, S 2 : g mi = = 629μS and g ds = 50x10 6 (0.06) = 3μS Thus, R II g m9 r ds9 r ds11 = (600μS) μS 4.5μS = 29.63M R out 29.63M (774.6μS) 1 1 6μS 10μS3μS = 7.44M k = R II(g ds2 g ds4 ) g m7 r ds7 = 7.44M(3μS10μS)(6μS) 774.6μS = 0.75 The smallsignal, differentialinput, voltage gain is A vd = 2k 22k g mir out = x x106 = (0.786)(4680) = 3,678 V/V The gain is slightly larger than the specified 3,000 V/V. Lecture 240 Cascode Op Amps (3/28/10) Page Comments on Folded Cascode Op Amps Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance (use Miller compensation in this case) Need first stage gain for good noise performance Widely used in telecommunication circuits where large dynamic range is required

14 Lecture 240 Cascode Op Amps (3/28/10) Page EnhancedGain, Folded Cascode Op Amps If more gain is needed, the folded cascode op amp can be enhanced to boost the output impedance even higher as follows. M10 V PB1 A M11 v IN M1 M2 M8 M9 v OUT M6 M7 A A Voltage gain = g m1 R out, where R out [Ar ds7 g m7 (r ds1 r ds5 )] (Ar ds9 g m9 r ds11 ) V NB1 M Since A g m r ds the voltage gain would be in the range of 100,000 to 500,000. Note that to achieve maximum output swing, it will be necessary to make sure that M5 and M11 are biased with V DS = V DS (sat). Lecture 240 Cascode Op Amps (3/28/10) Page What are the Enhancement Amplifiers? Requirements: 1.) Need a gain of g m r ds. 2.) Must be able to set the dc voltage at its input to get wideoutput voltage swing. Possible Enhancement Amplifiers: A V PB1 V M5 PB2 V NB1 M6 V SD (Sat) A V PB1 V NB2 M5 V NB1 M6 M1 M2 V DS (Sat)

15 Lecture 240 Cascode Op Amps (3/28/10) Page EnhancedGain, Folded Cascode Op Amp Detailed realization: Lecture 240 Cascode Op Amps (3/28/10) Page Frequency Response of the Enhanced Gain Cascode Op Amps Normally, the frequency response of the cascode op amps would have one dominant pole at the output. The frequency response would be, A v (s) = g R out (1/sC out ) g m1 R out m1 R out 1/sC out = sr out C out 1 = g m1r out 1 s p 1 If the amplifier used to boost the output resistance had no frequency dependence then the frequency response would be as follows. Gain (db) 100dB Enhanced Gain Cascode Op Amp 80dB 60dB 40dB 0dB Normal Cascode Op Amp p 1 (enh) p 1 GB log 10 ω

16 Lecture 240 Cascode Op Amps (3/28/10) Page Frequency Response of the Enhanced Gain Cascode Op Amp Continued Does the pole in the feedback amplifier A have an influence? Although the output resistance can be modeled as, R out R out A o s 1p 2 A o 1 s p 2 it has no influence on the frequency response because C out has shorted out any influence a change in R out might have. Higher order poles come from a diversion of the current flow in the op amp to ground rather than the intended destination of the current to the output. These poles that divert the current are: Pole at the source of M6 (Ag m6 /C 6 ) Pole at the source of M7 (Ag m7 /C 7 ) Pole at the drain of M8 (g m10 /C 8 ) Pole at the source of M9 (Ag m9 /C 6 ) Pole at the drain of M10 (g m8 r ds8 g m10 /C 10 ) Note that the enhancement amplifiers cause most of the higherorder poles to be moved out by A. However, each of the enhancement amplifiers introduce a pole at their output which is approximately 1/[r ds (C gs 2C db 2C gd )]. These poles become the dominant poles that limit GB. Lecture 240 Cascode Op Amps (3/28/10) Page SUMMARY Cascode op amps give additional flexibility to the twostage op amp Increase the gain Control the dominant and nondominant poles Enhanced gain, cascode amplifiers provide additional gain and are used when high gains are needed Folded cascode amplifier is an attractive alternate to the twostage op amp Wider ICMR Self compensating Good PSRR