Microelectronic Circuits II. Ch 10 : Operational-Amplifier Circuits

Transcription

1 Microelectronic Circuits II Ch 0 : Operational-Amplifier Circuits 0. The Two-stage CMOS Op Amp 0.2 The Folded-Cascode CMOS Op Amp CNU EE 0.-

2 Operational-Amplifier Introduction - Analog ICs : operational amplifiers, analog multipliers, analog-to-digital (A/D) and digital-toanalog (D/A) converters, phase-locked loops, etc. - Basic building blocks : single-stage amplifiers, differential pairs, current mirrors & MOS switches - CMOS op-amp : analog & mixed-signal VLSI circuits with high dc gain, wide bandwidth, or large output-signal swing ; utilized within an IC & loads are limited to small capacitances à do not need to have low output resistances; no danger of static charge damaging the gate oxide of input MOSFETs - Bipolar op-amp : general-purpose variety à 74-type of op amp for nearly 40 years Two-stage CMOS op amp - Simple but elegant circuit à the circuit has become a classic and is used in a variety of forms in the design of VLSI systems. - Multistage CMOS amplifier (section 7.6.) - st stage : Differential-amplifier circuit :. voltage gain in the range of 20V/V to 60V/V 2. conversion from differential to single-ended from while providing a reasonable common-mode rejection ratio (CMRR) - 2 nd stage : a gain of 50V/V to 80V/V - Frequency compensation of op amp : Compensation capacitance C C connected in a negative feedback path à introduction of a pole at a relatively low frequency & arrangement to dominate the frequency-response determination à open-loop gain is made to roll off with frequency at the uniform rate of -20dB/decade à op amp will operate in a stable fashion (as opposed to oscillating) when negative feedback of various amounts is applied CNU EE 0.-2

3 The circuit st stage : differential pair Q -Q 2 + current mirror load Q 3 -Q 4 Current mirror - Differential pair biased by current source Q 5 - A gain of 20V/V to 60V/V - Current mirror w/ Q 8, Q 5, Q 7 is fed by a reference current I REF 2 nd gain stage : common-source transistor Q 6 + current source load Q 7 - A gain of 50V/V to 80V/V Compensation Capacitance - Frequency compensation capacitance C C connected in the negativefeedback path of Q 6 à C C is Millermultiplied by the gain of 2 nd stage à st Amp. dominant pole by the interaction with the total resistance of the 2 nd stage Elimination of a systematic output I dc offset voltage : ( W ) ( W ) L 6 7 = 2 L 2 2 nd Amp. ( W ) ( W ) L 4 L 5 No output stage à drive only small on-chip capacitive loads CNU EE 0.-3

4 Relative levels of the terminal voltages of the enhancement-type NMOS transistor for operation in the triode region and in the saturation region Relative levels of the terminal voltages of the enhancement-type PMOS transistor for operation in the triode region and in the saturation region CNU EE 0.-4

5 - - Input common mode range Lowest value of V ICM = sufficiently large to keep Q & Q 2 in saturation à not be lower than drain voltage of Q (-V SS +V GS3 = -V SS +V tn +V OV3 ) by more than V tp Highest value of V ICM = Q 5 in saturation à V SD5 across Q 5 should not decrease below V OV5 = drain voltage of Q 5 should not go higher than V DD - V OV5 V V - V - V ICM DD OV5 SGI - Overdrive voltages subtract from the dc supply voltage à reduces the input common-mode range - V OV as low as possible is desired from a V ICM range point-of-view CNU EE 0.-5

6 Output swing - Lower end of output signal swing à keep Q 6 saturated - Upper end of output signal swing à keep Q 7 saturated Output voltage can swing to within an overdrive voltage of each of the supply rails. Output swing can be maximized by selecting values for V OV of Q 6 & Q 7 as low as possible CNU EE 0.-6

7 Voltage Gain ( st stage) Each of the Two stages à a transconductance amplifier Input resistance is infinite : = st stage transconductance G m = tansconductance of each of Q & Q 2 Since Q & Q 2 are operated at equal bias currents (I/2) & equal overdrive voltages, V OV = V OV2 R : output resistance of the st stage : Dc gain of the st stage : A = -G m R = -g m ( r o2 r R in o4 2 ) = - V R OV = r 2( I / 2) G m = = V OV G = g = g m m m2 I V OV VA2 VA4 ro 4 ro 2 = & ro 4 I / 2 I / 2 o 2 = é ê ë VA 2 + V A4 ù ú û A is increased by lower V OV of Q & Q 2 and larger Early voltage V A (longer channel length) à degrade the frequency response Small-signal equivalent circuit for the two stage op-amp CNU EE 0.-7

8 Voltage Gain (2 nd stage) 2 nd stage transconductance G m2 : R 2 : output resistance of the 2 nd stage : 2I G m2 = gm6 = V 2 é Voltage gain of the 2 nd stage : A2 = -Gm2R2 = -gm6( ro 6 ro 7) = - ê + VOV 6 ëva6 VA Overall dc voltage gain A v : order of (g m r o ) 2, in the range of 500V/V ~ 5000V/V A = A A = G R G R = g v D6 OV 6 V V A7 A7 R 2 = ro 6 ro 7 ro 6 = & ro 7 = = I D6 I D7 ( ro 2 ro 4) gm6( ro 6 r 7) 2 m m2 2 m o 7 V I ù ú û A7 D6 A 2 is increased by lower V OV of Q 6 & longer channel length of Q 6 & Q 7 à reduces the amplifier bandwidth Output resistance of the 2 nd stage is large (tens-of-kilohms range) R o = ro6 ro7 :: negative feedback samples the op-amp output voltage à output resistance is reduces by a factor equal to the amount of feedback (+Ab) & CMOS op amp are rarely drive heavy resistive load. Small-signal equivalent circuit for the two stage op-amp CNU EE 0.-8

9 Frequency response - Total capacitance between the output node of the st stage and ground : - Total capacitance between the output node of the op amp and ground : ; C L >> the other transistor cap. à C 2 >> C & C gd6 is ignored due to C C >> C gd6 & C C C gd6 - Two poles & a positive real-axis zero à f P : dominant pole formed by Miller-multiplied C C [i.e., (+G m2 R 2 )C C ~G m2 R 2 C C ] & R - Unity-gain frequency f t to achieve a uniform -20dB/decade gain rolloff down to 0dB f Simplified Equivalent Circuit - The uniform -20-dB/decade gain rolloff obtained at frequencies f >> f P à simplified equivalent circuit - Gain of the 2 nd stage, A 2 is large à virtual ground at the input terminal of 2 nd stage à 2 nd stage acts as an integrator fed with the output current signal of the st stage; G m V id G f m2 m2 f 2pR Gm2R2CC 2pC 2 2pCC Condition that f t must be lower than f P2 & f Z G C = C + C + C + C + C C + gd 2 db2 gd 4 db4 gs6 2 = Cdb6 + Cdb7 + Cgd 7 CL = m t Av f = m m2 P > < & Gm < Gm2 2pCC CC C2 G G G CNU EE 0.-9

10 Phase Margin Frequency compensation scheme for the two-stage CMOS amplifier = polesplitting type : dominant low-frequency pole with frequency f P and shifts the 2 nd pole beyond f t At the unity-gain frequency f t, the phase lag exceed 90 caused by the dominant pole at f P - æ f ö t Excess phase shift f ç P2 = - tan due to the 2 nd pole: è f P2 ø Right-half-plane zero: - æ f ö t f ç Z = - tan è fz ø Phase lag at f= f t : f total = 90 o + tan - - ( f f ) + tan ( f f ) t P2 t Z Phase margin: o PM = 80 -f - ( f f )- tan ( f f ) Magnitude of the phase margin significantly affects the closed-loop gain CNU EE 0.-0 = 90 o - tan - total t P2 t Z

11 Solution for the additional phase lag provided by the zero - Inclusion of R in series with C C à transmission zero is moved to other less-harmful locations - New location of transmission zero by setting V o =0 à Current through C C Vi R + sc æ ç è G 2 = GmVi 2 > s = CC m2 C ö - R ø - Zero is at infinite frequency by selecting R=/G m2 - Better selection of R > /G m2 àplace zero at a negative-real axis location where phase it introduces adds to the phase margin CNU EE 0.-

12 Slew rate Unity-gain follower with a step of V applied at the input Because of the amplifier dynamics, its output will not change in zero time à entire value of the step will appear as a differential signal between the two input terminals à Q 2 will turn off & Q will conduct the entire current I à Q 4 will sink a current I that will be pulled from C C A unit-gain follower with a large step input. Since the output voltage can not change immediately, a large differential voltage appears between the op-amp input terminals CNU EE 0.-2

13 Slew rate - Model of the two-stage CMOS op-amp when a large differential voltage is applied - Model of 2 nd stage = ideal integrator - Q 4 will sink a current I that will be pulled from C C - Output voltage will be a ramp with a slope of I/C C, and slew rate, SR : Relation between SR and f t f t G I I = SR = = 2pf tv 2p C m & Gm = gm = > CC VOV For a given unity gain bandwidth w t, the slew rate is determined by the overdrive voltage of the firststage transistor à Higher slew rate is obtained by operating Q & Q 2 at a larger overdrive voltage V OV à a larger V OV in p-channel devices for a given bias current I but lower G m ( st stage) & higher G m2 in n-channel device (2 nd stage) results in higher 2 nd -pole frequency & higher w t à a lower dc gain C OV = V OV w t CNU EE 0.-3

14 Folded-Cascode CMOS OP-Amp The circuit CS transistor + CG transistor of opposite polarity Single-stage op amp - differential pair Q -Q 2 + cascode transistors Q 3 -Q 4 - For differential input signal, Q -Q 2 à common source amplifier - Gate of Q 3 -Q 4 = constant dc voltage (V BIAS ) à signal ground - transistor pairs Q -Q 3 & Q 2 -Q 4 à folded-cascode amplifier - Bias current of Q -Q 2 = I/2, Bias current of Q 3 -Q 4 = (I B - I/2) à I B = I or I B is somewhat greater than I - Output resistance of current-source load à Cascode current mirror Q 5 -Q 8 - Load capacitance C L à frequency compensation CNU EE 0.-4

15 Folded-Cascode CMOS OP-Amp Input common mode range Two gate terminals of Q & Q 2 = V ICM Maximum value of V ICMmax = Q & Q 2 operate in saturation à V ICMmax is at most V tn volts above the drain voltage of Q & Q 2 à voltage drop across Q 9 & Q 0 is at least equal to their overdrive voltage, V OV9 = V OV0 V = V - + V ICM max DD VOV 9 Minimum value of V ICMmin = two-stage circuit V ICMmin is not sufficiently low due to threshold voltage V tn SS V + V ICM min OV tn = -VSS + VOV + VOV - V + V + V + V V V - + V OV tn ICM DD tn VOV 9 Output voltage swing Upper end of v o : Q 0 & Q 4 operate in saturation V BIAS : Q 0 operates at the edge of saturation v Omax is two overdrive voltages below V DD V v BIAS O max = V = V DD DD - V - V OV0 OV0 -V SG4 - V OV 4 tn Lower end of v o : Q 6 reaches the edge of saturation, when v o decreases below the gate voltage of Q 6 by V tn Gate voltage at Q 6 : -V SS + VGS7 + VGS5 or -VSS + VOV 7 + VOV Vtn > vo min = -VSS + VOV 7 + VOV 5 + Vtn v Omin is two overdrive voltages plus a threshold voltage above V SS à drawback of utilizing the cascode mirror CNU EE 0.-5

16 Voltage Gain Folded-cascode op ampà transconductance amplifier with an infinite input resistance : 2( I / 2) I G m = gm = gm2 G m = = VOV VOV output resistance R o : R = R R where ( g r )( r r ) & g r r Dc open-loop gain : Folded-Cascode CMOS OP-Amp o v = o4 [ g r ( r r )] ( g r r ) m4 o4 m o o6 o2 A = G R = -g 0 o4 m4 o4 m6 o6 o8 m6 o6 o8 Folded-cascode amplifier = transconductance amplifier à operational transconductance amplifier (OTA) : high output resistance (order of g m r o2 ) à relatively high voltage gain even in a single amplifier stage à ideal op amp with zero output resistance à negative feedback with voltage sampling type à output resistance is reduced by the factor (+Ab) where A=A v & b= o2 0 {[ g r r r )] ( g r r )} m m4 o4 ( o2 0 m6 o6 o8 o6 R R R = = of o = + Av Av Gm gm OTA has 00% voltage feedback g m ~ order of ma/v à R of ~ order of kw Small-signal equivalent circuit of the foldedcascode CMOS amplifier = operational transconductance amplifier (OTA) CNU EE 0.-6

17 Folded-Cascode CMOS OP-Amp Frequency response - Cascode configuration = excellent high-frequency response - Poles are at the input, at the connection between the CS and CG transistors (i.e., at the source terminals of Q 3 & Q 4 ) and at the output à first two poles are at very high frequencies - Primary purpose of CMOS op amp is to feed capacitive loads - Pole at the output becomes dominant because capacitive loads, C L is usually large Vo GmRo Gm = f f P : dominant pole P = ft = GmRo f P = Vid + sclro 2pC LRo 2pC L f t : unity-gain frequency - Design of C L : excess phase resulting from the nondominant poles is small enough to permit the required phase margin to be achieved at f = f t - Effects of increasing C L. two-stage circuit : C L à freq. of 2 nd pole à excess phase shift at f = f t à phase margin 2. folded-cascode : C L à f t à phase margin = heavier capacitive load decreases the bandwidth but does not impair its response (which happens when the phase margin decreases) CNU EE 0.-7

18 Folded-Cascode CMOS OP-Amp Slew rate Slewing occurs when a large differential input signal is applied Large signal V id is applied à Q 2 cut off & Q conducts the entire bias current I à Q 3 will carry (I B - I) & Q 4 conducts I B à (I B - I) through Q 5 & Q 7 and thus, (I B - I) in D of Q 6 by the current mirror à I 4 I 6 = I B - (I B - I) = I will flow into C L à v O will be a ramp with a slope of I/ C L which is the slew rate SR = I C L = 2pf tvov I B > I is to avoid turning off the current mirror completely; if the current mirror turns off, the output distortion increases. Typically, I B is set 0% to 20% larger than I CNU EE 0.-8