ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

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1 ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California, Davis ROBERT G. MEYER University of California, Berkeley JOHN WILEY & SONS, INC. New York / Chichester/ Weinheim /Brisbane / Singapore / Toronto

2 CHAPTER Comparison of Operating Regions Models for Integrated-Circuit Active of Bipolar and MOS Transistors Devices Decomposition of Gate-Source 1.1 Introduction 1 Voltage Depletion Region of a pn Junction Threshold Temperature Dependence Depletion-Region Capacitance MOS Device Voltage Limitations Junction Breakdown Large-Signal Behavior of Bipolar 1.6 Small-Signal Models of the MOS Transistors 8 Transistors Large-Signal Models in the Transconductance 50 Forward-Active Region Intrinsic Gate-Source and Effects of Collector Voltage on Gate-Drain Capacitance 51 Large-Signal Characteristics in the Input Resistance 52 Forward-Active Region Saturation and Inverse Active Output Resistance 52 Regions Basic Small-Signal Model of the MOS Transistor Transistor Breakdown Voltages Body Transconductance Dependence of Transistor Current Parasitic Elements in the Gain RF on Operating Conditions Small-Signal Model MOS Transistor Frequency 1.4 Small-Signal Models of Bipolar Response 55 Transistors Short-Channel Effects in MOS Transconductance 27 Transistors Base-Charging Capacitance Velocity Saturation from the Input Resistance 29 Horizontal Field Transconductance and Transition Output Resistance 29 Frequency Basic Small-Signal Model of the Mobility Degradation from the Bipolar Transistor 30 Vertical Field Collector-Base Resistance Weak Inversion in MOS Transistors Parasitic Elements in the 65 Small-Signal Model Specification of Transistor Frequency Response Drain Current in Weak Inversion Transconductance and Transition 1.5 Large Signal Behavior of Frequency in Weak Inversion 68 Metal-Oxide-Semiconductor 1.9 Substrate Current Flow in MOS Field-Effect Transistors 38 Transistors Transfer Characteristics of MOS Devices 38 A.1.1 Summary of Active-Device Parameters 73

3 xi CHAPTER 2 Bipolar, MOS, and BiCMOS n-channel Transistors 131 Integrated-Circuit Technology p-channel Transistors Introduction Depletion Devices Basic Processes in Integrated-Circuit Bipolar Transistors 142 Fabrication Passive Components in MOS Electrical Resistivity of Silicon Technology Resistors Solid-State Diffusion Capacitors in MOS Technology Electrical Properties of Diffused 145 Layers Latchup in CMOS Technology Photolithography Epitaxial Growth BiCMOS Technology Ion Implantation Heterojunction Bipolar Transistors Local Oxidation Polysi1icon Deposition Interconnect Delay Economics High-Voltage Bipolar of Integrated-Circuit Integrated-Circuit Fabrication Fabrication Advanced Bipolar Integrated-Circuit Yield Considerations in Integrated-Circuit Fabrication Fabrication Active Devices in Bipolar Analog Cost Considerations in Integrated Circuits 95 Integrated-Circuit Fabrication Integrated-Circuit npn Transistor Packaging Considerations for Integrated-Circuit pnp Transistors Integrated Circuits Maximum Power Dissipation Passive Components in Bipolar Reliability Considerations in Integrated Circuits 115 Integrated-Circuit Packaging Diffused Resistors 115 A.2.1 SPICE Model-Parameter Files Epitaxial and Epitaxial Pinch Resistors 119 CHAPTER Integrated-Circuit Capacitors 120 Single-Transistor and Multiple-Transistor Zener Diodes 121 Amplifiers Junction Diodes Device Model Selection for 2.7 Modifications to the Basic Bipolar Approximate Analysis of Analog Process 123 Circuits Dielectric Isolation Two-Port Modeling of Amplifiers Compatible Processing for 3.3 Basic Single-Transistor Amplifier High-Performance Active Devices Stages High-Performance Passive Common-Emitter Configuration Components MOS Integrated-Circuit Fabrication Common-Source Configuration Common-Base Configuration 2.9 Active Devices in MOS Integrated 183 Circuits Common-Gate Configuration 186

4 xii Contents Common-Base and Common-Gate Input Offset Current of 188 Configurations with Finite ro the Emitter-Coupled Pair Common-Base and 235 Common-Gate Input Input Offset Voltage of the Resistance 188 Source-Coupled Pair Common-Base and Offset Voltage of the Common-Gate Output Source-Coupled Pair: Ap- Resistance 190 proximate Analysis Common-Collector Configuration Offset Voltage Drift in the (Emitter Follower) 191 Source-Coupled Pair Common-Drain Configuration Small-Signal (Source Follower) 195 Characteristics of Common-Emitter Amplifier with Unbalanced Differential Emitter Degeneration 197 Amplifiers Common-Source Amplifier with A.3.1 Source Degeneration Elementary Statistics and 200 the Gaussian Distribution Multiple-Transistor Amplifier Stages The CC-CE, CC-CC, and Darlington Configurations 202 CHAPTER 4 Current Mirrors, Active Loads, and References The Cascode Configuration Introduction The Bipolar Cascode Current Mirrors The MOS Cascode eneraroperties Gl P 253 The Active Cascode 211 4,2,2 Simple The Current Mirror 255 Super Source Follower Bipolar Differential Pairs MOS The 257 do Transfer Characteristic of Simple Current Mirror with Beta an Emitter-Coupled Pair 215 Helper The do Transfer Characteristic with Emitter Degeneration Bipolar The do Transfer Characteristic of a MOS 262 Source-Coupled Pair Simple Current Mirror with Introduction to the Degeneration Small-Signal 262 Analysis of Differential Amplifiers Bipolar MOS Small-Signal 263 Characteristics of Balanced Differential Amplifiers Cascode Current Mirror Bipolar Device Mismatch Effects in Differential Amplifiers MOS Input Offset Voltage and Wilson Current Mirror 274 Current Bipolar Input Offset Voltage of the Emitter-Coupled MOS 277 Pair 232 4,3 Active Loads Offset Voltage of the Motivation 278 Emitter-Coupled Pair : Common-Emitter/Common-Source Approximate Analysis Amplifier with Complementary 232 Load Offset Voltage Drift in the Common-Emitter/Common-Source Emitter-Coupled Pair Amplifier with Depletion Load

5 xiii Common-Emitter/Common-Source 5.2 The Emitter Follower As an Output Amplifier with Diode-Connected Stage 344 Load Differential Pair with Transfer Characteristics of the Current-Mirror Load 287 Emitter-Follower Large-Signal Analysis Power Output and Efficiency Emitter-Follower Drive Small-Signal Analysis Requirements Small-Signal Properties of the Common-Mode Rejection Emitter Follower 355 Ratio The Source Follower As an Output 4.4 Voltage and Current References 299 Stage Low-Current Biasing Transfer Characteristics of the Bipolar Widlar Current Source Follower 356 Source Distortion in the Source Follower MOS Widlar Current 358 Source Bipolar Peaking Current 5.4 Class B Push-Pull Output Stage 362 Source MOS Peaking Current Transfer Characteristic of the Source 304 Class B Stage Power Output and Efficiency of the Supply-Insensitive Biasing 306 Class B Stage Widlar Current Sources Practical Realizations of Class B 306 Complementary Output Stages Current Sources Using 369 Other Voltage Standards All-npn Class B Output Stage Self Biasing Quasi-Complementary Output Temperature-Insensitive Biasing Stages Overload Protection Band-Gap-Referenced Bias Circuits in Bipolar 5.5 CMOS Class AB Output Stages 382 Technology Common-Drain Configuration Band-Gap-Referenced 383 Bias Circuits in CMOS Common-Source Configuration Technology 323 with Error Amplifiers 384 A.4.1 A.4.2 Matching Considerations in Current Mirrors 327 A Bipolar 327 A MOS 329 Input Offset Voltage of Differential Pair with Active Load 332 A Bipolar 332 A MOS Alternative Configurations Combined Common-Drain Common-Source Configuration Combined Common-Drain Common-Source Configuration with High Swing Parallel Common-Source Configuration 394 CHAPTER 5 Output Stages Introduction 344 CHAPTER 6 Operational Amplifiers with Single-Ended Outputs Applications of Operational Amplifiers 405

6 xiv Contents Basic Feedback Concepts Inverting Amplifier Noninvertin 5 Amplifier MOS Folded-Cascode Operational Amplifiers MOS Active-Cascode Operational Amplifiers Differential Amplifier Bipolar Operational Amplifiers Nonlinear Analog Operations The do Analysis of the Integrator, Differentiator 410 Operational Amplifier Internal Amplifiers Small-Signal Analysis of the Switched-Capacitor Operational Amplifier 461 Amplifier Input Offset Voltage, Input Switched-Capacitor Offset Current, and Integrator 416 Common-Mode Rejection Ratio of the Deviations from Ideality in Real Operational Amplifiers Design Considerations for Bipolar Mlithi onocperaonampers Otil 6.2 Alifi.1 Input Bias Current Input Offset Current Design of Low-Drift Operational Input Offset Voltage 421 Amplifiers Common-Mode Input Range Design of Low-Input-Current Common-Mode Rejection Ratio Operational Amplifiers 476 (CMRR) Power-Supply Rejection Ratio CHAPTER 7 (PSRR) 422 Frequency Response of Integrated Input Resistance 424 Circuits Output Resistance Introduction Frequency Response Single-Stage Amplifiers Operational-Amplifier Equivalent Circuit Single-Stage Voltage Amplifiers and The Miller 6.3 Effect 488 Basic Two-Stage MOS Operational The Bipolar Differential Amplifiers 425 Amplifier : Differential Input Resistance, Output Mode Gain 493 Resistance, and Open-Circuit The MOS Differential Voltage Gain 426 Amplifier : Differential Mode Gain 496 Output Swing Frequency Response of the Input Offset Voltage 428 Common-Mode Gain for a Common-Mode Rejection Ratio Differential Amplifier Frequency Response of Voltage Common-Mode Input Range Buffers Power-Supply Rejection Frequency Response of the Ratio (PSRR) 434 Emitter Follower Frequency Response of the Effect of Overdrive Voltages 439 Source Follower Layout Considerations Frequency Response of Current Buffers Two-Stage MOS Operational Common-Base-Amplifier Amplifiers with Cascodes 442 Frequency Response MOS Telescopic-Cascode Operational Common-Gate-Amplifier Amplifiers 444 Frequency Response 515

7 xv 7.3 Multistage Amplifier Frequency Local Shunt Feedback 591 Response The Voltage Regulator as a Feedback Dominant-Pole Approximation Circuit Zero-Value Time Constant 8.8 Feedback Circuit Analysis Using Analysis 517 Return Ratio Cascode Voltage-Amplifier Closed-Loop Gain Using Return Frequency Response 522 Ratio Cascode Frequency Response Closed-Loop Impedance Formula 525 Using Return Ratio Frequency Response of a Current Summary-Return-Ratio Analysis Mirror Loading a Differential Pair Modeling Input and Output Ports in Short-Circuit Time Constants 533 Feedback Circuits Analysis of the Frequency Response of the 741 Op Amp 537 CHAPTER High-Frequency Equivalent Circuit Frequency Response and Stability of of the Feedback Amplifiers 624 Calculation of the -3-dB Frequency of the Introduction Nondominant Poles of the Relation Between Gain and 540 Bandwidth in Feedback Amplifiers 7.5 Relation Between Frequency 624 Response and Time Response Instability and the Nyquist Criterion 626 CHAPTER Compensation 633 Feedback Theory of Compensation Ideal Feedback Equation Methods of Compensation Gain Sensitivity Two-Stage MOS Amplifier 8.3 Effect of Negative Feedback on Compensation 644 Distortion Compensation of Single-Stage 8.4 Feedback Configurations 557 CMOS OP Amps Series-Shunt Feedback Nested Miller Compensation Shunt-Shunt Feedback Root-Locus Techniques Shunt-Series Feedback Root Locus for a Three-Pole Series-Series Feedback 562 Transfer Function Rules for Root-Locus Construction 8.5 Practical Configurations and the Effect 667 of Loading Root Locus for Dominant-Pole Shunt-Shunt Feedback 563 Compensation Series-Series Feedback Root Locus for Feedback-Zero Compensation Series-Shunt Feedback Slew Rate Shunt-Series Feedback Origin of Slew-Rate Limitations Summary Single-Stage Feedback Methods of Improving Slew-Rate Local Series Feedback

8 xvi Contents Improving Slew-Rate in Bipolar Op Amps Shot Noise Improving Slew-Rate in MOS Op Thermal Noise 752 Amps Flicker Noise (11f Noise) Effect of Slew-Rate Limitations on Burst Noise (Popcorn Noise) 754 Large-Signal Sinusoidal Performance Avalanche Noise 755 A.9.1 Analysis in Terms of Return-Ratio 11.3 Noise Models of Integrated-Circuit Parameters 691 Components 756 A.9.2 Roots of a Quadratic Equation Junction Diode Bipolar Transistor 757 CHAPTER MOS Transistor 758 Nonlinear Analog Circuits Resistors Introduction Capacitors and Inductors Precision Rectification Circuit Noise Calculations Analog Multipliers Employing the Bipolar Transistor Noise Bipolar Transistor 708 Performance Equivalent Input Noise and the The Emitter-Coupled Pair as a Minimum Detectable Signal 766 Simple Multiplier Equivalent Input Noise Generators The do Analysis of the Gilbert 768 Multiplier Cell The Bipolar Gilbert Cell as an Transistor Noise Analog Multiplier Generators MOS 10.3 Transistor Noise Generators.4 A Complete Analog Multiplier The Gilbert Multiplier 11.6 Effect of Cell as a Feedback on Noise Balanced Modulator and Phase Performance 776 Dectector Effect of Ideal Feedback on Noise 10.4 Phase-Locked Loops (PLL) 720 Performance Effect of Practical Feedback on Phase-Locked Loop Concepts Noise Performance The 11.7 Phase-Locked Noise Performance of Loop in the Other Transistor Locked Condition 722 Configurations Integrated-Circuit Phase-Locked Common-Base Stage Noise Loops 731 Performance Analysis of the 560B Monolithic Emitter-Follower Noise Phase-Locked Loop 735 Performance Nonlinear Differential-Pair Function Noise Symbols 743 Performance Noise in Operational Amplifiers 788 CHAPTER Noise Bandwidth 794 Noise in Integrated Circuits Noise Figure and Noise Temperature 11.1 Introduction Sources of Noise Noise Figure Noise Temperature 802

9 CHAPTER CMFB Using Transistors in the Fully Differential Operational Amplifiers Triode Region Switched-Capacitor CMFB Introduction Fully Differential Op Amps Properties of Fully Differential A Fully Differential Two-Stage Op Amplifiers 808 Amp Small-Signal Models for Balanced Fully Differential Telescopic Differential Amplifiers 811 Cascode Op Amp Common-Mode.6.3 Fully Differential Folded-Cascode Feedback 816 Op Amp Common-Mode Feedback at Low A Differential Op Amp with Two Frequencies 817 Differential Input Stages Stability and Compensation Neutralization 849 Considerations in a CMFB Loop Unbalanced Fully Differential Circuits 12.5 CMFB Circuits CMFB Using Resistive Divider 12.8 Bandwidth of the CMFB Loop 856 and Amplifier CMFB Using Two Differential Index 865 Pairs 828 xvii

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS

ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS ANALYSIS AND DESIGN OF ANALOG INTEGRATED CIRCUITS Fourth Edition PAUL R. GRAY University of California, Berkeley PAUL J. HURST University of California, Davis STEPHEN H. LEWIS University of California,

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