You will be asked to make the following statement and provide your signature on the top of your solutions.

Transcription

1 1 EE 435 Name Exam 1 Spring 216 Instructions: The points allocated to each problem are as indicated. Note that the first and last problem are weighted more heavily than the rest of the problems. On those problems that need technology parameters, assume you are working in a.5µm CMOS process with process with ncox=1 A/v 2 pcox=3 A/v 2,VTNO=.8V, VTPO= -.8V, COX= =2fF/ 2, =.1v -1, Cbdbot =.5fF/ 2, and Cbdsw = 2.5fF/. As a take-home exam, all work on this exam must be done individually. There should be no collaboration with anyone except for the course instructor, R. Geiger, should there be any questions. Since this is a take-home exam, please address any questions you may have by to the course instructor. An immediate response can not be promised but I will check my periodically throughout the weekend. You will be asked to make the following statement and provide your signature on the top of your solutions. All of the work on this exam is my own and I did not collaborate with anyone about this exam except possibly with the course instructor signature here Problem 1 (2 points) The operational amplifier has been designed with VEB = 25mV for all transistors with a total power dissipation of 2mW when biased with a single 5V supply (i.e. VDD=5V). The load capacitor is CL=2pF and the length of all transistors is 4µm. a) Determine the GB of the op amp b) What is the W/L ratio of M1? c) Determine either VB2 or VB3? d) Express the dc gain in terms of the small-signal model parameters of the devices. e) Give a numerical value for the dc gain of this op amp. f) What is the 3dB bandwidth? g) What is the slew rate of the op amp? V DD M 5 M 6 M 7 M 8 V B2 M 3 M 4 C L M 1 M 2 I T V B3 M 11

2 2 Problem 2 (1 points) A large number of different op amp architectures were identified in class. A table summarizing some of the more popular possible structures is shown below. Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 1 Tail Voltage Bias Tail Current Bias Common Source Current Mirror Differential Input Single-Ended Input Differential Output Single-Ended Output Stage 2 Tail Voltage Bias Tail Current Bias Internally Compensated p-channel Input Output Compensated n-channel Input a) Give the schematic of a two-stage op amp with a telescopic cascode first stage, a common source second stage, with a differential inputs and singleended output on the first stage. Use n-channel inputs on the first stage and p- channel inputs on the second stage. Use tail current bias on the first stage and tail voltage bias on the second stage. Use output compensation. Assume the total output capacitance (including any compensation capacitance) is CL. b) Give an expression for the dc gain of the amplifier in part a) in terms of the small signal model parameters and in terms of the practical design parameters. c) Give an expression for the GB of the amplifier in terms of the small signal model parameters and in terms of the practical design parameters.

3 3 Problem 3 (1 points) The magnitude and phase plot of a differential input, single-ended output all-pole operational amplifier is shown below. a) Determine the phase margin if this is used in a feedback amplifier with a feedback factor of β=.1 b) Is the feedback amplifier stable? Why? c) What is the maximum value of β that can be used if the amplifier is to have a 75 o phase margin? d) If β =.1, what is the ideal dc closed loop gain if configured as a basic noninverting feedback amplifier and what is the percent closed-loop gain error due to the finite dc gain limitations of the op amp? e) How many poles does this amplifier have? Gain Magnitude in db Phase in Degrees ω

4 4 Problem 4 (1 points) β =.1 Generate the Nyquist plot for the amplifier of Problem 3 if Problem 5 (1 points) Assume the resistors in the amplifier shown were selected so that the gain of the feedback amplifier is 4 when the op amp is ideal. If an ideal transconductance amplifier with a transconductance gain of GT is used for the op amp (as shown in the second figure below), how large must GT be so that the gain of the feedback amplifier differs by at most 1% from the desired value of 4? Assume the resistor values are large so that the β network does not load the transconductance amplifier. R 1 R 2 V 1 R 2 R 1 G T Problem 6 (1 points) An all-pole amplifier has two open-loop poles, one at 1Hz and the other at 1MHz and the dc gain of the amplifier is 9dB. If used in a feedback application in a closed-loop amplifier with β=.2, determine the a) phase margin b) Q of the closed loop poles Assume the closed-loop gain satisfies the standard Black feedback expression As AFB 1 As where A(s) is the open-loop gain of the op amp. (Note: the pole locations specified above are really at -1Hz and at -1MHz but the -_ sign is often ignored when referring to open-loop poles) Problem 7 (1 points) Consider a feedback amplifier where the gain with As feedback satisfies the standard Black feedback equation AFB. Assume further 1 As

5 5 that the open-loop amplifier is a two-pole amplifier with gain As where k A s s 1 1 p1 kp1 is the ratio of the open-loop poles. a) sketch a root locus plot of the closed-loop poles for <β<1. In this sketch, assume the pole ratio k satisfies the relationship k>>1. b) Determine the Q of the closed-loop poles if β=.5, A=1, and k=15,. (as stated in part a) there is no value given for A or k. I had expected this sketch to be parametric but if you find it more convenient you may use the values for A and k given in part b)) Problem 8 (2 points) Consider the two-stage internally compensated op amp shown below where the compensation capacitor CC is selected so that the dominant pole of the open-loop amplifier is on the internal node and the ratio of the two open loop poles, k, satisfies the equation k =3βA where A is the dc open loop gain of the op amp and where β is the standard feedback factor. If the total power, P, is fixed, the designer must determine how to split the total power between the first stage and the second stage. If the total power in the op amp is P then θp is the fraction of the total power that is in the second stage where <θ<1. Assume CL and β are fixed. a) Plot the GB of the op amp for.1<θ<.9 for a fixed P. b) Comment on how the power should be allocated between the first and second stages if the GB requirement is fixed. Assume the goal is to minimize the total power required. V DD M 3 M 4 M 5 M 1 M 2 C C C L I T V B2 M9 V B3 M 6 V SS