Common Gate Stage Cascode Stage. Claudio Talarico, Gonzaga University

Transcription

1 Common Gate Stage Cascode Stage Claudio Talarico, Gonzaga University

2 Common Gate Stage The overdrive due to V B must be consistent with the current pulled by the DC source I B careful with signs: v gs = v bs = -v i V DD R LD V o C gd +C db R LD Vo V B (grounded) G & B D -(g m +g mb )v i S i i R i RC S i I B i i i + v i - C gs +C sb +C i Driving Circuit (e.g. photodiode) Define: C S = C gs + C sb + C i = g m + g mb R i models finite resistance in the driving circuit C i models parasitic capacitance in the driving circuit C D = C gd + C db enhanced g m due to both gates EE 303 Common Gate Stage 2

3 Common Stage Bias Point Analysis Assume R i is large: (very reasonable for a reverse biased photodiode) I D I B I B I D = V OUT = V DD R D I B 2 µc W OX L (V V GS t )2 V t = V t 0 +γ ( PHI +V SB PHI ) V SB = V S V B V DD R D V OUT V GS = V t + I B 0.5µC OX W / L V S = V B V GS = V B V t I B 0.5µC OX W / L A precise solution requires numerical iterations. Since the dependency of V t on V S is weak a few iterations are satisfactory for hand calculation V S Once V S is computed we can check that M operates in saturation: R i I B V DS = V OUT V S > V Dsat = V GS V t EE 303 Common Gate Stage 3

4 CG biasing () Example: V DD = 5V; V B = 2.5V; I B = 400µA; R D =3KΩ; W=00µm; L=µm; V t0 = 0.5V * CG stage * filename: cgbias.sp * C. Talarico, Fall 204 *** device model.model simple_nmos nmos kp=50u vto=0.5 lambda=0. cox=2.3e-3 capop=2 + cgdo=0.5n cgso=0.5n cj=0.m cjsw=0.5n pb=0.95 mj=0.5 mjsw= acm=3 cjgate=0 hdif=.5u gamma=0.6 PHI=0.8 *** useful options.option post brief nomod accurate *** circuit VDD vdd 0 5 * IB vi 0 dc 400u VS vi 0 dc.3077 *** value for.op analysis VB vb 0 dc 2.5 *** d g s b mn vo vb vi 0 simple_nmos w=00u l=u Rd vdd vo 3k *** calculate operating point.op *** large signal analysis (sweep Vi).dc VS element 0:mn model 0:simple_n region Saturati id u ibs f ibd f vgs.923 vds vbs vth m vdsat m vod m beta m gam eff m gm m gds u gmb u cdtot f cgtot f cstot f cbtot f cgs f cgd f!.end! EE 303 Common Gate Stage 4

5 CG biasing (2) DC Transfer Function um Technology M cut-off M saturation V out [V] M triode V in =V s [V] V B -V t The I/O characteristic is flipped w.r.t. the CS stage (small signal voltage gain A V = dv out /dv in is positive!) EE 303 Common Gate Stage 5

6 CG small signal model Depending on how the CG is used the output variable of interest may be: - The current that flows into the output (Current Buffer) - The voltage at the output (Transresistance Amplifier) careful with signs: v bs =v gs = -v s D C D R D v out g mb v bs g m v gs G G & B v s S Z D = R D + sr D C D = sc D + R D i s rr s s C S Z S = + s C S = sc S + EE 303 Common Gate Stage 6

7 CG input impedance () First pass: Z S in to v test so let s temporarily remove it i o = i test KCL@v o : w.r.t. (g m >> ) g m v s = g v test gs C S + v o - RZ LD 0 = v o + v o v test v test v o ( Z D )v test Z D + v gs - S KCL@v test : w.r.t. (g m >> ) v test Y in i test = v test + v test v o Aside: if g m is not >> v test i test = + Z D + i test v test Z D (Z D + ) = Z D + EE 303 Common Gate Stage 7

8 Final Pass: Let s bring back Z S : CG input impedance (2) i o = i test CZ Ss + v gs - v gs S + v o - Y in g' r m o + sc S + = g m v s = g m v test Z D + RZ LD + sc " % S + $ R D '+ # sc D & v test Y in Z in " % + $ R D ' # sc D & sc S g m >> (always true with our technology!!) EE 303 Common Gate Stage 8

9 CG input impedance: Summary () Z in " % + $ R D ' # sc D & sc S At low frequency: R in + R D Two interesting cases: - R D << R in Typically >> /g m If not most of the driving current instead of going to the MOS is lost!! Well known result! - R D is not << This happen quite often!! (example: R D is a current source load) Not so Well known EE 303 Common Gate Stage 9

10 CG input impedance: Summary (2) Z in " % + $ R D ' # sc D & sc S At high frequency - As long as R D << (regardless of the term C D ) Z in sc S Typically >> /g m sc S NOTE: R D If R D << so is is always < than R D. sc D R D sc D EE 303 Common Gate Stage 0

11 CG output impedance () At low frequency w.r.t. (g m >> ) D R out i test = v test v s v s i test v s = i test -g v gs v s v test C S + v gs - S R out = v test i test (+ ) G & B (Very high if g m >> ) Aside: if g m is not >> R out = v test i test = + (+ ) R out = v test i test EE 303 Common Gate Stage

12 CG output impedance (2) At high frequency D R out C S -g m v s v gs S C D i test v test ( " Z out * + $ ) # sc S % + '- &, sc D + v gs - C S G & B Typically C S /(g m ) << C D If g m R s >> Z out sc s sc D sc D EE 303 Common Gate Stage 2

13 CG current transfer () w.r.t. (g m >> ) i out = v s v out + v s R D i out + g m 'v s i out! + R $ D # & v s " % NOTE : for >> R D i out g m 'v s The CG stage is approx. unilateral i out EE 303 Common Gate Stage 3

14 CG current transfer (2) i in =g m v s CG stage model valid for: g m v s g m >> and >> R D i out At low frequency: - for g m >> and >> R D ) i out i s = i out i in i in i s + Typically g m >> This is a current buffer!!! A I0, R in small, R out large EE 303 Common Gate Stage 4

15 CG current transfer (3) Z in * CG Core Z out v s i out v out i s rr s S C gs +C sb /g m g m v s C gd +C db R D C s i in i o C d At high frequency: - for g m >> and >> R D! # since R D > R D " $, >> R D implies >> Z D & sc D % i o i s v s = " % $ + sc S + 'v s # & + s C S + = A I 0 s p = + C + s S + EE 303 Common Gate Stage 5

16 CG current transfer (4) Z in * CG Core Z out v s i out v out i s rr s S C gs +C sb /g m g m v s C gd +C db R D C s i in i o C d i out i s i out i s = i out i o i o i s " + sc D R D $ # sc D + R D sc D % ' & ( ) + s C S Typically g m >> + C + s S + g' = m + sc D R D + C + s S + A I0 s p 2 s p EE 303 Common Gate Stage 6

17 CG Input-Output RC Time Constants i o + C S v gs v >> o R LD C D - + v gs - Y in vi test S For this specific configuration and assumptions ( >> R D and g m >>) input and output are decoupled à RC time constants are = /poles - Input RC: ~C S (/g m ) ( >>/g m ) - Output RC: R D C D EE 303 Common Gate Stage 7

18 CG Frequency Response ( db) AC response CS stage vs. CG stage 3.39GHz (7.89 db) MHz Gain [db] CS stage CG stage freq [Hz] A v0_cs g m R D A v0_cg g m R D EE 303 Common Gate Stage 8

19 CG Summary Current gain is about unity up to very high frequencies - The CG stage absorbs most of the current from the input source and it passes the current to the output terminal The CG does not contain a FB capacitance between input and output (no Miller effect) - The effect of large values of R D on the frequency response in much less than in CS stage (for a desired BW we can extract more gain out of the CG stage) Input impedance is typically very low (R in /g m ) At least when the output is terminated with some reasonable impedance (R D << ) Can achieve very high output resistance (R out g m ) In summary, a common gate stage is ideal for turning a decent current source into a much bettene Seems like this is something we can use to improve our common source stage Which is indeed nothing but a decent (voltage controlled) current source EE 303 Common Gate Stage 9

20 Aside If we cannot assume >>R D, the unilateral model used for the CG stage falls apart. Computing the current transfer gain is a little harder. i in R 2 i out - i out i S + v in - /g mm + v out - R LD i out i s = (+ ) R D gg m v m v in pp.3-4 Murmann s Textbook The poles of the circuit are no longer isolated. However, computing the bandwidth using ZVTC is not too difficult. '! + R $ * D )# &, r τ= C o S )# # + &, ), & ( )" % +, and τ 2 = C D '( ( + (+ )) R D * + EE 303 Common Gate Stage 20

21 Cascode Stage (CS + CG) One of the most important application of the CG. M is a transconductor (i =g m v in ) and M 2 buffers the current fed by M (i 2 i ) V B R o v out D 2 i 2 M 2 + Low-frequency, small-signal equivalent circuit v out G m = i out v in = i 2 i i v in = i 2 i g m g m G v in i M G m v in v in - R o R o 2 2 G m R o g r g' r g m o m2 o2 ( r m o) 2 Super transistor (Cascode) S Intrinsic gain of cascode EE 303 Common Gate Stage 2

22 Low Frequency Benefits R Output resistance very high ( g m 2 ) - The cascode device shields the input device from voltage variations at the output node V o V B V o M2 -g m2 ΔV x (ΔV ΔV x )/2 2 2 /g m C gd Z x ΔV x ΔV x V i V x M ΔI # & % ( $ g' ΔV x = ΔV m2 ' << ΔV # & % (+ 2 $ 2 ' - application: precision current source/mirror Intrinsic gain very high (g m ) 2 - application: OTA/OA Input resistance of CS stage (R in ) EE 303 Common Gate Stage 22

23 High Frequency Benefits R v x v i = g m Z x )# % * + $ ( ) g m + C db2+ C gd2 g m2 2 >> 2 # + R &&, % ( $ r ( o2 ''. -. V B C gd gd V i C gs M2 Z x V x M V o C db+ C gs2+ C sb2 For moderate value of R: v x /v i very close to - - Mitigates Miller effect (C in C gs + 2C gd ) - Even if R is large, there is often a load capacitance that provides a low impedance termination to help maintain t his feature (R is AC shorted by the load capacitance) For not so moderate values of R (R 2 ): v x /v i very close to -2 - Still mitigate Miller effect quite a bit (C in C gs +3C gd ) Additional benefit - Cascode mitigates direct forward coupling from V i to V o at high frequencies (RHP zero at z=+g m /C gd ) I Cgd = sc gd (V i V x ) if we could make V i V x I Cgd 0 which would be the same as cancelling the zero!! EE 303 Common Gate Stage 23

24 Example Revisited.8V 5V What we expect to see after adding the cascode device Relatively small R in (~/g mc ) v i V I R i V BCAS I B MNC 20/ MN 20/ V o V B R Bandwidth should increase (reduction of Miller effect) Easy to compute using a ZVTC analysis Non-dominant pole around some fraction of f T of cascode device Drain current of MN runs into a current divider between /g mc and total capacitance at this node (dominated by C gs of MNC) V B = 0.9V; V I = 0.627V; V DD =.8V; V BCAS =.077V; I B = 400µA; R = 2kΩ; R i = 0kΩ; W/L = 2.34 µm/0.8 µm EE 303 Common Gate Stage 24

25 Simulated Frequency Response 50 AC Response CS stage vs. Cascode 0 Magnitude [db] poles and a zero 2 poles and a zero 200 w/o cascode with cascode Frequency [Hz] 3-dB bandwidth increased from MHz to MHz ( 2.34x) gain_cs = 7.84 db; gain_cas = 8.40 db EE 303 Common Gate Stage 25

26 Supply Headroom Issue () V BCAS V DD R V o V DS2 >V DSsat2 Even if we adjust V BCAS such that V DS is small, adding a cascode reduces the available signal swing This can be a big issue when designing circuits with V DD V Typically need each V DS >~0.2V V i V DS >VV DSsat2 DSsat EE 303 Common Gate Stage 26

27 Source: Razavi Supply Headroom Issue (2) Is the issue really as bad as it sounds? For a given bias current, let s compare the price of increasing gain using cascoding vs. the price of increasing gain augmenting the transistor s length in a CS stage I D = 2 µc OX W L V 2 OV g m = 2I D V OV L I D Example: let s quadruple L (if we quadruple L, to maintain the same I D we need to double V OV ) increasing by increasing L + 2V ov g m,, V OV cs stage Very Interesting result: g m /2, 4, 2V OV cascode - By quadruplicating L we consume an extra V OV of headroom, (we consume 4x more area), and we get a 2x increase in the intrinsic gain ( 2g m ) - By cascoding we also consume and extra V OV of headroom, (we consume only 2x more area), but we get a significant better intrinsic gain ( g m ) 2 - EE 303 Common Gate Stage 27

28 Cascode Bias Analysis M saturation: V x > V in V T V x = V B V GS2 > V in V T V B > V in - V T + V GS2 M 2 saturation: V out V x > V GS2 V T2 Source: Razavi V out > V B V GS2 + V GS2 V T2 V out > V in V T +V GS2 V T2 = V x = V OV = V OV2 The minimum output DC level for which both transistors operate in saturation is: V out (min) = V OV + V OV2 EE 303 Common Gate Stage 28

29 I/O DC characteristic of cascode stage Example: V DD =5V, V B = 3V, W/L = 20µm/µm, R D =5KΩ V DD M off DC Transfer Function um Technology V DD -V T2 V out, V x [V] M 2 sat. M sat. V out V x V out (max) = V DD V out (min) = V OV + V OV2 M 2 (nmos) passes a degraded V DD M triode M 2 triode V in [V] As V in assumes sufficiently large values - V x drops below V in by V T forcing M into triode - V out drops below V B by V T2 forcing M 2 into triode Depending of the device dimensions and the values of R D and V B one effect may occur before the other EE 303 Common Gate Stage 29

30 Detailed Transistors operation 6 M operation V ov V ov, V ds [V] off sat. triode V ds all M 2 current goes into charging cap. at node x V ov2, V ds2 [V] sat. V in [V] M2 operation triode V ov2 V ds V in [V] EE 303 Common Gate Stage 30