ADVANCED ANALOG CIRCUIT DESIGN TECHNIQUES

Transcription

1 ADVANCED ANALOG CIRCUIT DESIGN TECHNIQUES By Edgar Sánchez-Sinencio Oice 318-E WEB When: Tuesday and Thursday 8:00-9:15am Where: WEB 049 1

2 Advanced Analog Circuit Design Required background: Techniques 1. How to optimally bias your CMOS circuits 2. How to use MOS transistor models 3. Derive transer unctions rom small signal circuits - Use o nodal admittance matrix 1. Stability Criteria. - How to determine pole and zeros.? - Routh Hurtwitz Criteria - Reduction o a higher-order system into a 2nd-order unction 1. How to design: 1. Inverting Ampliiers 2. Current mirrors and current sources 3. Dierential pairs, and low noise ampliiers 4. Simple Transconductor Ampliiers 5. Two Stage Conventional Operational Ampliiers Analog and Mixed Signal Center, TAMU (ESS) 2

3 6. Basic common-mode eedback structures or Fully Dierential Operational Ampliiers 7 Common Mode Feedback Concept Required background (continues): Use CADENCE or Noise Analysis Monte Carlo Analysis S/N ratio determination Pole and zero determination Temperature eects Use o non-linear dependent sources Use o SIMULINK or systems analysis, modeling and characterization Analog and Mixed Signal Center, TAMU (ESS) 3

4 What is the motivation? The knowledge and applications o analog circuits in medical electronics, modern mixed-signal IC chips or multimedia, energy harvesting, wearable devices, instrumentation and telecommunications are vital design element o any practical and commercial system. What are the challenges in designing low voltage circuits? - To perorm with technologies smaller than 40 nm - To operate with power supplies smaller than 1 volt - To design circuits with the same perormance or better than circuits designed or larger power supplies -To generate new design alternatives Analog and Mixed Signal Center, TAMU (ESS) 4

5 Why Low-Voltage Analog Integrated Circuits? Modern CMOS eature size is continuing to be scaled down to have a high T and large component density. In addition the maximum allowable power supply voltage continuously decreases. Thereore portable batterypowered equipment also necessitates low-voltage lowpower circuit design. 5

6 6

7 7

8 Year o Technology Forecast (rom ITRS Roadmap 2009) Production Supply Voltage(V)# DRAM ½ Pitch (nm) (contacted) / / / Gate length(nm) 37/250 28/180 22/180 Threshold Voltage (V) Gm/gds at 5(10)Lmin 1/ noise (uv 2.um 2 /Hz) (220) 30(160) 30(160) 100/500 80/180 70/180 NFmin(dB) 0.20 <0.2 <0.2 Peak Ft (GHz) 240/40 320/50 400/50 Peak Fmax (GHz) 370/40 480/50 590/50 # one data is or Perormance RF/Analog and the other or Precision Analog/RF Driver 8

9 ( continues) Why are we concerned in designing low voltage circuits? - Designers could not use conventional cascode structures, and other conventional design methodologies yielding high signal swing. - Circuits must have the same perormance or better than circuits designed or larger power supplies - Circuit perormance with technologies smaller than 65 nm must be better than circuits or larger technologies. -Fourth-generation communication applications require circuits ( and systems) with improved dynamic range over a much wider bandwidth. - New building blocks and systems must be designed to satisy the needs o portable, lighter, cheaper and aster products 9

10 Remarks.- Power supply reduction helps digital circuits or power consumption but hurts analog voltage swing which should not be reduced. Inherent transistor voltage gain decreases with reduced size technology, this implies larger number o stages to compensate the overall voltage gain. Threshold voltages do not reduce linearly with size o technology, making the design with low VDD harder or analog circuits Year o Production Threshold Voltage (V) AMSC-TAMU by Edgar Sánchez-Sinencio 10

11 Concerns about low power supply voltage VTH Scaling down size technology and supply voltage does not scale linearly the VTH hat VTH Mister 3.3 volts IC Mister 0.5 volts IC Also VDSAT does not scale down linearly with power supply nor with smaller size technologies. 11

12 Remarks on low power supply voltage integrated circuits Technology trends show that in every generation: Circuit delay is scaling down by 30% Supply voltages are also scaling by 30% Transistor s threshold voltage is reduced by nearly 15% Transistor density and digital perormance are double approximately every two years. Higher power dissipation and temperature. Reerence. W. M. Elgharbawy and M. A. Bayoumi, Leakage Sources and Possible Solutions in Nanometer CMOS Technologies IEEE Circuits and Systems Magazine, pp. 6-15, Fourth Quarter

13 LOW VOLTAGE ANALOG DESIGN TECHNIQUES When transistors operate in saturation, how deep in saturation should they operate? i.e. PMOS Vds >Vgs-Vt? By how much? How can one answer this question? Can one model transistor with one equation valid or all regions o operation? I LV circuits do not allow cascode circuits, what are the alternatives? -Floating Gate - Bulk Driven - Bulk Bias - Nested Gm-C ( cascade plus optimal eedback compensation) - Sel Cascode Transistor - NP Dierential Pairs 13 Analog and Mixed Signal Center, TAMU (ESS)

14 TRANSISTOR REGIONS OF OPERATION How to determine how much bias current is needed or certain application? When a designer operates transistors in saturation, what does it mean VDS > VDS(SAT)? Can a circuit have their transistors operating in the (moderate inversion) transition region? What transistor model equation can be employed? 14

15 One Equation-All Regions Transistor Model Features o ACM model: physics-based model, universal and continuous expression or any inversion level independent o technology, temperature, geometry and gate voltage, same model or analysis, characterization and design. Main design equations: (design parameters: I, g m, i ) I g t T W L W L m 1 1 i n 2 t 2 1 i L g C m ox V DSAT i t 2C t 1 1 i ox gm I t t g m 1 1 n I transistor drain current g m transconductance in saturation n slope actor t thermal voltage inversion level o the transistor deined as i t i I I s, where I s ncox is the 2 L normalization current. i << 1 weak inversion, i >> 1 strong inversion. 2 W 15

16 Current-based MOSFET model(drain current split into a orward and a reversed term: I D I F I W 1 I C V nv V L 2n VGB VT 0 VDB n Forward saturation I F I R and R 2 F ( R) ox GB SB( DB) T 0 I D Normalized output characteristic: I F V 1 i 1 DS 1 i 1 ir ln t 1 ir 1 I W L F(R) i (r) IS ISQ IS I SQ =technological parameter (slightly dependent on V G ) 16

17 The Saturation Voltage A V DSSAT t gms gmd ln = gain in CG coniguration 1 A 1 1 i 1 A 1 1 saturation level A 10 1 Strong inversion V i ( V V DSSAT t t G T / ) n 10 0 VDSsat V DSAT i t Weak inversion V.ln t DSSAT A 10-1 A = 100 A = 30 A = Inversion level i- 17

18 Drain Current and Aspect Ratio g 2 m GBW CL 1 1 ID gm n i t W g 1 1i m L C ox t i d 10-1 I BIAS 2 g m n t W L g 2 m C ox t Normalized I D and W/L vs. i 4 i d WI (i 1) MI (i =8) SI (i 1) I D 1/2 1 normalized I D i /4 normalized W/L W/L 4/ i 1 2/ i 18

19 Correlation Between Area and Frequency Response WL 2 CL C ox GBW T Correlation Between Junction Capacitance (CJ) and Frequency Response Parasitic capacitance GBW/ T CJ CJ W L DIF L DIF W CJ CL CJ 2 C ox L L DIF GBW T CJ 19

20 BIPOLAR MOS I BIAS =I C I BIAS =I D DC Circuit + V I - CL + V O - + V I - CL + V O - Transconductance -to-current-ratio (g m /I D ) DC Gain (A vo ) Gain-Bandwidth Product (GBW) Intrinsic Cuto Frequency ( T ) A g I vo GBW m 1 C t VA t I C 1 2CL 1 2 t gm 1 2 I n1 1i A D t vo VA t n 2 1 1i 1 ID 2 GBW 2CL t n1 1i 1 T T 2 1 i 1 2 Minimum Output Voltage (V O ) V CEsat t VDSsat 6 to 8 i t

21 21

22 Design Methodology 1 - Select the inversion level (i ) or 'optimal' design (I D, W/L). 2 - Choose both W and L. I T GBW, add the parasitic capacitances (CJ, Cov) to CL. 1 1 ID gm n i t 2 W g m 1 L C ox t 1i 1 V DSsat CJ Cov 1 2 CL LC t 1 i 1 4 ox CJL DIF CGDO GBW T 3 - Veriy i the spec or A vo is met. Otherwise, increase the channel length and/or reduce i d (cascode/cascade design can be necessary). 4 - Take into account V DSsat and the parasitic capacitance o the current source. 22

23 Process technology to choose Cost Perormance Compatibility Design approach and testing time Floating Gate Bulk-driven LV techniques Region o operation Weak inversion Moderate inversion Ohmic region Saturation ( strong inversion) 23

24 Small Size Technology The good news is that we will be able to run our ICs aster i.e., circuit delay is scaling down by 30% every generation. The bad news is that leakage power dissipation increases in a much aster rate than dynamic power Power (W) Active Power Leakage Power

25 Example: 90nm sub-threshold leakage increases exponentially with every 65mV decrease in threshold voltage 25

26 LEAKAGE SOURCES IN CMOS CIRCUITS 1. Subthreshold leakage in the channel in an OFF transistor between the source and drain terminals (Isub) 2. Reverse-bias source/drain junction leakage (IRB) 3. Gate leakage ( IGATE) 26

27 NMOS TRANSISTOR and ITS THREE MAIN LEAKAGE SOURCES Isolation Oxide V DS V GS source gate drain I D source gate drain p n + n + p p n + n + p n + n + n + n + p p p p substrate p p p p p p p p p Top view Drain p- substrate V GS = 0, V DS = 0 (cuto) Well IGate Gate Source IRB IRB Isub Well 27

28 High Speed Ampliiers Remarks Op Amps usually have more than one high impedance node, this slow signiicantly the speed o ampliier. Recall that poles are inversely proportional to time constants. Thus large impedance node imply poles near the origin. Transconductance Ampliiers have ideally only one high impedance node, all the internal nodes are low impedance. This produces low voltage gains but the highest requency response. 28

29 Course Objectives: To understand at the macromodel level the circuit design parameter tradeos. To design optimal circuits, that is circuits that meet the speciications with minimum area, design time and/or power. To identiy the eect o the non-idealities o actual circuits and how to overcome these problems. 29

30 Next we review the conventional Op Amp Design requency response compensation techniques and also we introduced a simple LV Current- Mode based Op Amp using resistors as transconductors. Dierence Dierential Ampliiers are also introduced. 30