Tradeoffs and Optimization in Analog CMOS Design

Transcription

1 Tradeoffs and Optimization in Analog CMOS Design David M. Binkley University of North Carolina at Charlotte, USA A John Wiley & Sons, Ltd., Publication

2 Contents Foreword Preface Acknowledgmerits List of Symbols and Abbreviations xvii xxi xxiii xxv 1 Introduction Importance of Tradeoffs and Optimization in Analog CMOS Design Industry Designers and University Students as Readers Organization and Overview of Book Füll or Selective Reading of Book Example Technologies and Technology Extensions Limitations of the Methods Disclaimer 7 PART I MOS Device Performance, Tradeoffs and Optimization for Analog CMOS Design 9 2 MOS Design from Weak through Strong Inversion Introduction MOS Design Complexity Compared to Bipolar Design Bipolar Transistor Collector Current and Transconductance MOS Drain Current and Transconductance In Weak Inversion In Strong Inversion without Velocity Saturation Effects In Strong Inversion with Velocity Saturation Effects In Moderate Inversion and All Regions of Operation MOS Drain-Source Conductance Analog CMOS Electronic Design Automation Tools and Design Methods Electronic Design Automation Tools Design Methods Previous Application of Design Methods Presented in this Book 29 References 30 3 MOS Performance versus Drain Current, Inversion Coefficient, and Channel Length Introduction Advantages of Selecting Drain Current, Inversion Coefficient, and Channel Length in Analog CMOS Design 34

3 viii CONTENTS Optimizing Drain Current, Inversion Coefficient, and Channel Length Separately Design in Moderate Inversion Design Inclusive of Velocity Saturation Effects Design with Technology Independence Simple Predictions of Performance and Trends Minimizing Iterative Computer Simulations - "PreSPICE" Guidance Observing Performance Tradeoffs - The MOSFET Operating Plane Cross-Checking with Computer Simulation MOS Models Process Parameters for Example Processes Calculation of Composite Process Parameters DC, Small-Signal, and Intrinsic Gate Capacitance Parameters Flicker Noise and Local-Area DC Mismatch Parameters Gate-Overlap and Drain-Body Capacitance Parameters Temperature Parameters Substrate Factor and Inversion Coefficient Substrate Factor Inversion Coefficient Traditional inversion coefficient Fixed-normalized inversion coefficient Using the fixed-normalized inversion coefficient in design Regions and subregions of inversion Temperature Effects Bandgap Energy, Thermal Voltage, and Substrate Factor Mobility, Transconductance Factor, and Technology Current Inversion Coefficient Threshold Voltage Design Considerations Sizing Relationships Shape Factor Channel Width Gate Area and Silicon Cost Drain Current and Bias Voltages Drain Current Without small-geometry effects With velocity Saturation effects With VFMR effects With velocity Saturation and VFMR effects The equivalent velocity Saturation voltage Predicted and measured values The extrapolated threshold voltage Effective Gate-Source Voltage Without small-geometry effects With velocity Saturation and VFMR effects\ Predicted and measured values Summary of trends Drain-Source Saturation Voltage Physical versus circuit defmition Without small-geometry effects With velocity Saturation effects 92

4 CONTENTS ix Predicted and measured values Summary of trends Small-Signal Parameters and Intrinsic Voltage Gain Small-Signal Model and its Application Transconductance Without small-geometry effects With velocity Saturation and VFMR effects Predicted and measured values Summary of trends Universal g m /I D characteristic in CMOS technologies Distortion Body-Effect Transconductance and Relationship to Substrate Factor Substrate factor Body-effect transconductance Predicted and measured values Summary of trends Drain Conductance 130 ^ Due to Channel length modulation DuetoDIBL Due to hot-electron effects Impact of increase near V DSsal Measured values Summary of trends Intrinsic Voltage Gain Capacitances and Bandwidth Gate-Oxide Capacitance Intrinsic Gate Capacitances Extrinsic Gate-Overlap Capacitances Drain-Body and Source-Body Junction Capacitances Intrinsic Drain-Body and Source-Body Capacitances Intrinsic Bandwidth Extrinsic and Diode-Connected Bandwidths Noise Thermal Noise in the Ohmic Region Thermal Noise in the Saturation Region Without small-geometry effects With small-geometry effects Summary of drain-referred and gate-referred thermal noise Flicker Noise Carrier density fluctuation model Carrier mobility fluctuation model Unified, carrier density, correlated mobility fluctuation model Flicker-noise prediction from flicker-noise factors Reported flicker-noise factors and trends Measured and predicted flicker noise Summary of gate-referred and drain-referred flicker noise Flicker-noise corner frequency Gate, Substrate, and Source Resistance Thermal Noise Channel Avalanche Noise Induced Gate Noise Current Gate Leakage Noise Current 231

5 CONTENTS 3.11 Mismatch Local-Area DC Mismatch Modeling Reported mismatch factors and trends Edge effects and other model limitations Calculating gate-source voltage and drain current mismatch Threshold-voltage mismatch increase for non-zero V SB Threshold-voltage dominance of mismatch Summary of gate-source voltage and drain current mismatch Distance DC Mismatch Modeling Reported mismatch factors and trends Gate-source voltage and drain current mismatch Threshold-voltage dominance of mismatch Critical spacing for comparable distance and local-area mismatch DC Mismatch Effects on Circuit Performance Bandwidth, power, and accuracy tradeoffs in current-mode circuits Bandwidth, power, and accuracy tradeoffs in voltage-mode circuits Tirning skew in digital circuits Small-Signal Parameter and Capacitance Mismatch Transconductance mismatch Drain-source conductance mismatch Mismatch effects on circuit Performance Leakage Current Gate Leakage Current and Conductance Gate current Gate conductance Gate Leakage Current Effects on Circuit Performance Minimum frequency of Operation Intrinsic current gain Discharge of capacitances Noise Mismatch Summary of tradeoffs Drain-Body and Source-Body Leakage Current Subthreshold Drain Leakage Current 282 References 283 Tradeoffs in MOS Performance, and Design of Differential Pairs and Current Mirrors Introduction Performance Trends Exploring Drain Current, Inversion Coefficient, and Channel Length Separately Trends as Inversion Coefficient Increases Trends as Channel Length Increases Trends as Drain Current Increases Performance Tradeoffs Overview - The MOSFET Operating Plane Region and Level of Inversion - The Inversion Coefficient as a Number Line 304

6 CONTENTS xi Tradeoffs Common to All Devices Channel width and gate area Intrinsic gate capacitance and drain-body capacitance Effective gate-source voltage and drain-source Saturation voltage Transconductance efficiency and Early voltage Intrinsic voltage gain and bandwidth Tradeoffs Specific to Differential-Pair Devices Transconductance distortion Intrinsic gate capacitance and gate-referred thermal-noise voltage Gate-referred flicker-noise voltage and gate-source mismatch voltage Tradeoffs Specific to Current-Mirror Devices Intrinsic bandwidth and drain-referred thermal-noise current Drain-referred flicker-noise current and drain mismatch current Tradeoffs in Figures of Merit Transconductance efficiency and Early voltage Intrinsic voltage gain, bandwidth, and gain-bandwidth Transconductance efficiency and intrinsic bandwidth Thermal-noise efficiency and flicker-noise area efficiency Bandwidth, power, and accuracy with DC offset Bandwidth, power, and accuracy with thermal noise Comparison of bandwidth, power, and accuracy for DC offset and thermal noise Extensions Design of Differential Pairs and Current Minors Using the Analog CMOS Design, Tradeoffs and Optimization Spreadsheet Selecting Inversion Coefficient Selecting Channel Length Selecting Drain Cunent Optimizing for DC, Balanced, and AC Performance DC optimization AC optimization Balanced optimization Optimizations at millipower Operation Optimizations at micropower Operation Summary of micropower Performance considerations Summary Procedure for Device Optimization 372 References 373 PART II Circuit Design Examples Illustrating Optimization for Analog CMOS Design Design of CMOS Operational Transconductance Amplifiers Optimized for DC, Balanced, and AC Performance Introduction Circuit Description Simple OTAs Cascoded OTAs Circuit Analysis and Performance Optimization Transconductance Simple OTAs Cascoded OTAs 384

7 xü CONTENTS Optimization Output Resistance Simple OTAs CascodedOTAs Optimization Voltage Gain Simple OTAs Cascoded OTAs Optimization Frequency Response Simple OTAs CascodedOTAs Optimization Thermal Noise Simple OTAs Cascoded OTAs Optimization Flicker Noise Simple OTAs CascodedOTAs Optimization Offset Voltage due to Local-Area Mismatch Simple OTAs Cascoded OTAs Optimization Systematic Offset Voltage for Simple OTAs Input and Output Capacitances Simple OTAs CascodedOTAs Optimization Slew Rate Simple OTAs Cascoded OTAs Optimization Input and Output Voltage Ranges Simple OTAs CascodedOTAs Optimization Input, 1 db Compression Voltage Simple OTAs CascodedOTAs Optimization Management of Small-Geometry Effects Design Optimization and Resulting Performance for the Simple OTAs Selection of MOSFET Inversion Coefficients and Channel Lengths DC optimization AC optimization Balanced optimization Predicted and Measured Performance Transconductance, Output resistance, and voltage gain Frequency response 439

8 CONTENTS xiii Thermal noise Flicker noise Offset voltage due to local-area mismatch Systematic offset voltage Input and Output capacitances Slewrate Input and Output voltage ranges Input, ldb compression voltage Layout area Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth Other Optimizations: Ensuring Input Devices Dominate Thermal Noise Design Optimization and Resulting Performance for the Cascoded OTAs Selection of MOSFET Inversion Coefficients and Channel Lengths DC optimization AC optimization B alanced optimization Predicted and Measured Performance Transconductance, Output resistance, and voltage gain Frequency response Thermal noise Flicker noise Offset voltage due to local-area mismatch Input and Output capacitances Slew rate Input and Output voltage ranges Input, 1 db compression voltage Layout area Tradeoffs in DC accuracy, low-frequency AC accuracy, voltage gain, and transconductance bandwidth Comparison of Performance tradeoffs with those of simple OTAs Other Optimizations: Ensuring Input Devices Dominate Flicker Noise and Local-Area Mismatch Other Optimizations: Complementing the Design Prediction Accuracy for Design Guidance and Optimization 474 References 476 Design of Micropower CMOS Preamplifiers Optimized for Low Thermal and Flicker Noise Introduction Using the Lateral Bipolar Transistor for Low-Flicker-Noise Applications Measures of Preamplifier Noise Performance Thermal-Noise Efficiency Factor Flicker-Noise Area Efficiency Factor Reported Micropower, Low-Noise CMOS Preamplifiers MOS Noise versus the Bias Compliance Voltage Transconductance in Saturation Drain-Source Resistance and Transconductance in the Deep Ohmic Region Gate Noise Voltage Thermal noise Flicker noise 493

9 xiv CONTENTS Drain Noise Current Thermal noise Flicker noise Drain Noise Current with Resistive Source Degeneration Bias compliance voltage Thermal noise Flicker noise Extraction of MOS Flicker-Noise Parameters Preamplifier Input Devices Preamplifier Non-Input Devices Comparisons of Ricker Noise Differential Input Preamplifier Description Circuit Analysis, Performance Optimization, and Predicted Performance Voltage gain Frequency response Thermal noise Thermal noise expressed from DC bias conditions Flicker noise Flicker noise expressed from DC bias conditions Summary of Predicted and Measured Performance MOSFET design selections Resulting preamplifier Performance Design Improvements Single-Ended Input Preamplifier Description Circuit Analysis, Performance Optimization, and Predicted Performance Voltage gain Frequency response Thermal noise Thermal noise expressed from DC bias conditions Flicker noise Flicker noise expressed from DC bias conditions Summary of Predicted and Measured Performance MOSFET design selections Resulting preamplifier Performance Design Improvements Prediction Accuracy for Design Guidance and Optimization Summary of Low-Noise Design Methods and Resulting Challenges in Low-Voltage Processes 550 References 552 Extending Optimization Methods to Smaller-Geometry CMOS Processes and Future Technologies Introduction Using the Inversion Coefficient for CMOS Process Independence and for Extension to Smaller-Geometry Processes Universal g m /I D, V EFF, and V DSsal Characteristics Across CMOS Processes 556

10 CONTENTS Other Nearly Universal Performance Characteristics Across CMOS Processes Porting Designs Across CMOS Processes Extending Design Methods to Smaller-Geometry Processes Enhancing Optimization Methods by Including Gate Leakage Current Effects Using an Inversion Coefficient Measure for Non-CMOS Technologies 561 References 562 Appendix: The Analog CMOS Design, Tradeoffs and Optimization Spreadsheet 565 Index 583