Gunning Transceiver Logic Interface Bus Design Project

Transcription

1 Gunning Transceiver Logic Interface Bus Design Project Group #14 EE 307 Winter 2007 February 23, 2007 Robert Hursig Tommy Oleksyn

2 Abstract In this project the given Gunning Transceiver Logic circuit was designed per the specifications given. The noise margins on node 20 and node 52 fell within the specified limits of 0.25 V and 1V respectively. The upper and lower noise margins on node 20 are 0.35 V each while the upper and lower margins between the input (node 10) and output (node 52) are 1.8 V and 1.5 V respectively. All sized transistors had a minimum feature size greater than or equal to 0.25 µm and total transistor area fell below the maximum allowed area of 250 µm 2. The pertinent parameters of the circuit can be seen in Table 1 below along with the designed W/L ratios and total transistor area seen in Table 2 below. For final PSpice code see Appendix A. Table 1: Final Parameter Values for the GTL Circuit Parameter Value FOM [ns mw] Power Dissipation [mw] Delay [ns] Table 2: W/L Ratios and Transistor Areas for the GTL Circuit Transistor W [µm] L [µm] Area [µm 2 ] MN MP MP MN MN MP MN MP MP MN MP MN MP MP51* MP51* Total Area [µm 2 ] : 62.6 *W/L Ratios given One specific application of GTL is in the driving of an electronic backplane bus such as a computer bus. The GTL interface is used to connect pins of the bus to transmit the high frequency signals at high speeds and with a diminished voltage swing, thus reducing power consumption within the system. i

3 Objective The objective of this project involves optimizing the given Gunning Transceiver Logic circuit of Figure 1 below to meet the following project requirements: Maintain noise margins of at least 0.25V between V in and node 20 and noise margins of at least 1V between V in and V out Size all transistors other than MP51 and MN51 given that the minimum feature size of the transistors is 0.25 µm and given that the total combined transistor area must be no greater than 250 µm 2. Minimize the figure of merit (FOM) value for the circuit assuming V in toggles from railto-rail (3.3V to 0V) at 100 MHz. The FOM is defined as follows: FOM = (delay in ns) x (total power dissipation in mw) Figure 1: Circuit Diagram for the Optimized GRL Circuit -2-

4 Design Procedure To design and optimize the GTL circuit of Figure 1, the circuit was divided into three subsections. First, the W/L ratios for the GTL driver circuit ending at node 20 were designed. Second, the transistors of the GTL receiver circuit from input node 20 to output node 22 was designed. Last, the two inverting output buffer circuits from input node 22 to output node 50 were specified. In general, W and L values were designed to be as small as possible due to the necessity of the circuit to operate at high frequencies and under a total transistor area of 250 µm 2. As the W and L values increase, the capacitance increases, as does the delay of the circuit, which is not desired in this high frequency application. It was discovered that using the minimum feature size of 0.25 µm for transistor parameters altered the performance of the circuit significantly, yielding values that simple DC MoHAT analysis could not accurately predict. While using larger W and L values would circumvent this problem, the requirement of this project was to optimize the given circuit s speed and power dissipation at AC, meaning the smaller feature sizes were necessary. First, W and L values for the transistors were calculated by hand at DC to arrive at estimated values. Next, the W and L parameters were then input into Cadence PSPICE simulation software and the desired waveforms were analyzed for correct operation and then fine-tuned. In general, if a waveform appeared to be staying relatively low or high, the appropriate pull-up or pull-down circuit, respectively, was increased using an iterative process. Sizing the Driver Circuit Transistors The first sub-circuit analyzed and designed was the GTL driver circuit as seen in Figure 2 below. The driver consists of a CMOS inverter with an additional PMOS transistor, MP2, in series with the pull-up transistor, MP1. At DC, MN2 and the transmission line can be analyzed as a standard NMOS inverter with a resistive load being driven by the output of the CMOS inverter. The purpose of this circuit is to transmit a high frequency input signal across a transmission line at high speed while maintaining noise margins on the receiving end. Figure 2: GTL Driver Circuit and Modeled Transmission Line Sizing MN1, MP1, and MP2 As the driver for the entire circuit, the W and L values for the driver transistors are key to the behavior. The steepness and the location of the threshold voltage on the VTC are important factors to the sizing of these transistors. The first three transistors in the driver circuit, MN1, MP1, and MP2, form a CMOS inverter with an additional PMOS transistor in the pull-up -3-

5 network. The first step in determining the W and L values for the transistors was setting the threshold voltage of the first inverter to a value midway between the rails, keeping the VTC symmetrical. The following calculation shows the designation of the W/L ratios, assuming that transistor MP2 is taken to be twice the value of MP1. Calculation 1: Finding the W/L Ratios for the CMOS Inverter of the GTL Driver V IN =V 12 =1.65V, k N = A/V 2, k P = A/V 2, V TN = V, V TP = V Hypothesize: MP1 and MN1 are SATURATED, MP2 is LINEAR Analyze: ' W 2 I N =.5 k N ( ) N ( VM VTN ) L ' W 2 I P1 =.5 k P ( ) P1 ( VSP 1 VM + VTP ) L ' W 2 W W I P2 =.5 k P ( ) P2 [2( VCC + VTP )( VCC + VSP 1) + ( VCC + VSP 1) ],( ) P2 = 2 ( ) P1 L L L V = 3.207V SP1 W ( ) P1 L = 7.19 W ( ) N L Test: MN1:V DS =1.65 V > V GS V TN = 1.23 V MP1: V SD =1.56 V > V SG + V TP = 1.00 V MP2: V SD =0.093 V < V SG + V TP = 2.75 V While the minimum feature size of the transistors is 0.25 µm, it was decided that the VTC of the driver circuit should be steeper near the threshold voltage. It was seen through iteration that increasing the W and L values away from the minimum feature size increased the steepness of VTC curves, even while maintaining the same ratios. Hence, a minimum feature size (L) of 1 µm was chosen for these transistors, making MN1 (1/1), MP1 (7.2/1), and MP2 (14.4/1). The resulting VTC of the circuit at node 12 is seen in Figure 3 below, confirming the symmetry and threshold voltage calculated. Figure 3: Voltage Transfer Characteristic at Node V 3.0V 2.0V 1.0V -4-0V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V V(12) Vin

6 Sizing MN2: The transmission line driver, MN2, was first sized due to the first important requirement of the project, maintaining 0.25V noise margins on node 20. This part of the circuit also posed a distinct challenge as the first stage of the GTL driver circuit, a CMOS inverter with a positive rail voltage of 3.3V, to an NMOS inverter with resistive load with positive rail voltage of 1.2V. It was important for this circuit to also have a lower logic swing due to the lumped transmission line capacitance and inductance which resist changes in voltage and current. The important part in designing this circuit was realizing that node 20 is the input to the GTL receiver, a differential amplifier with reference voltage V REF, which is 0.8 V. As such, the output logic swing at node 20 should be centered about V REF to keep the output of the receiver symmetrical. As the output high voltage of the GTL driver circuit is equal to V TT (1.2 V), the output low voltage of the driver circuit should be 0.4 V to center the logic swing around V REF. This V OL value must be checked to fit the noise margin criteria for node 20, but depends on the design of the GTL receiver circuit and will be discussed in the next section. To achieve a V OL of 0.4 V, MN2 must be sized appropriately. As seen in Figure 4, the output of the driver at node 20 depends on the voltage drop in the resistor R TT. Hence, an increased current through R TT and MN2 results in a larger voltage drop across the resistor and a lower V OL value. Due to the output impedance of this part of the driver, the W and L values of the transistor need to be minimized, requiring the use of the minimum feature size of 0.25 µm. The W/L ratio for MN2 was calculated by hand and was found to be largely inaccurate when using this value. Calculation 2 below shows the hand calculation of the W/L ratio. With V OH =1.2V, set V IN =V OH =1.2V Hypothesize: MN2 is LINEAR Analyze: ' W 2 I N =.5 k N ( ) N [2( VTT VTN ) VOL VOL ] L Setting V OL =0.4V = I R V = TT V R W ( ) N = L Test: MN2: V DS =0.4V < V GS -V TN = 1.2V V = Through the calculation, a W/L ratio of is derived, yet simulating the circuit with W = 69.4 µm and L=0.25 µm yields a V OL of 0.2 V, not 0.4 V. Therefore, fine tuning the W and L values for MN2 yields an output low voltage of 0.4 V for a W/L ratio of 34/0.25. The voltage transfer characteristic between node 20 and V IN (node 10) can be seen in Figure 4 on the next page. OL -5-

7 1.5V Figure 4: Voltage Transfer Characteristic Between Node 20 and V IN, Node V 0.5V 0V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V V(20) Vin Sizing the GTL Receiver Circuit Transistors The second part of the entire GTL circuit analyzed was the GTL receiver, or differential amplifier circuit as seen in Figure 5 below. The purpose of this circuit is to receive the signal from the transmission line at node 20 and boost the logic swing back towards the original rail-torail voltage of 3.3 V. Figure 5: GTL Receiver Circuit V BIAS MP21 (4/.25) (4) MP23 (4/.25) (22) V CC V CC (21) V CC (23) V CC = 3.3V V REF = 0.8V V TT = 1.2V V BIAS = 0.0V (2) MP22 (4/.25) V REF MN21 (4/.25) Because the output logic swing of the driver circuit was centered around V REF, the differential amplifier of the receiver circuit will amplify voltages above the 0.8 V reference voltage and attenuate voltages below the reference voltage. The differential amplifier circuit must be symmetrical to properly boost the signal around V REF. Hence, MP21 and MP22 must have matching W/L values and MN21 and MN22 must have matching W/L values. As transistor MP23 supplies current to the differential amplifier, its W/L value must be large enough to supply the necessary current to the receiver yet small enough to avoid large power dissipation in the circuit. To maintain symmetry the W/L values between the NMOS and PMOS devices was set to be equal and sequential simulations were ran. The W/L values were gradually increased until MN22 (4/.25) -6-

8 the (FOM) failed to decrease, meaning that the decrease in delay failed to outweigh the increase in power dissipation for the circuit. The GTL receiver circuit must meet the minimum 0.25 V noise margin requirements for node 20. For the differential amplifier circuit the input high and input low voltages are as follows: V IL = V REF -50mV=0.75 V and V IH = V REF + 50 mv = 0.85 V Moreover, the noise margins for node 20 are defined as, NM L = V IL(DIFF) -V OL(DRIVER) and NM H = V OH(DRIVER) -V IH(DIFF) where V IL(DIFF) and V OL(DIFF) are the differential amplifier input low and input high voltages and where V OL(DRIVER) and V OH(DRIVER) are the driver output low and output high voltages. Plugging in the V OL and V OH values from the driver circuit yields noise margins of 0.35 V on the high and low side, satisfying the project requirement of 0.25 V. Sizing the Output Buffer Transistors The purpose of the output buffer stage of the circuit, as seen in Figure 6 below, is to further restore logic levels coming out of the GTL Receiver circuit. Moreover, the second inverting buffer stage is specifically tasked with driving the load gate and load capacitance at node 50. Figure 6: Output Buffer Circuit with Load Gate and Capacitance Sizing MN31 and MP31 Sizing the transistors of the first inverting buffer of this circuit depends heavily on restoring the logic levels from the previous input. Looking at the transient analysis as seen in Figure 7 on the next page, the output waveform of the GTL receiver (node 22) only swings from V to 1.98V. Therefore, as this waveform is an input to the inverting CMOS buffer of MN31 and MP31, the output (node 30) must be pulled down more strongly than it is being pulled up. Moreover, because k N is significantly greater than k P, the influence of increasing the W/L ratio on the NMOS transistor outweighs the influence of increasing the W/L ratio on the PMOS transistor. The hand derived calculation of the ratio of W/L for MP31 to the W/L for MN31 turned out to be 6.02/1, but simulation yielded much different results. Through an iterative process of gradually increasing or decreasing the strength of the pull-up network or the pulldown network the W/L values for both MN31 and MP31 turned out to be 4/0.25. Even though these W/L ratios are identical, the larger k of the NMOS transistor still satisfies the needed stronger pull-down network. -7-

9 3.5V Figure 7: GTL Receiver Output Waveform with V IN as a 100 MHz Square Wave 3.0V 2.5V 2.0V 1.5V 1.0V 0.5V 0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns V(10) V(22) Time Sizing MN32 and MP32 Sizing the transistors of the second inverting buffer, on the other hand, depended heavily on the ability to quickly charge and discharge the load capacitance, C L. As the load capacitance resists change in voltage, both a strong pull-up network and a strong pull-down network are needed to quickly charge and discharge the capacitor respectively. Calculating t PHL by hand yields a W/L ratio for MN32 that must be greater than to discharge the load capacitance within half of the period, or 5ns. Calculating t PLH by hand yields a W/L ratio for MP32 that must be greater than 18.3 to charge the load capacitance within the same 5 ns half-period. While these conditions were indeed met through the simulation, the actual W/L values for both MN32 and MP32 were much greater than the calculated values. Through the same iterative simulation process the optimal values of the W and L numbers for MN32 and MP32 were 30/0.25 and 60/0.25 respectively. Another critical part of the project requirements is verifying that the noise margins between V IN and V OUT of the circuit are greater than the 1 V minimum requirement. A simple DC analysis of the VTC seen in Figure 8 on the next page verifies that this benchmark was indeed surpassed. The output VTC is nearly vertical and an upper noise margin of 1.8 V and a lower noise margin of 1.5 V. -8-

10 4.0V Figure 8: Voltage Transfer Characteristic, V IN Versus V OUT 3.0V 2.0V 1.0V 0V 0V 0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 3.5V V(52) Vin -9-

11 Results The performance of the final circuit meets the criteria specified. The 0.35 V noise margins at node 20 exceeded the minimum required value of 0.25 V by 40%. Moreover, the 1.8 V upper noise margin between V IN and V OUT surpassed the 1 V minimum by 80%, while the lower noise margin of 1.5 V surpassed the 1 V minimum by 50%. All transistors were sized with a minimum feature size greater than or equal to the 0.25 limit and the total transistor size of the circuit was 62.6 µm 2, 25% of the maximum allowed area. Final W and L values, individual area, and total transistor area values can be seen in Table 2 below. Table 2: W/L Ratios and Transistor Areas for the GTL Circuit Transistor W [µm] L [µm] Area [µm 2 ] MN MP MP MN MN MP MN MP MP MN MP MN MP MP51* MP51* Total Area [µm 2 ] : 62.6 *W/L Ratios given The entire GTL circuit performs its dedicated task as seen in Figure 9 on the following page. The input waveform is transmitted successfully at 100 MHz to the output slightly delayed. As seen in the figure the shape of the waveform is preserved, closely matching that of the original input. Figure 9: Transient Analysis of the GTL Circuit 4.0V 2.0V 0V 4.0V V(10) V(52) 2.0V SEL>> 0V 4.0V V(10) V(20) V(22) V(12) 2.0V 0V 0s 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns V(10) V(30) V(50) Time -10-

12 The overall performance of the circuit is based upon the speed and power dissipation of the circuit, reflected in the final figure of merit value. The total propagation delay of the circuit was approximately ns while the total power dissipation of the circuit due to both V CC and V TT turned out to be mw. As all other sources were tied to gates, no power dissipation occurred in other voltage sources. These two values combined yield a FOM value equal to approximately ns mw. The delay, power, and FOM values are listed in Table 1 below, and the PSpice Eval Goal Functions used to calculate these values can be found in Appendix B at the end of this report. Table 1: Final Parameter Values for the GTL Circuit Parameter Value FOM [ns mw] Power Dissipation [mw] Delay [ns]

13 Appendix A: Final PSpice Code * EE 307 GTL Project Winter 2007 * Group #14 - Robert Hursig and Tommy Oleksyn * Rails Vcc Vref Vtt Vbias * GTL Driver Vin 10 0 PULSE ( n 0.5n 5n 10n) * PULSE( {v1} {v2} {tdelay} {trise} {tfall} {width} {period} ) MN CMOSN W=1u L=1u MP CMOSP W=7.2u L=1u MP CMOSP W=14.4u L=1u MN CMOSN W=34u L=.25u * Interconnect Ltt n Rtt Ctt p * GTL Receiver MP CMOSP W=4u L=.25u MP CMOSP W=4u L=.25u MN CMOSN W=4u L=.25u MP CMOSP W=4u L=.25u MN CMOSN W=4u L=.25u * GTL CMOS Buffer MP CMOSP W=4u L=.25u MN CMOSN W=4u L=.25u MP CMOSP W=60u L=.25u MN CMOSN W=30u L=.25u *Load Cout p MP CMOSP W=1u L=1u MN CMOSN W=1u L=1u *.DC Vin TRAN 20p 80n 0 10p * print_step final_time (results_delay) (step_ceiling) * The last two parameters are officially optional, * but I recommend that you specify a step_ceiling no * greater than the smaller of final_time/1000 or (rise or fall time)/10..probe.op * From * TSMC (0.25 micron) DATE: Jun 11/01 LOT: T14Y WAF: 03 DIE: N_Area_Fring * DEV: N3740/10 * Temp= 27.MODEL CMOSN NMOS ( LEVEL = 3 + TOX = 5.7E-9 NSUB = 1E17 GAMMA = PHI = 0.7 VTO = DELTA = 0 + UO = ETA = 0 THETA =

14 + KP = E-4 VMAX = E4 KAPPA = RSH = E-3 NFS = 1E12 TPG = 1 + XJ = 3E-7 LD = E-11 WD = E-8 + CGDO = 6.2E-10 CGSO = 6.2E-10 CGBO = 1E-10 + CJ = E-3 PB = 0.5 MJ = CJSW = E-10 MJSW = 0.5 ).MODEL CMOSP PMOS ( LEVEL = 3 + TOX = 5.7E-9 NSUB = 1E17 GAMMA = PHI = 0.7 VTO = DELTA = 0 + UO = 250 ETA = 0 THETA = KP = E-5 VMAX = E5 KAPPA = RSH = NFS = 1E12 TPG = -1 + XJ = 2E-7 LD = E-13 WD = E-9 + CGDO = 6.66E-10 CGSO = 6.66E-10 CGBO = 1E-10 + CJ = E-3 PB = MJ = CJSW = E-10 MJSW = 0.5 ) *.end

15 Appendix B: PSpice Eval Goal Functions Power Dissipation Calculation Code: YatX(AVGX((-I(Vtt))* V(3)+ (-I(Vcc))* V(1),10n),70n) Propagation Delay Calculation Code:.5*(XatNthY(V(52),1.65,5)-XatNthY(V(10),1.56,5)+XatNthY(V(52),1.65,6)- XatNthY(V(10),1.56,6)) FOM Calculation Code:.5*(XatNthY(V(52),1.65,5)-XatNthY(V(10),1.56,5)+XatNthY(V(52),1.65,6)- XatNthY(V(10),1.56,6))*YatX(AVGX((-I(Vtt))* V(3)+ (-I(Vcc))* V(1),10n),70n)*PWR(10,12)