A MOS VLSI Comparator

Transcription

1 A MOS VLSI Comparator John Monforte School of Music University of Miami, Coral Gables, FL. USA Jayant Datta Department of Electrical Engineering University of Miami, Coral Gables, FL. USA ABSTRACT A comparator is designed that can coexist with digital circuits on a MOS VLSI die. Besides designing the circuit, modeling and layout techniques for the comparator or other analog devices are described that can be used to design analog circuits despite the strictly digital nature of most VLSI CAD systems. The performance of the fabricated comparator is compared to the modeled version. 1. INTRODUCTION In order for any digital system to interface with its human operators, it must interact in a manner that humans are accustomed to. Since humans are analog beings, it is ultimately necessary for the machine to accept analog inputs and deliver analog outputs in order to make the interaction easiest on the human. The catalog of analog building blocks is relatively concise, consisting principally of digital to analog converters and their counterparts which in turn are comprised of sample-and-holds, filters, amplifiers, and comparators. More sophisticated components such as phase locked loops, voltage controlled oscillators and filters, and sensors for temperature, magnetism and light are also possible. The comparator designed here was an exercise in modeling and layout of analog devices for CMOS VLSI technologies. A comparator was chosen because it is the simplest of analog to digital converters and has much usefulness as a building block. Construction of this circuit required no adaptation of the fabrication process. 2. DESIGN LIMITATIONS In order for a need for MOS VLSI analog circuitry to exist, it must be assumed that the devices will be coexisting on a substrate shared with digital circuitry. Almost any other semiconductor technology is superior to the task of implementing analog circuitry (for reasons to be outlined below) so it follows that MOS VLSI analog blocks must be operated on the same supply voltages, use the same process parameters and also be small enough to not crowd the die.

2 There are several difficulties trying to implement a comparator on a MOS VLSI substrate. Among them are: 2.1 Passive components Substrate connected diodes can be formed by connecting to an empty P or N well. Since light doping is used in MOS fabrication. It is possible that the diodes will encourage latch up in nearby circuits. Resistors and capacitors are virtually unavailable. Capacitors require area, which becomes less available as new fabrication technologies allow for even higher transistor densities. The cost of losing valuable transistor area becomes greater as the level of integration increases. Resistors can be made with metal or polysilicon but their resistivity is low. Unless the value needed is on the order of 10 KΩ or less a resistor will take up inordinate amounts of area. 2.2 Bipolar Devices Using the natural diode junctions formed when wells are doped, bipolar transistors can be fabricated. Lower output impedances and higher power outputs can be achieved using such devices on output stages, but the tendencies of these lightly doped areas to cause latch up in nearby wells requires the use of spacing rules that are not well defined. 2.3 Supply voltages Process parameters dictate that each circuit element operate over a 5 volt potential, with the substrate being the most negative potential and connected to ground. In order to use voltages less than logic ground, the logic circuitry must itself be formed in a well, which requires extra process steps. This 5 volt maximum will limit the dynamic range of the analog circuit by restricting the headroom available. Also for best noise margin when connecting with digital elements we would like the analog inputs and outputs to handle the full 5 volt range. These factors effectively prevent the use of voltage source biasing elements because they will ultimately limit the linear voltage swing of the circuits. It is therefore convenient that these biasing elements are not readily available to begin with. 2.4 Output power MOS transistors, unlike bipolar devices, are limited in output power capability. They are horizontal devices, meaning their current is carried on the surface of the substrate. Bipolar devices have depth and therefore allow more bulk material to sink the heat. Typical bias currents are on the order of 10 µa. An output device such as a LED requires 10 ma and a small loudspeaker requires around an ampere. While output stages could be accommodated to drive current gain stages off the chip, it makes more to move sense the entire circuit off-chip because the other technology would most likely be superior. The design of this paper presupposes that it would be used

3 as an input device whose output will drive a logic gate or another MOS analog stage on the same substrate. Output circuits are possible and may best be formed as current sources which can best be transformed to a voltage by an external current to voltage converter. R/2R ladders used in digital to analog converters are good examples of this. 2.5 Quantum noise Designing with a level of integration as high as VLSI requires that the circuit be small. At feature sizes approaching one micron, the Johnson thermal noise model begins to break down. Here, individual electrons moving due to thermal activity are discretely identifiable. We can no longer assume there is a steady flow of current. This noise has a spectrum that increases as 1/f which further degrades the low frequency and DC dynamic range. This makes interface with humans more difficult because humans are low frequency creatures. Preamplification of transducers with low efficiencies will need to be handled off chip. This design presupposes that the input signals will be large in amplitude. 2.6 Bandwidth MOS devices are capable of high speeds and, therefore, so are the analog elements formed from them. This is further enhanced as the device sizes become smaller, because the parasitic capacitances are reduced. However, this is not necessarily a virtue. The small capacitances that exist between neighboring logic circuits and connecting traces will cause significant signal currents to be cross coupled to the analog stages due to the high frequency spectral components represented by digital switching and the high input impedances inherent in MOS transistors. Faraday shielding may be an important element of the design itself. If the capacitance it subsequently adds also slows the circuit, so much the better. 2.7 Power density An interesting parameter that needs consideration is called power density. As devices are scaled smaller, their power dissipations must also decrease. Also, the density/speed product desired with such a high level of integration dictates that the power levels be low for the device to be reliable. Digital CMOS circuits draw virtually no power at idle. Since their inputs load capacitively, the power consumed is proportional to the clocking frequency. Analog circuits, on the other hand are biased for linear operation and therefore all devices are centered in their active regions. The result is that the circuit consumes current at all times and all power that is not delivered to the load must be dissipated in the chip. When combined with other circuits, the resultant heat may cause chip failure. Some examples of relative power densities are shown in the table below. For example, a 100 watt light bulb emits its thermal power over an area that is defined by its glass bulb. That power density makes the bulb too hot to touch.

4 POWER DENSITY SOURCE 10 3 watts/meter 2 Sunlight 10 4 watts/meter 2 100w light bulb 10 5 watts/meter 2 VLSI with grooved substrate 10 6 watts/meter 2 Space shuttle tiles Table 1 Power Densities Ideally we would like to keep our power density at or below 10KW/m 2 which is the range used commonly in VLSI. Since it is our objective to make this device as small as the technology will allow, the power density requirement will define the bias currents used. 2.8 Design system limitations Most CAD systems for VLSI design presuppose that digital circuits are the objective. Test signals such as sine waves and test procedures that obtain transfer curves, model noise, or plot bandwidth are not available. 2.9 External contacts The contacts formed on the edge of the chip usually contain logic circuitry for protection and buffering. This will cause difficulty when trying to pass an analog signal. Designers that integrate analog circuits on a chip need to use specially designed input and output pads when passing analog signals between the chip and the outside world. 3. DESIGN DEVELOPMENT Our design begins with establishing a circuit topology shown in figure 1. The inputs are through a differential pair of transistors, M 1 and M 2, which have active loads M 3 and M 4 respectively. The input pair is fed current from M 7 which is mirrored from M 6. The output of the first stage is delivered to the second stage which consists of M 5 and its active load M 8. The current reference comes from the M 6 current source which uses M 9 as a high impedance active load.

5 Vdd 1 Vdd 1 Vdd 1 M6 REF M7 M8 2 CMV 3 NEG M1 M2 POS OUT ACL 7 COMP 8 M5 M9 M3 M4 Vss 0 Vss 0 Vss 0 Vss 0 FIGURE 1 Topology of the Circuit The input stage uses P channel FET's. While P channel devices are inferior to N channel ones, we opted to use PFET's to allow the circuit to compare signals near ground and remain in their linear region. At the other end of their common mode range, the transistors begin to turn off and the current source M 7 also starts to leave its linear area. The next step is to select bias voltages. Node 1 is defined by the 5 volt supply. Node 4, the output, would be best centered between power and ground potentials. The current mirror reference voltage must be as high as practical to allow for the maximum common mode swing, but must allow the enhancement devices to remain in the saturation region. Since V T is around 0.7 to 0.8 volts, V GS is selected to be 1 volt. This puts the value at node 2 to be 4 volts. Node 3 is selected to be below node 2 so that the saturation condition is maintained while permitting high common mode swings. Nodes 7 and 8 are picked to be 1.5 volts so that the active loads are fully saturated while allowing maximum voltage swings for the input transistors. Hand calculations show that adequate power densities can be achieved if the bias currents are kept around 1.5 microamp for each of the three loops. Lower currents are of course permissible, but increased noise and smaller bandwidth will result. Also, as we will soon see from the geometry calculations, the devices will become longer and therefore require more area. Once the currents and voltages have been declared, the device geometries can be calculated. The relationship used is given as:

6 where: S = W/L = 2I/{K P (V GS - V T ) 2 } S - Aspect ratio W -Channel width (microns) L -Channel length (microns) I - Channel current (A) V GS - Gate to Source voltage K P - Transconductance factor (A/V 2 ) V T - Threshold voltage The latter two parameters are given seperately for N and P transistors. The parameters that are process dependent were obtained in a printout from a recent fabrication run of IC's using the same 2 micron N-well technology that the amplifier is being designed for. For the purpose of our calculations we used: K Pn = 5.0 A/V 2 K Pp = 2.5 A/V 2 V Tn = 0.75 V V Tp = 0.79 V If K P is not given, it can be calculated using the relation: K Pn = µ n C ox K Pp = µ p C ox where: µ - Channel mobility (cm 2 /V s ) C ox - Gate oxide capacitance factor (F/cm 2 ) One of the design objectives was to utilize the minimum feature limit of the process technology, which is 2 microns. As it turns out, the aspect ratios of the devices were less than 1 meaning the channels are to be longer than they are wide. The widths were fixed at the 3 micron limit in the MAGIC scmos6 technology specifications for scalable CMOS which put the lengths at: DEVICE LENGTH M 1,M 2 2 M 3,M 4 26 M 5 13 M 6,M 7,M 8 37 M The length of M 9 was considered unreasonable so a new transistor wired as an active resistor and placed in series was included as M 10. The new M 9 and M 10 combination is

7 shorter. The only penalty paid is the reduced voltage range over which the active resistors can remain linear. This is no detriment at this point because their purpose is to establish a fixed reference voltage anyway. Their lengths are: DEVICE LENGTH M 9 37 M The complete circuit is shown in figure 2. Vdd 1 Vdd 1 Vdd 1 M6 REF M7 M8 2 CMV NEG M1 M2 POS OUT M10 ACL COMP M REF2 M9 M3 M4 Vss 0 Vss 0 Vss 0 Vss 0 Figure 2 Comparator Circuit After hand calculation, the circuit was modeled in SPICE. The MOSIS device parameters of figure 2 are given for SPICE simulation. The results of the SPICE simulation are summarized in Appendix 1. Common mode performance was simulated separately and the results are given in Appendix LAYOUT The final step in the process was to lay the elements out in "virtual silicon" using MAGIC. The sensitive input stage was symmetrically placed in the center of the cell. The output stage and current reference were placed on either side. Since they both consume the

8 same current, they raise the temperature of the substrate area above ambient temperature by an equal amount. The input transistors will experience identical temperatures and have less thermal drift, so that both the absolute offset voltage and the offset voltage drift can be minimized. Power nodes line the cell on top and bottom and similar low impedance nodes cover the cell in a metal1 layer. The intent is to provide the cell with a bit of Faraday shielding to protect it from electrostatically coupled signals that may come from nearby logic elements. The stray parasitic capacitances formed between the circuit elements and the shielding will appear as a capacitance to AC ground. The finished cell takes up an area 61 by 66 microns or 4026 micron 2. A test version of the cell was fabricated. Measurement of the performance of such a device is problematic. The source follower output stage has an output impedance of 4 MΩ which is hardly an ideal voltage source. The large gain makes it almost impossible to keep the device out of saturation while measuring. As the output signal drifts, the current in the transistors changes, causing thermal changes which in turn causes more drifting. In order to see if the fabricated unit matches the design goals, we checked the bias voltages and connected the unit as a unity gain follower to measure the frequency of oscillation which can be compared to the SPICE model. A photograph of this appears as figure 3. The device appears to meet all design expectations. Figure 3 Photo of output in oscillation Full specifications of the finished comparator are listed in figure 4.

9 Input Voltage Range V max -0.5 to 5.5V Supply Current I dd 7.5x10-6 A Power Dissipation P d 3.73x10-5 W Forward Gain AV 61dB Common Mode rejection CMRR 67dB Differential Input Resistance R i 1x10 20 Ω Output Resistance R o 3.8x10 6 Ω Gain-Bandwidth Product GBW 1.8x10 10 Hz Unity Gain Frequency f T 3x10 8 Hz Figure 4 Comparator Specifications 5. SUMMARY The purpose of this project was twofold. First, we were able to design a cell for use as a comparator. Second, and more importantly, we were able to find a means to design analog components using existing digital VLSI design tools. An N-type device can be made using the same design rules. New circuits can be made that have greater gain, less offset or other features. From there, more analog cells can be developed such as digital to analog ladders, single ended amplifiers and more. These cells can be applied to form functional blocks such as filters, oscillators, opto-isolators, and other analog circuits. Integration of analog functions on an otherwise digital chip can prove to be a useful asset in VLSI designs. 6. ACKNOWLEDGMENTS This work was done with support of a grant for MOSIS sponsored by the National Science Foundation (USA). 7. REFERENCES Glasser L. and Dobberpuhl D.,1985, The Design and Analysis of VLSI Circuits (Addison Wesley) Mavretic, A MAGIC scmos6 specifications Appendix 1 SPICE Performance parameters, differential drive Appendix 2 SPICE Performance parameters, common mode drive

10 *******28-APR-89 ******* SPICE 2G.5 (10AUG81) *******00:22:46***** P Channel Opamp/Comparator **** INPUT LISTING TEMPERATURE = DEG C *********************************************************************** * Node 0 Vss * Node 1 Vdd * Node 2 REF * Node 3 CMV * Node 4 OUT * Node 5 NEG * Node 6 POS * Node 7 ACL * Node 8 COMP * Node 9 REF2 * * Circuit Description * Vdd 1 0 5V M CMOSP W=3U L=2U M CMOSP W=3U L=2U M CMOSN W=3U L=26U M CMOSN W=3U L=26U M CMOSN W=3U L=13U M CMOSP W=3U L=37U M CMOSP W=3U L=37U M CMOSP W=3U L=37U M CMOSN W=3U L=26U M CMOSP W=3U L=37U * Device effective widths have been ignored * * Device Parameters *.MODEL CMOSN NMOS LEVEL=2 LD= U TOX= E-10 + NSUB= E+15 VTO=0.75 KP= E-05 GAMMA = PHI=0.6 UO= UEXP= UCRIT= DELTA= VMAX= XJ= U LAMBDA= E-02 + NFS= E+11 NEFF=1 NSS= E+12 TPG= RSH= CGDO= E-10 CGSO= E-10 + CGBO=3.46E-11 CJ= E-04 MJ= CJSW= E-10 + MJSW= PB= * Weff= Wdrawn - DeltaW DeltaW = -0.38U *

11 .MODEL CMOSP PMOS LEVEL=2 LD= U TOX= E-10 + NSUB= E+15 VTO= KP= E-5 GAMMA= PHI=0.6 UO=286 UEXP= UCRIT= DELTA= VMAX= XJ= U LAMBDA= E-02 + NFS= E+11 NEFF=1.001 NSS= E+12 TPG= RSH= CGDO= E-11 CGSO= E-11 + CGBO=2.11E-10 CJ= E-04 MJ= CJSW= E-10 + MJSW= PB= * Weff= Wdrawn - DeltaW DeltaW = -0.27U ÜjÜŒ* * Simulation Parameters * * Set initial voltages to speed convergence.nodeset V(2)=3.0 V(3)=3.0 V(4)=2.5 V(7)=1.5 V(8)=1.5 V(9)=1.5 * VIN AC SIN( G) VCM V.DC VIN OP.TF V(4,0) VIN.AC DEC 4 1 1G.NOISE V(4,0) VIN *.PRINT DC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0).PLOT DC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) (0,5).PRINT AC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) VP(4,0).PLOT AC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) VP(4,0).PRINT NOISE ONOISE INOISE.END

12 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** MOSFET MODEL PARAMETERS TEMPERATURE = DEG C ************************************************************************************************************************* CMOSN CMOSP TYPE NMOS PMOS LEVEL VTO KP 5.04D D-05 GAMMA PHI LAMBDA 3.43D D-02 PB CGSO 1.16D D-11 CGDO 1.16D D-11 CGBO 3.46D D-10 RSH CJ 1.46D D-04 MJ CJSW 5.08D D-10 MJSW TOX 3.99D D-08 NSUB 1.00D D+15 NSS 1.00D D+12 NFS 1.00D D+11 TPG XJ 2.50D D-07 LD 1.34D D-08 UO UCRIT 9.90D D+04 UEXP VMAX 5.68D D+04 NEFF DELTA

13 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** DC TRANSFER CURVES TEMPERATURE = DEG C ************************************************************************************************************************* VIN V(4) V(3) V(7) V(8) V(2) E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+00

14 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** DC TRANSFER CURVES TEMPERATURE = DEG C ************************************************************************************************************************* LEGEND: *: V(4) +: V(3) =: V(7) $: V(8) 0: V(2) (*+=$0) D D D D D+00 VIN V(4) D D-01. *. =. $ D D-01. *. =. X D D-01. *. =. X D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =. $ D D-01. *. =.$ D D-01. *. = $ D D-01. *. = $ D D-01. *. = $ D D-01. *. = $ D D+00.. X * D D+00. $. = * 1.000D D+00. $. = * 1.500D D+00. $. = * 2.000D D+00. $. = * 2.500D D+00.$. = * 3.000D D+00.$. = * 3.500D D+00 $. = * 4.000D D+00 $. = * 4.500D D+00 $. = * 5.000D D+00 $. = * 5.500D D+00 $. = * 6.000D D+00 $. = * 6.500D D+00 $. = * 7.000D D+00 $. = * 7.500D D+00 $. = * 8.000D D+00 $. = * 8.500D D+00 $. = * 9.000D D+00 $. = * 9.500D D+00 $. = * 1.000D D+00 $. = *

15 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = DEG C ************************************************************************************************************************* NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) ( 2) ( 3) ( 4) ( 5) ( 6) ( 7) ( 8) ( 9) VOLTAGE SOURCE CURRENTS NAME Vdd VIN VCM CURRENT D D D+00 TOTAL POWER DISSIPATION 3.73D-05 WATTS

16 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** OPERATING POINT INFORMATION TEMPERATURE = DEG C ************************************************************************************************************************* **** MOSFETS À nà M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 MODEL CMOSP CMOSP CMOSN CMOSN CMOSN CMOSP CMOSP CMOSP CMOSN CMOSP ID -1.27E E E E E E E E E E-06 VGS VDS VBS VTH VDSAT GM 9.54E E E E E E E E E E-06 GDS 1.65E E E E E E E E E E-07 GMB 1.18E E E E E E E E E E-07 CBD 0.00E E E E E E E E E E+00 CBS 0.00E E E E E E E E E E+00 CGSOVL 1.58E E E E E E E E E E-16 CGDOVL 1.58E E E E E E E E E E-16 CGBOVL 3.96E E E E E E E E E E-15 CGS 3.25E E E E E E E E E E-14 CGD 0.00E E E E E E E E E E-15 CGB 0.00E E E E E E E E E E+00 **** SMALL-SIGNAL CHARACTERISTICS V(4)/VIN INPUT RESISTANCE AT VIN OUTPUT RESISTANCE AT V(4) = 1.154D+03 = 1.000D+20 = 3.767D+06

17 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** AC ANALYSIS TEMPERATURE = DEG C ************************************************************************************************************************* FREQ V(4) V(3) V(7) V(8) V(2) VP(4) 1.000E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+02

18 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** AC ANALYSIS TEMPERATURE = DEG C ************************************************************************************************************************* FREQ ONOISE INOISE 1.000E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E-02

19 ***************28-APR-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:22:46*************** P Channel Opamp/Comparator **** AC ANALYSIS TEMPERATURE = DEG C ************************************************************************************************************************* LEGEND: *: V(4) +: V(3) =: V(7) $: V(8) 0: V(2) <: VP(4) (*) D D D D D+02(+) D D D D D-04 (=) D D D D D-03($) D D D D D-02(0) D D D D D-04(<) D D D D D+02 FREQ V(4) D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D < X +. $ D D-01.. X X +. $ D D-01.. < 0 X +. $ D D-01.. < 0 X +. $ D D-01.. < 0 X +. $ D D-01.. < 0X +. $ D D-01.. < X 0 +. $ D D-01.. < X 0 +. $ D D-01.. < X +0. $ D D-01.. < X + 0 $ D D-01.. <. X +. 0 $ D D-01.. <. *= +. 0 $ D D-01.. <. * = +. 0 $ D D-01.. <. * =+. 0 $ D D-01.. <. X =. X D D-02.. <.+ * =. $ D D <. *.= $ D D <. *. =$ D D <. * $ = D D <. *. $ = D D <. *. $ = D D <. * $. = D D <. * $. = D D <. * $ = D D <. * $ = D D-05. < + * $ = D D-05. < X $. = D D-06. * $ + =.. 0. <

20 ******* 2-MAY-89 ******* SPICE 2G.5 (10AUG81) *******00:47:58***** P-Channel Opamp/Comparator Common Mode Test **** INPUT LISTING TEMPERATURE = DEG C *********************************************************************** * Node 0 Vss * Node 1 Vdd * Node 2 REF * Node 3 CMV * Node 4 OUT * Node 6 POS connected to NEG * Node 7 ACL * Node 8 COMP * Node 9 REF2 * * Circuit Description * Vdd 1 0 5V M CMOSP W=3U L=2U M CMOSP W=3U L=2U M CMOSN W=3U L=26U M CMOSN W=3U L=26U M CMOSN W=3U L=13U M CMOSP W=3U L=37U M CMOSP W=3U L=37U M CMOSP W=3U L=37U M CMOSN W=3U L=26U M CMOSP W=3U L=37U * Device effective widths have been ignored * * Device Parameters *.MODEL CMOSN NMOS LEVEL=2 LD= U TOX= E-10 + NSUB= E+15 VTO=0.75 KP= E-05 GAMMA = PHI=0.6 UO= UEXP= UCRIT= DELTA= VMAX= XJ= U LAMBDA= E-02 + NFS= E+11 NEFF=1 NSS= E+12 TPG= RSH= CGDO= E-10 CGSO= E-10 + CGBO=3.46E-11 CJ= E-04 MJ= CJSW= E-10 + MJSW= PB= * Weff= Wdrawn - DeltaW DeltaW = -0.38U *

21 .MODEL CMOSP PMOS LEVEL=2 LD= U TOX= E-10 + NSUB= E+15 VTO= KP= E-5 GAMMA= PHI=0.6 UO=286 UEXP= UCRIT= DELTA= VMAX= XJ= U LAMBDA= E-02 + NFS= E+11 NEFF=1.001 NSS= E+12 TPG= RSH= CGDO= E-11 CGSO= E-11 + CGBO=2.11E-10 CJ= E-04 MJ= CJSW= E-10 + MJSW= PB= * Weff= Wdrawn - DeltaW DeltaW = -0.27U * Simulation Parameters * * Set initial voltages to speed convergence.nodeset V(2)=3.0 V(3)=3.0 V(4)=2.5 V(7)=1.5 V(8)=1.5 V(9)=1.5 * VCM AC 0.1 SIN( G).DC VCM OP.TF V(4,0) VCM.AC DEC 4 1 1G *.PRINT DC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0).PLOT DC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) (0,5).PRINT AC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) VP(4,0).PLOT AC V(4,0) V(3,0) V(7,0) V(8,0) V(2,0) VP(4,0).END

22 *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** MOSFET MODEL PARAMETERS TEMPERATURE = DEG C ************************************************************************************************************************* CMOSN CMOSP TYPE NMOS PMOS LEVEL VTO KP 5.04D D-05 GAMMA PHI LAMBDA 3.43D D-02 PB CGSO 1.16D D-11 CGDO 1.16D D-11 CGBO 3.46D D-10 RSH CJ 1.46D D-04 MJ CJSW 5.08D D-10 MJSW TOX 3.99D D-08 NSUB 1.00D D+15 NSS 1.00D D+12 NFS 1.00D D+11 TPG XJ 2.50D D-07 LD 1.34D D-08 UO UCRIT 9.90D D+04 UEXP VMAX 5.68D D+04 NEFF DELTA

23 *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** DC TRANSFER CURVES TEMPERATURE = DEG C ************************************************************************************************************************* VCM V(4) V(3) V(7) V(8) V(2) 0.000E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+00

24 1.900E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+00

25 4.200E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+00

26 *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** DC TRANSFER CURVES TEMPERATURE = DEG C ************************************************************************************************************************* LEGEND: *: V(4) +: V(3) =: V(7) $: V(8) 0: V(2) (*+=$0) D D D D D+00 VCM V(4) D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00..* X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X

27 1.650D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. * X D D+00.. *X D D+00.. *X D D+00.. X D D+00.. X D D+00.. X* D D+00.. X* D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X * D D+00.. X.* D D+00.. X. * D D+00.. X. * X D D+00.. X. * 0+..

28 3.950D D+00.. X. * D D+00.. X. * D D+00.. X. * D D+00.. X. * D D+00.. X. * D D+00.. X. X D D+00.. X. 0* D D+00.. X. 0 * D D+00.. X. 0 * D D+00.. X. 0 * D D+00.. X. 0.* D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00.. X. 0. * D D+00..X. 0. * D D+00..X. 0. * *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = DEG C ************************************************************************************************************************* NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE ( 1) ( 2) ( 3) ( 4) ( 6) ( 7) ( 8) ( 9) VOLTAGE SOURCE CURRENTS NAME Vdd VCM CURRENT D D+00 TOTAL POWER DISSIPATION 3.73D-05 WATTS

29 *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** OPERATING POINT INFORMATION TEMPERATURE = DEG C ************************************************************************************************************************* **** MOSFETS M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 MODEL CMOSP CMOSP CMOSN CMOSN CMOSN CMOSP CMOSP CMOSP CMOSN CMOSP ID -1.27E E E E E E E E E E-06 VGS VDS VBS VTH VDSAT GM 9.54E E E E E E E E E E-06 GDS 1.65E E E E E E E E E E-07 GMB 1.18E E E E E E E E E E-07 CBD 0.00E E E E E E E E E E+00 CBS 0.00E E E E E E E E E E+00 CGSOVL 1.58E E E E E E E E E E-16 CGDOVL 1.58E E E E E E E E E E-16 CGBOVL 3.96E E E E E E E E E E-15 CGS 3.25E E E E E E E E E E-14 CGD 0.00E E E E E E E E E E-15 CGB 0.00E E E E E E E E E E+00 **** SMALL-SIGNAL CHARACTERISTICS V(4)/VCM INPUT RESISTANCE AT VCM OUTPUT RESISTANCE AT V(4) = 4.987D-01 = 1.000D+20 = 3.767D+06

30 *************** 2-MAY-89 *********************** SPICE 2G.5 (10AUG81) ***********************00:47:58*************** P-Channel Opamp/Comparator Common Mode Test **** AC ANALYSIS TEMPERATURE = DEG C ************************************************************************************************************* ************ FREQ V(4) V(3) V(7) V(8) V(2) VP(4) 1.000E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E+01