EEEE 381 Electronics I

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1 EEEE 381 Electronics I Lab #5: Two-Stage CMOS Op-Amp Oeriew In this lab we will expand on the work done in Lab #4, which introduced the actiely-loaded differential pair. A second stage that is comprised of an actiely-loaded PMOS common-source amplifier will be added to the differential amplifier from Lab #4. The result is a two-stage complementary MOS (CMOS) amplifier, the CMOS designation referring to the fact that both NMOS and PMOS transistors are used. Theory A generic multi-stage amplifier haing N stages is shown in Figure 1. The indiidual stages could be MOS- or BJT-based, and they could be single-transistor stages (like common source), compound transistor stages (like a differential amplifier), or a mix of any of the foregoing. A common theory applies for determining the oltage of the oerall multi-stage amplifier irrespectie of the indiidual stage types. Note that stage k has an input resistance, Rin(k). For stages 1,,, k,, (N 1), the load on stage k is the input resistance of the next stage, Rin(k+1). For stage N, the load is the actual load, shown as RL. The gain through any gien stage depends on its load. R in(1) R in() R in(k) R in(k+1) R in(n) ~ R sig sig i1 Stage 1 o1 = i Stage o Stage ik k ok in Stage N R L o Figure 1. Generic multi-stage amplifier Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 1 of 11

2 o ( k ) Designating the oltage gain through stage k as A k, the gain of the oerall amplifier is calculated as the product of the indiidual stage gains: A o i1 N k 1 A ( k ) i ( k ). (1) In the eent where the signal source sig itself has some associated resistance Rsig, the oerall gain is gien by: G o sig R R in (1) in (1) R sig N k 1 A ( k ), () where the factor that precedes the product of the indiidual stage gains represents the oltage diision that occurs between Rsig and the input resistance of the first stage, Rin(1). The small-signal output resistance for a MOSFET operating in the saturation region is gien by 1 where is a technology-dependent parameter for a gien channel length. Note that r o I D ro aries inersely with the DC bias current. The alue of for each transistor can be determined by measuring the output resistance at a gien bias point, as was done in Lab #. Channel-length modulation increases the magnitude of the drain current in a MOSFET aboe its first-order saturation alue that is gien by I Dsat k W n V V (3) GS tn L for an NMOS deice. When the effect of channel-length modulation is included, the more accurate calculation of the drain current is gien by I Dsat k n k p W L 1 V GS W L 1 V SG V tn V tp n V DS p V SD for for NMOS PMOS, (4) Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page of 11

3 Pre-Lab A two-stage CMOS amplifier is shown in Figure. The first stage is an actiely-loaded differential amplifier comprised of M1 M4. It is biased using the M6 current source. The second stage is a PMOS common-source amplifier (M7). Transistor M8 proides bias current for M7 and functions as an actie load on M7. The RD7 and RD8 resistors can be used to center the DC output oltage at 0 V (only one of them is needed; the other one should be 0 i.e., omitted). (Channel-length modulation would hae to be taken into account if calculating the DC oltage at the output by hand.) +5 V M 3 M 4 V DD 5 V R I REF M 1 10 M + 51 sig ~ 1 kz id 1 k 100 F M 7 R D7 R out8 R out 100 F o R L 0 k R D8 V SS 5 V M 5 M 6 I o V com M 8 R S = 00 5 V Figure. Two-stage CMOS amplifier Assume the following parameters for the CD4007 deices: Vtn = 1.4 V, Vtp= -1.6 V, k = 60 A/V, k = 3 A/V, W for NMOS = 170u, L=10u, W for PMOS = 360u, L=10u, n n =0.01 and p =0.0 p Design the two-stage amplifier to meet two specifications: (1) The oerall small-signal gain, A o / id 40 V/V (47.6 db). () The DC output oltage at the node between M7 and M8 = 0 V 0.1 V; Your calculated alue of R must be rounded to a standard 10% resistor alue, then the actual small-signal gain must be re-calculated. Set RD7 = RD8 = 0 Ω in your initial design. (continued) ***** There is not a unique design solution ***** Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 3 of 11

4 Calculate the minimum alue of Vcom (a DC alue) that is needed to ensure proper operation of the differential amplifier (i.e., all transistors in saturation). (Since the lower power supply is 5 V, it is possible that Vcom could be negatie.) Simulate the circuit and compare the simulation results to your hand calculations. Explain any discrepancies, re-design if necessary, and adjust RD7 or RD8 to center your DC output oltage to 0 V. Use standard 10% alues for RD7 or RD8. Calculate the output resistance of M8 (Rout8) and the output resistance Rout of the oerall amplifier. Lab Exercise Using three CD4007 packages, build the circuit in Figure 3. (The pin diagram for the CD4007 package is shown in Figure 4.) Measure the 10 resistor yourself and record the actual resistance prior to inserting it in the circuit. The 51 Ω resistance (shown as a standard 5% resistor alue) can be implemented as two 100 Ω resistors in parallel. The 51 Ω /1 kω oltage diider proides a controllably small id in order that the oltage swing at the output o is still in the linear range of amplification i.e., to ensure that none of the MOSFETs are drien out of saturation. CD V M3 M 4 V DD 5 V R I REF M 1 M 10 + id 1 k 100 F 51 sig 1 kz ~ R D7 R out8 R out CD F o R L 0 k R D8 V SS 5 V M5 M6 I o V com M 8 R S = 00 CD V Figure 3. Two-stage CMOS amplifier with scaled signal generator differential input. Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 4 of 11

5 Note that all NMOS body connections (pin 7) go to the lowest supply ( VSS). Since we are using a separate chip for M1 and M from the one for M5 and M6, we could eliminate body effect in M1 and M by connecting their bodies directly to their sources. Howeer, that is not realistic because all the NMOS bodies are common in an integrated circuit, tied to the lowest potential in the circuit (not always true). (Also, all the PMOS substrates (bodies) are common, tied to the highest potential in the circuit.) The substrate (pin 14) of the PMOS deice must be connected to the most positie supply oltage (VDD). Apply power to VDD before connecting the input signal. Remoe the input signal before disconnecting power. Make sure you are grounded before touching the pins of the CD4007 MOSFET package. 1) Verify that the M6 current source is sinking approximately the designed amount of current from the differential amplifier. This can most easily be accomplished by measuring the oltage drop across the 10 resistor and diiding by the actual measured resistance that you recorded earlier while building the circuit. ) A small-signal differential input must be applied. Note that the signal generator connection in Figure 3 is superimposed on the DC common mode oltage supply Vcom (use the power supply s ariable +6 V output for Vcom). Set Vcom = 0 V initially. It will be adjusted in step (3) below. The output sig from the signal generator has been scaled so that the input to the differential amplifier can be adjusted to about id = 5 mv. Set the signal generator sig to a sine wae of 1 khz frequency and 100 mv amplitude. Make sure that the signal generator is in High Z mode. 3) A common-mode DC supply must be proided in addition to the differential signal to bias the amplifier in the linear operating region (all transistors in saturation). Place a scope on the output signal node (o) and carefully adjust the Vcom DC supply from zero olts until you see an undistorted sine wae on the display. Compare this alue of Vcom to the alue calculated in your pre-lab preparations. Caution: You must get Vcom up to a point where the transistors are operating properly i.e., in saturation. It is not sufficient to merely get a response at the output node. (You will get a response as soon as there is some current flowing. You will also see amplification of the differential input signal, albeit distorted.) You must get Vcom up the point where your current source is operating properly i.e., at the designed current leel. All your results will be inalid if this is not done properly. If Vcom is too low, M6 will not be in saturation. You must monitor the current in M6 and erify that you are getting the desired current. (continued) Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 5 of 11

6 4) Measure the DC output oltage at the node between M7 and M8. Add RD7 OR RD8 (not both) to adjust it to 0 V 0.1 V. 5) Measure the differential mode oltage gain of the amplifier in Figure 3 for an input signal of id = 5 mv at 1 khz. N.B.: The two-stage CMOS amplifier of Figures and 3 will be used in Lab #6, so you may wish to keep it assembled once you hae it working properly. Summary and Discussion Summary of questions to be addressed: Is the alue of Vcom obtained in part (3) of the lab exercise consistent with the alue you calculated in your pre-lab preparations? What is the differential-mode oltage gain at 1 khz? Is it consistent with your pre-lab calculations? What discrepancies hae you noted in your lab measurements compared to your calculated alues? How can you account for any obsered differences? Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 6 of 11

7 Appendix A PSPICE Instructions Please refer to the following for assistance in modifying the MbreakN MOSFET model. You also need to modify the MbreakP model similarly see the spice model aboe for alues for W, L, NRD, and NRS. We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7. Right Click on the transistor and select Edit Properties, Piot, Display, Apply Finally, we want to let PSPICE know where to find the text file that has the SPICE MODEL in it. That is done by editing the PSPICE simulation profile. Under the Configuration Files Tab, select Include, and then Browse to the Location of the file where the SPICE model is. (Note: you should hae already placed the text file that has the RIT4007N7 SPICE model in it on your computer in some location) Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 7 of 11

8 Appendix A SPICE Instructions Please refer to the following for assistance in modifying the MbreakN MOSFET so that it represents the NMOS FETs in the CD4007 chip. We want to place the MbreakN Schematic symbol on our schematic then edit and display the properties to represent the CD4007 transistors. We also want to change the name of the spice Model from MbreakN to RIT4007N7. Right Click on the transistor and select Edit Properties, Piot, Display, Apply Finally, we want to let SPICE know where to find the text file that has the SPICE MODEL in it. That is done by editing the SPICE simulation profile. Under the Configuration Files Tab, select Include, and then Browse to the Location of the file where the SPICE model is. (Note: you should hae already placed the text file that has the RIT4007N7 SPICE model in it on your computer in some location) Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 8 of 11

9 *SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER *LOCATION DR.FULLER'S COMPUTER *and also at: * * *Used in Electronics II for CD4007 inerter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.059 NRS=0.059.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD= MOBMOD=1 +TOX=4E-8 XJ=.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=.0E-7 LINT=1E-7 +NGATE=5E0 RSH=300 JS=3.3E-8 JSW=3.3E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.6E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inerter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=80u Ps=80u NRS=0.07 NRD=0.07.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD= MOBMOD=1 +TOX=5E-8 XJ=.6E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E0 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.8E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) * These are two of the seeral SPICE models in the text file RIT_SPICE_Models.txt proided on the lab webpage. You should download the entire text file and place it on your computer. You can include all the models by telling SPICE the location of the downloaded file as shown on the page aboe (page 8). SPICE will actually only use the models called for by the deices in your schematic. Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 9 of 11

10 Enlarged CD4007 Pin Out Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 10 of 11

11 Check-Off Sheet A. Pre-Lab Design of the two-stage amplifier to achiee small-signal oltage gain and DC output oltage specifications: determination of R, RD7, and RD8. Calculation of output resistances of M8 and the oerall amplifier. Calculation of the minimum acceptable alue of Vcom. PSPICE simulation of the oerall amplifier; comparison to hand calculations. B. Experimental Two-stage amplifier built and tested: erification of designed current amount in current source; determination of Vcom leel needed for proper operation; measurement of differential-mode gain. TA Signature: Date: Electronics I EEEE 381 Lab #5: Two-Stage CMOS Op-Amp Re 017 Page 11 of 11