Differential Amplifier with Current Source Bias and Active Load

Transcription

1 Technical Memo: Differential Amplifier with Current Source Bias and Active Load Introduction: From: Dr. Lynn Fuller, Professor, Electrical and Microelectronic Engineering, Rochester Institute of Technology Date: February 22, 2017 The differential amplifier with current source bias and active load is a fundamental building block for analog integrated circuits. A good current source with a high value of source resistance will make the common mode gain negligible. Active loads (or current mirror) can provide high differential voltage gain. The exact results depends on the small signal transistor output resistance, ro. Abstract: This document investigates the DC and small signal operation of the differential amplifier with current source bias and active load. Simple hand calculations, SPICE simulations and electrical measurements are compared and evaluated. It was found that the value of the small signal transistor output resistance, ro, is the most important parameter to have correct if the results from hand calculations, SPICE and measurements are to agree. The value of ro comes from the inverse slope of the ID vs. VDS family of curves at the Q point. The Q point is determined by the transistor current ID and the voltages VDS and VGS. (Similarly for BJT differential amplifier with current source bias and active load, the Q point is determined by the transistor current IC and the voltages VCE and VBE.) It was found that there is a lot of discrepancy in the value of ro but if careful attention is given to use the same value for hand calculations, SPICE and measurements the results will agree.

2 3 2 1 With both transistor inputs equal to zero and the load resistor R2 infinite. The IEE current splits equally. In this case 1.949mA each. The gate to source voltage for M3 and M4 are equal at VDS is for both M4 and M3. The gate to source voltage for M1 and M2 is same for each because both gates go to zero and both sources are tied together in the differential amplifier configuration. The same gate to source voltage and same drain current means the drain to source voltage is the same for M1 and M2. Thus Voutput and V drain of M1 are both volts. PMOS Vds Vgs=3 Q 3&4 Vgs=4 Vgs=5 Ids-mA Ids-mA NMOS Vgs= Q 1&2 Vgs=4 Vgs= Vds 5

3 3 2 1 With both transistor inputs equal to zero and the load resistor R2 equal to 10K. The IEE current splits but not exactly equally even though both M4 and M3 have the same gate to source voltage. Some current goes to the load. This can happen if the voltage drain to source is different for M4 and M3 and there is slope in the saturation region of the transistors (lambda or channel length modulation). The Q point for M3 is at slightly higher current than for M4 because the VDS for M3 is almost a volt larger. PMOS Vds Vgs=3 Q3 Vgs=4 Q4 Vgs=5 Ids-mA Ids-mA NMOS Vgs= Q2 Q1 Vgs=4 Vgs= Vds 5

4 Lets return to the infinite load and apply a differential input of 0.1 volts DC to the gate of M1. With higher voltage on the gate of M1 than on the gate of M2 there is more current in M1 than in M2. the gate to source voltages of M4 and M3 are the same but the currents are different because of slope in the saturation region. M4 is operating at VDS of while M3 is operating at VDS of 1.64 volts. This gives lower current for M3 and M2. Voutput changes to (from for zero differential voltage input case) giving a gain of 22.1 V/V. This gain is dependent on the slope in the saturation region 50 for the transistors (small signal ro for M3 and M2). 25 Gain ~40 SEL>> 0 5.0V D(V(Voutput)) 0V Vout vs Vin -5.0V -500mV 0V 500mV V(Voutput)

5 Lets return to the infinite load and apply a differential input of 0.1 volts sinusoid to the gate of M1. This gain is dependent on the slope in the saturation region for all the transistors. Gain is Vout p-to-p / Vin p-to-p = 39 V/V 50mV 0V Vin SEL>> -50mV 4.0V V(Input) Gain = 39V/V 2.0V 0V Vout -2.0V If ro2 is 80K ro3 is 80K gm2 is 2m Vo/Vin = ½ 2m (80//80)K = 40 V/V 0s 1.0ms 2.0ms 3.0ms V(Voutput) Time

6 MOSFET models do not use LAMBDA (since early 1980 s), rather SPICE models use a set of complicated equations based on a calculation of effective channel length, Leff. This allows SPICE models to show more correct behavior in the saturation region. For example the figures below show measured and SPICE simulated Id-Vds family of curves. A single slope in the saturation region (LAMBDA) will not give the correct behavior, similarly gm is not a number but depends on Q point including the applied gate voltage. 9.5mA gm Measured Simulated 9.5mA gm

7 DIFFERENTIAL AMPLIFIER GAIN CALCULATIONS Diff Amp Hand Calculations: Differential Gain Vodiff/Vindiff = gm ro//ro//rl Single Sided Gain Voss/Vindiff = ½ gm ro//ro//rl See Sedra and Smith, pages It specifically talks about the differences between differential and single ended outputs. It says that using load resistors you get 1/2 the gain if you take your output single ended. But it says that you can fix this by using a current mirror load, which provides a matching current of the one drawn by the driving transistors and results in Iout=(2*Id/2) to the output. This compensates the 1/2 loss. It is the use of a current-mirror in the load that leads to a gain of Avss = gm(ro2//ro4//rl) for single ended outputs using current mirror load. I do not think this is correct. The current mirror does not match currents it matches the gate to source voltages of the two transistors (or for BJT s the base to emitter voltages of the two transistors) Only if ro is infinite will the currents be the same. Otherwise the currents can be slightly different giving different voltage drops across the two transistors. These voltage differences can be large. ro comes from lambda: Assume l=0.01 for NMOS and l=0.02 for PMOS ro for NMOS = (1/l) (1/ID) = 1/0.01 1/2m = 50K ohm ro for PMOS = (1/l) (1/ID) = 1/0.02 1/2m = 25K ohm I do not think the above expressions for ro are correct. Using Early voltage and IC might be correct for BJT s. Dr. Jim Early proposed the voltage, VA, to obtain the slope of the IC vs VCE family of curves at different currents. Applying the same to MOSFETs does not work very well. We need a value of ro for hand calculations to represent the small signal output resistance in our transistor models. The value for ro is only valid for small changes near the Q point. Determining the ro = 1/slope of the ID vs VDS curve at the Q point is valid.

8 Measured CD4007 NMOS Id vs Vds Family of Curves Extraction of Lambda, gm and Vt from measured Ids vs Vds Family of curves. ID DID = 1.1ma l = slope/idsat = /5.837ma = ~0.01 ro = 1/slope = 20.9K ohms VGS = 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V DVG = 0.5V gm = DID/DVG =1.1ma/0.5V = 2.2m S Vt = VGS where ID ~ zero = ~1.4V

9 Measured CD4007 NMOS Id vs Vgs Family of Curves gm = did/dvg ID VG = VD gm = Vt = x-intercept = ~1.38V Extraction of gm from measured Ids vs Vgs in saturation region Vdg = 0 Extraction of gm from measured Ids vs Vgs in linear region Vds = 0.1V

10 Measured CD4007 PMOS Id vs Vds Family of Curves CD4007 PMOS at 5 Volts CD4007 PMOS at 10 Volts gm = DID/DVG =1.0ma/0.5V = 2.0m S gm = DID/DVG =2.3ma/1V = 2.3m S ro = 1/slope = 5.9K ohms l = slope/idsat = m/3.74ma = Use l = ~0.02 l = slope/idsat = 0.682m/17.2ma = Since the x-intercept is so different the Early voltage concept is not valid. The PMOS devices are probably buried channel devices in the CD4007 chips.

11 The question is what is SPICE using to determine the slope in the saturation region? The answer is that there is no single value in the spice model that does that (no LAMBDA). No problem, we can have SPICE generate the family of curves and determine the slope in the saturation region near the Q point and find ro = 1/ slope. We can also find gm in the saturation region. Circuit for Ids-Vds Family of curves for Vgs steps Circuit for Ids-Vgs Saturation Region Circuit for Ids-Vs Linear Region Sweep V3, 0-5V, 0.001V increments Step V2, 0-5V, 1V steps Sweep V2, 0-5V, 0.001V increments Plot Id and gm Sweep V2, 0-5V, 0.001V increments Plot Id and gm

12 The hand calculations for voltage gain needs values for gm and ro for both NMOS and PMOS. We can obtain values near the Q point if the SPICE model gives the correct behavior (verify by matching simulated to measured) we can find gm and ro near the Q point. In the example below we generate Id-Vg curves to find gm and we generate the Ids-Vds family of curves to find slope at the Q point. ro is 1/slope. Q point: IDS=1.91mA, Vds=4.5V 4.0m gm 8.0mA gm = 2mS 2.0m 6.0mA Vgs= mA D(ID(M1)) 4.0mA Vgs=4 4.0mA 2.0mA Vgs=3 Ro = 1/slope = 80K SEL>> 0A 0V 2.0V 4.0V 5.0V ID(M1) Vgs V_V2 0A 0V 2.0V 4.0V 5.0V ID(M1) Vds V_V3

13 The hand calculations for voltage gain needs values for gm and ro for both NMOS and PMOS. We can obtain values near the Q point if the SPICE model gives the correct behavior (verify by matching simulated to measured) we can find gm and ro near the Q point. In the example below we generate Id-Vg curves to find gm and we generate the Ids-Vds family of curves to find slope at the Q point. ro is 1/slope. 4.0m Q point: IDS=1.91mA, Vds=3.85V Vgs=3 2.0m Vgs=4 Ro = 1/slope = 80K SEL>> 0 0A D(I(M2:d)) Vgs=5-4.0mA -8.0mA -5.0V -2.5V 0V ID(M2) V_V2 Vgs Vds

14 Measured CD4007, Id-Vds Family of Curves for 5, 10 and 20 volt Operation These measurement made using HP4145 Semiconductor Parameter Analyzer NMOS at 5Volts NMOS at 10Volts NMOS at 20Volts PMOS at -5 Volts PMOS at -10 Volts PMOS at -20 Volts Note: slope in the saturation region can be very different at different points on the family of curves.

15 SPICE MODELS FOR CD4007 MOSFETS *SPICE MODELS FOR RIT DEVICES AND LABS - DR. LYNN FULLER *LOCATION DR.FULLER'S COMPUTER *and also at: * * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=170u Ad=8500p As=8500p Pd=440u Ps=440u NRD=0.059 NRS=0.059.MODEL RIT4007N7 NMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=4E-8 XJ=2.9E-7 NCH=4E15 NSUB=5.33E15 XT=8.66E-8 +VTH0=1.4 U0= 1300 WINT=2.0E-7 LINT=1E-7 +NGATE=5E20 RSH=300 JS=3.23E-8 JSW=3.23E-8 CJ=6.8E-8 MJ=0.5 PB=0.95 +CJSW=1.26E-10 MJSW=0.5 PBSW=0.95 PCLM=5 +CGSO=3.4E-10 CGDO=3.4E-10 CGBO=5.75E-10) * *Used in Electronics II for CD4007 inverter chip *Note: Properties L=10u W=360u Ad=18000p As=18000p Pd=820u Ps=820u NRS=O.027 RD=0.027.MODEL RIT4007P7 PMOS (LEVEL=7 +VERSION=3.1 CAPMOD=2 MOBMOD=1 +TOX=5E-8 XJ=2.26E-7 NCH=1E15 NSUB=8E14 XT=8.66E-8 +VTH0=-1.65 U0= 400 WINT=1.0E-6 LINT=1E-6 +NGATE=5E20 RSH=1347 JS=3.51E-8 JSW=3.51E-8 CJ=5.28E-8 MJ=0.5 PB=0.94 +CJSW=1.19E-10 MJSW=0.5 PBSW=0.94 PCLM=5 +CGSO=4.5E-10 CGDO=4.5E-10 CGBO=5.75E-10) *

16 CALCULATIONS FOR DIFF AMP CURRENT SOURCE Current Source Hand Calculations: Assume transistors are in saturation I Dsat = µw Cox (Vg-Vt) 2 2L NMOS SPICE model shows: VT=1.4, KP=UO Cox =60uA/V2 NMOS Parameters shown as: L=10u, W=170u, NRD=0.059, NRS= PMOS SPICE model shows: VT=1.65, KP=UO Cox = 23uA/V2 PMOS parameters as: L=10u, W=360u, NRD=0.027 NRS= For the current source: ID = 4mA = 0.5(60uA/V 2 )(170u/10u)(VG-1.4) =(VG-1.4) 2 VG=4.2 SPICE GIVES=4.37 Measured from family of curves gives Vg=4.3

17 Active loads are also used for BJT differential amplifiers. Similar results will be obtained.

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19 ACTIVE LOADS CURRENT MIRROR +V I1=IE/2 + vi1 - Vo1 T1 -V T2 IE I2=IE/2 Vo2 + vi2 - DC Analysis: 1. IE is constant current. 2. I1 = I2 = IE/2 3. Vo1 = V -0.7 actually Vo1 = V KT/q ln I1/IS 4. Vo2 = V VEB1-VBC2 Vo2 = V KT/q ln I1/Is VBC2 When Vin1=Vin2=zero and I1=I2=IE/2 we have everything balanced and VBC2=VBC1=0 thus Vo2=V When Vin1 > Vin2 then I1 > I2 and Vo2 rises toward +V Note: p-p signal swing is about 1 volt

20 SMALL SIGNAL ANALYSIS OF DIFF AMP WITH ACTIVE LOAD Vo1 + vi1 - T1 IEE -V +V T2 REE Let V1,V2 and V3 be node voltages at node 1,2 and 3, summing currents KCL at node1 (b+1)(vin1 V1)/rp1 + (V2-V1)/ro1 + (V3-V1)/ro2+ (b+1)(vin2-v1)/rp2 V1/REE = 0 at node2 V2/Rd+V2/rp4 + (V2-V1)/ro1 + b(vin1-v1)/rp1 = 0 Vo2 + vi2 - + Vin1 - at node3 bv2/rp4+v3/ro4 + (V3-V1)/ro2 + b(vin2-v1)/rp2 = 0 ib1 rd 2 rp1 bib1 ro1 ro2 1 - vbe + ib4 rp4 bib2 bib4 3 rp2 ro4 ib + Vin2 -

21 SMALL SIGNAL ANALYSIS OF DIFF AMP WITH ACTIVE LOAD Rearranging: at 1 at 2 [-1/REE-(b+1)/rp1-1/ro1-1/ro2-(b+1)/rp2]V1+[1/ro1]V2+ [1/ro3]V3 = RHS a1 RHS = -Vin2(b+1)/rp2 Vin1(b+1)/rp1 [-1/ro1-b/rp1]V1 +[1/Rd+1/rp4+1/ro1]V2+ 0 V3= -bvin1/rp1 a2 a3 at 3 [-b/rp2-1/ro2]v1+b/rp4v2 + [1/ro4+1/ro2]V3 = -bvin2/rp2 a4 a5

22 SMALL SIGNAL ANALYSIS OF DIFF AMP WITH ACTIVE LOAD Using Cramer s rule and determinants a1 a2 a4 1/ro1 a3 b/rp4 [-Vin2(b+1)/rp2 Vin1(b+1)/rp1] -bvin1/rp1 -bvin2/rp2 V3 = a1 a2 a4 1/ro1 a3 b/rp4 1/ro3 0 a5

23 SMALL SIGNAL ANALYSIS OF DIFF AMP WITH ACTIVE LOAD Example: let ro1= ro2 = ro3 = 50K rp1 = rp2 = rp3 = 2K b =100, rd =20, REE = infinite a) If Vin1=1/2 volt and Vin2= -1/2 volt Find V3 = 1246 Therefore Avd = 1246 Simple Hand Calculation: Avd = ½ gm Rc = 1250 b) If Vin1=1 volt and Vin2= 1 volt Find V3 = Therefore Avc = c) CMMR = 1246/ = 2.44e7