The basic inverter circuit or common-source amplifier using a resistive load is shown in Figure 1. source s

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1 of 0 MOS FET Inverter Amplifier The basic inverter circuit or common-source amplifier using a resistive load is shown in Figure. g d Io gate R L drain in in rds R L out out in source s Figure Common-source / Inverter amplifier using a resistive load The gain is approximately time the load resistance RL:- oltage Gain A v A O O IN - IN ( r //R ) ds L A r - rds ds.r L + R L Input Resistance R IN Output Resistance O R IO r ds //R L Current Gain A i A i The problem with this circuit is to increase the gain we have to increase the load resistor, which will lower the current. We ideally need a high impedance load that is independent of voltage and an ideal resistor replacement is the CMOS active diode load shown in Figure.

2 of 0 I out DD M SAT + ON M out SAT + ON N Type Diode Type Diode I Figure Realisation of a diode using both N and type CMOS Fets The equivalent input resistance of the active diode (looking into the source) is:- R go λ.i DS DD I M M out in Figure 3 Inverter (Common-source) Amplifier with active diode load The output load of the inverter, is dominated by the low impedance of the diode load ie

3 3 of 0 R K ( W /L ).I DS And the gain will be:- A O O IN - IN ( R ) -. + Av Av -.R g We can relate the gain to the geometry of the gates (ie W and L) as follows:- A - K N.W N.L K.W.L N Example Calculate the gain of an active inverter with W/L ratios of, Kn0uA/, Kp50uA/, λ 0.05; T 0.7. I D set to 00uA. First set the correct current to 00uA, so we need to determine the correct vgs to apply to the N-type FET. IREF 00E gs Kp 0E T.65 K N.W N.LN 0E - 6 A - K.W.L 50E (Inverted) The simulation of this circuit is shown in Figure 4 with the resulting simulated results shown in Figure 5. Note The example shows that this amplifier is low gain as the W/L ratios are in a square root term so this amplifier is used for speed applications.

4 4 of 0 AC AC Start.0 MHz Stop500 MHz DC DC AC DC _DC SRC dc5 I_robe IDS vout MOSFET_MOS MOSFET ModelMOSFETM LengthL um WidthW um _AC SRC4 dcgs acpolar(,0) Freqfreq MOSFET_NMOS MOSFET ModelMOSFETM LengthL um WidthW um LEEL_Model MOSFETM NMOSyes to0.7 Kp0e Gamma0.57 hi0.8 Lambda0.04 Cgso0e- Cgdo0e- Cgbo700E- Cj770e- Mj0.5 Cjsw380e- Mjsw0.38 LEEL_Model MOSFETM MOSyes to0.7 Kp50e Gamma0.4 hi0.7 Lambda0.05 Cgso0e- Cgdo0e- Cgbo700E- Cj560e- Mj0.5 Cjsw350e- Mjsw0.35 ar Eqn AR AR W DS5 GS.65 L Figure 4 Active inverting amplifier used in the example.

5 5 of 0 mag(ac.vout) freq, MHz DC.vout 3.59 DC.IDS.i 3.3uA Figure 5 Simulated results from the calculations of example simulated using the ADS simulation of Figure 4. Frequency Response The frequency response of the inverting amplifier is dependant on the parasitic charge storage capacitances around the device terminals. The dominating capacitance is the gate to drain overlap capacitance Cdg as shown in Figure 6. Other smaller capacitances are the bulk-drain (Cbd) and gate-source overlap (Cgs). Calculations of the parasitic capacitances are made from the device data on CGSO, CGDO and CGBO. For the saturation region these are as follows: Cgb CGBO(L ) Cgs CGSO(W ) Cox(W )(L ) Cgd CGDO(W ) L L - (LD) and W W - (WD) Where LD diffussion length (rocess dependant) WD diffusion width (rocess dependant)

6 6 of 0 Cgs DD 5 I M Cbd Cgd in Cbd out DC.65 for 00uA Cgs M Figure 6 arasitics ecting frequency response of the Inverting amplifier ole R ( C + C ) DG oltage Gain (db) Zero C DG Freq Figure 7 Frequency response of the inverting amplifier showing how the voltage gain response is ected by the pole and zero caused by the gate to drain capacitance on M.

7 7 of 0 Note that C Cgd+Cbd+Cbd+C L in most cases CL will dominate with small gate geometries. Example Estimate the frequency response of the inverter with W & L um, Load capacitor pf, FET parasitics as per Figure 4. Also calculate the maximum output voltage swing of the amplifier. Cgb CGBO(L) 770E - x E 0.77fF Cgs CGSO(W ) Cox(W)(L) ( 00E x E ) + ( 0.67x4.7E xe xe ).88fF Cgd CGDO(W) 00E - x E 0.fF R 0KΩ K /.00E ( W /L ).IDS.50E ( ) K ( W/L).I DS K N ( W/L ).I x 0E ( ) DS /.00E.48E - 4 A/ K ( W/L).I x 50E ( /.00E ) E - 4 A/ DS E - 4 oltage Gain A v E dB (MAX) DD - T (MIN) DD DD - T - T - β + β E E 4 oltage swing

8 8 of 0 Zero C DG.48E 00E x0 9 rads/sec Frequency of zero 0.74x0.π 9 7MHz ole R 3 ( C ) 0E ( E ) 00x0 6 rads/sec As the load capacitance dominates in this example 00x0 Frequency of pole.π 6 5.9MHz To check these rough calculations the circuit was simulated with the correct process data (based a 0.8um Silicon-gate bulk CMOS n-well process) using ADS with the circuit shown in Figure 8.

9 9 of 0 I_robe IDS _AC SRC4 dcgs ac Freqfreq _DC SRC dc5 vout MOSFET_MOS MOSFET ModelMOSFETM LengthL um WidthW um MOSFET_NMOS MOSFET ModelMOSFETM LengthL um WidthW um ar Eqn AR AR W DS5 GS.59 L C C C pf DC DC DC AC AC AC Start.0 MHz Stop000 MHz LEEL_Model MOSFETM NMOSyes to0.7 Kp0e Gamma0.4 hi0.7 Lambda0.04 Cgso0e- Cgdo0e- Cgbo700E- Cj770e- Mj0.5 Cjsw380e- Mjsw0.38 Tox4.7e-4 LEEL_Model MOSFETM MOSyes to0.7 Kp50e Gamma0.57 hi0.8 Lambda0.05 Cgso0e- Cgdo0e- Cgbo700E- Cj560e- Mj0.5 Cjsw350e- Mjsw0.35 Tox4.7e-4 Figure 8 AC simulation setup for the inverter given in Example.

10 0 of db(ac.vout) m m freq8.79mhz db(ac.vout).564 E6 E7 E8 E freq, Hz DC.vout DC.IDS.i 99.83uA Eqn phase(ac.vout)-80 m freq0.3mhz m -00 E6 E7 E8 E9 freq, Hz Figure 9 Simulation of Inverting Amplifier of Example. The phase plot has been normalised to 0 degrees and shows the pole and zero breakpoints (at approximate frequencies of 8MHz and 00MHz respectively.