Lecture # 16 Logic with a State Dependent Device. Logic Gates How are they built in practice?

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1 EECS 42 Introduction to Digital Electronics Andrew R. Neureuther These viewgraphs will be handed out in class 1/21/ Lecture # 16 Logic with a State Dependent Device S&O pp. 9-9, 4-6 (read for graphs and not physics or equations), plus Handout of these viewgraphs. A)State Dependent Device vs. B)Load Line Analysis for Logic Levels C)Voltage Transfer Characteristics VTC = plot of vs. D) 42S_NMOS Pull-Down Device and Logic EECS 42 Intro. Digital Electronics, Fall Logic Gates How are they built in practice? Pull up Network V SUPPLY A Valve is a Transistor Current flows when is high Can be modeled by a 1kΩ resistor Valves in Series => NAND A Array of Fan Out Signals Valves IN = ff B A,B,C Ground Valves in Parallel => NOR What goes in this box? A B How does it affect digital performance? 1

2 Digital Logic from State-Dependent Three-Terminal Devices Three-terminal devices such as MOS transistors have output characteristics (such as vs. curves) on the output side that can be programmed by changing signals on the input side (such as the input voltage). The input voltage can thus be viewed as changing or programming the State of the output of the device. Three-terminal devices whose input voltage or State can be programmed can be used to make digital logic devices for computers whose outputs respond to input signals. EECS 42 Intro. Digital Electronics, Fall State-Dependent Three-Terminal Device Element Input for Control Signal to set the State 2

3 State-Dependent Device vs. = Only four states or input values are shown but typically there is a continuum of states. Depending on the state the output vs. is constrained to be on one of these curves by the three-terminal device. EECS 42 Intro. Digital Electronics, Fall Terminology for a Logic Circuit Pull-Down (NMOS) Pull-Up Network = Set of devices used to carry current from the power supply to the output node to charge the output node to the power supply voltage. Pull-Down Network = Set of devices used to carry current from the output node to ground to discharge the output node to ground. = Power supply voltage (D is from Drain) we do not draw the symbol. = Current for the device under study. V TD = Threshold Voltage value of at which the Pull-Down (NMOS transistor) begins to conduct. -SAT-D = Value of beyond which the current -D saturates at the (drain) current saturation value -SAT-D.

4 Thevenin Model For Pull-Up Device V THEVENIN = SHORT CIRCUIT = ( / ) Example: = V and = kω V THEVENIN = V SHORT CIRCUIT = µa Thevenin looking this way EECS 42 Intro. Digital Electronics, Fall Thevenin Model For Pull-Up Device vs. For the Pull-Up Resistor and vs. is constrained to be on this line by the circuit external to the three-terminal device V THEVENIN 4

5 Composite Current Plot for the Logic Circuit Three-Terminal Device Plus Load Line for the Pull-Up Device vs. = V THEVENIN For a given state only one point satisfies both the external circuit and the threeterminal device Note that when is low current flows and power is consummed EECS 42 Intro. Digital Electronics, Fall Voltage Transfer Function for the Logic Circuit Sketch the curve = (V)

6 Voltage Transfer Function: vs. The vs. characteristic is another view of the logic gate that is used to determine the inverting and noninverting nature of a gate. Inverting type Noninverting type = VIN = (V) (V) EECS 42 Intro. Digital Electronics, Fall Saturation Current 42S_NMOS Model Current only flows when is larger than the threshold value V TD and the current is proportional to up to -SAT-D where it reaches the saturation current I OUT SAT D Example: k D = 2 µa/v 2 V TD = 1V -SAT-D = 1V = k D ( VIN VTD ) VOUT SAT D Note that we have added an extra parameter to distinguish between threshold (V TD ) and saturation (-SAT-D ). Use these values in the homework. State V Saturation (with ) I µ A = 2 V 2 = ( V 1V ) 1V A OUT SAT PD µ Linear (with ) -SAT-D 6

7 Drawing as function of and for the 42S_NMOS Pull-Down Device The equations are expressly designed for EE42 to make it very simple to draw vs. 1) For < V TD, the current is zero. 2) For > V TD, first evaluate the current at = -SAT-D and plot the single point (, ) ) Draw a line from this point to the origin to create the linear region. 4) Draw a horizontal line from this point to create the saturation region 2 State V Saturation (with ) Linear (with ) V OUT-SAT-D EECS 42 Intro. Digital Electronics, Fall States of 42S_NMOS are Voltage Levels of Current is flat (saturated) beyond -SAT-D State or = V State or V Current is zero until is larger than V TD State 1 or = 1V (Drain) current saturation values -SAT-D = µa -SAT-D = µa The maximum voltage is -SAT-D = µa = -SAT-D 7

8 Composite Current Plot for the 42S_NMOS Logic Circuit (Open Load) = V THEVENIN (Open Load) EECS 42 Intro. Digital Electronics, Fall Composite Current Plot for the 42S_NMOS Circuit with kω Load to Ground (Open Load) (KΩ Load) = V THEVENIN (KΩ Load) =. V V THEVENIN (Open Load) R LOAD (KΩ) 8

9 Voltage Transfer Function for the 42S_NMOS Logic Circuit w/wo Load Open Load Complete a VTC like this for the device in the Homework KΩ Load = (V) 9