Microelectronics, BSc course
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1 Microelectronics, BSc course MOS inverters
2 Overview of MSOFET types Microelectronics BSc course, MOS inverters András Poppe, BME-EET
3 Characteristics of enhancement mode MOSFETs inversion layer Now we calculate with this! triode region saturation Microelectronics BSc course, MOS inverters András Poppe, BME-EET
4 Simple model of MSOFETs The simplest (logic) model: mo conduction (off) / conduction (on) V GS Gate Source (of carriers) Drain (of carriers) enhancement mode device Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T "open" "short" Microelectronics BSc course, MOS inverters András Poppe, BME-EET
5 Let's construct an inverter! Resistor at supply voltage (V DD ) Other end connected to ground () through a swithc Switch controlled by a logic signal: 1 (V DD level) "short" 0 ( level) "open" The output is the common node of the switch and the resistor load resistor V DD IN Microelectronics BSc course, MOS inverters András Poppe, BME-EET
6 Let's construct an inverter! IN = 1 switch "on" aoutput connected to = 0 V DD IN = 0 switch "off" output floating at V DD = 1 V DD IN IN Microelectronics BSc course, MOS inverters András Poppe, BME-EET
7 Two switches in series: NAND gate V DD If A and B equal to 1, then =0 A B serial conduction path This is the NOT (A AND B) function, i.e. NAND In practice with max inputs. If there are parallel conductions paths then we get the NOR function Microelectronics BSc course, MOS inverters András Poppe, BME-EET
8 The scheme of the NOR gate: V DD If A or B equals to 1, then =0 A B This is the NOT (A OR B) function, i.e. NOR PARALLEL conduction path Complex conduction paths == option for complex logic gates Microelectronics BSc course, MOS inverters András Poppe, BME-EET
9 Complex logic gates Serial paths connected in parallel V DD Out = AB + C + ( D + E) F A D E C B F There are 4 paths Microelectronics BSc course, MOS inverters András Poppe, BME-EET
10 Inverter realizations V DD Switch = n channle MOSFET: normally OFF device V DD Load resistor: another transistor, e.g. in triode region V DD V GG load IN IN IN drive Needs another supply not OK Microelectronics BSc course, MOS inverters András Poppe, BME-EET
11 nmos technique very simple V DD Depl. mode tr.: V T shifted by ion implantation Simple process, outdated, many disadvantages static consumption if =0 if = 0, it will not be a pure level asymmetrical transfer characteristic (see later) IN I d ~ W/L In both cases the load resistor is replaced by a MOSFET but this transistor was not provided with an active control This is the passive load inverter Microelectronics BSc course, MOS inverters András Poppe, BME-EET
12 Complex gates (in nmos) Serial conduction paths in parallel, e.g.: There are 4 paths = AB + C + ( D + E) F Microelectronics BSc course, MOS inverters András Poppe, BME-EET
13 The CMOS technique The name comes from: Complementary MOS Idea: the load also should be provided with active control if the nmos driver (switching) trasistor conducts the load transistor must be an "open" circuit if the nmos driver (switching) trasistor is an "open circuit", the load must be conducting This needs such a normally OFF device which needs "opposite" control signals than the nmos transistors Such device is a pmos transistor Microelectronics BSc course, MOS inverters András Poppe, BME-EET
14 The CMOS inverter V DD pmos An n and a p type enhancement mode device Active load inverter: the two transitors have the same common control In steady state only one device is "on", the other is "off". IN nmos IN IN = Microelectronics BSc course, MOS inverters András Poppe, BME-EET
15 Characteristics of inverters, rudiments Transfer characteristic: output voltage vs. input voltage "1" U = out f ( U in ) Uout The output signal is the inverted version of the logic value of the input signal "0" Uin transfer characteristic of an ideal and a realistic inverter "1" Microelectronics BSc course, MOS inverters András Poppe, BME-EET
16 Xfer char. of a CMOS inverter V DD pmos IN nmos U IN =U GSn U =U DSn Microelectronics BSc course, MOS inverters András Poppe, BME-EET
17 Characteristics of inverters, rudiments Noise immunity: Same U out corresponds to a wide U in range There are 3 regions in the charactersitic On the L and H sides the characteristc is flat, i.e. any voltage change in the input has negligible effect on the output. "1" Uout L H "1" L and H regions "0" Uin transfer characteristic of an ideal and a realistic inverter Microelectronics BSc course, MOS inverters András Poppe, BME-EET
18 Characteristics of inverters, rudiments Signal regeneration depends on the slope of the middle region U 1 U 2 U U 1 is a "bad" logic 0 signal. Output U 2 of the first inverter is already close to an acceptable logic 1 level. output voltage U 3 at the second inverter is already a "good" logic 0 level. U 2 U out U 3 "1" Microelectronics BSc course, MOS inverters András Poppe, BME-EET "0" U 1 U 2 U in transfer characteristic of an ideal and a realistic inverter
19 Characteristics of inverters, rudiments Signal regeneration U 1 U 2 U U L =0V, U H =5V U [V] 6.0 U 1 U 2 U n 10.0n 20.0n 30.0n 40.0n (SPICE simulation) time [sec] In case of U 3 both the voltage level and the signal form are visibly regenerated! Microelectronics BSc course, MOS inverters András Poppe, BME-EET
20 Characteristics of inverters, rudiments Inverter logic threshold voltage The level, under which the signals will be converted into logical 0 and above which the signals will be converted by the inverter chain into logical 1 U k V dd U out Intersection of the U in =U out line and the x-fer characteristic V dd U in Microelectronics BSc course, MOS inverters András Poppe, BME-EET
21 Characteristics of inverters, rudiments Logic level ranges The voltage range of the logic 0 and 1 values within which the circuit works safely in the respective logic level V dd U Hm U k U out U Z Example: 74HC00, V dd =3V, U LM =0.9V U Hm =2.1V U LM V dd Important voltage values U LM, max. of logic 0 U Hm, min. op logic 1 U in Microelectronics BSc course, MOS inverters András Poppe, BME-EET
22 Characteristics of inverters, rudiments Propagation delay U U in U out U Hm U LH t pd t t pd is difficult to define, and may be different for switching on and off (e.g. nmos inverters) Microelectronics BSc course, MOS inverters András Poppe, BME-EET
23 Characteristics of inverters, rudiments Inverter pair delay n n A long chain of uniform inverters is assumed. After a certain number of inverters the signal form will be determined by the inverter properties only. After propagating throug 2 inverters the signal will be the same, the delay will be t pdp the inverter pair delay U U n U n+2 t pdp t Microelectronics BSc course, MOS inverters András Poppe, BME-EET
24 Characteristics of inverters, rudiments Measuring the inverter pair delay THE RING OSCILLATOR Odd number of inverters connected in a chain, no stable state oscillate T=n t pdp Microelectronics BSc course, MOS inverters András Poppe, BME-EET
25 Characteristics of inverters, rudiments Power-delay product (Pτ) low power and small delay refer to good quality, the product may be a figure of merit for the quality of a circuit family. the physical meaning: the minimal energy, needed to work on 1 bit of information Microelectronics BSc course, MOS inverters András Poppe, BME-EET
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