Shorthand Notation for NMOS and PMOS Transistors
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1 Shorthand Notation for NMOS and PMOS Transistors
2 Terminal Voltages Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V ds = V d V s = V gs - V gd Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation V s V gs V g + V ds + V gd - V d
3 In linear: nmos I-V o How much charge Q channel is in the channel o How much time t each carrier takes to cross In saturation: o If V gd < V t, channel pinches off near drain When V ds > V dsat = V gs V t o Drain voltage no longer increases current
4 nmos I-V Summary, 0 Vgs V V I V V ds V V V 2 V V 2 V V 2 ds gs t ds ds dsat gs t ds dsat t cutoff linear saturation
5 pmos I-V All doping and voltages are inverted for pmos Mobility m p is determined by holes Typically 2-3x lower than that of electrons m n Thus pmos must be wider to provide same current In this class, assume m n / m p = 2
6 CMOS Combinational Circuits Implementation of logic gates and other structures using CMOS technology. Basic element: transistor 2 types of transistors: n-channel (nmos) and p-channel (pmos) Type depends on the semiconductor materials used to implement the transistor. We want to model transistor behavior at the logic level in order to study the behavior of CMOS circuits view pmos and nmos transistors as swithes.
7 CMOS transistors as Switches 3 terminals in CMOS transistors: G: Gate D: Drain S: Source nmos transistor/switch X=1 switch closes (ON) X=0 switch opens (OFF) pmos transistor/switch X=1 switch opens (OFF) X=0 switch closes (ON)
8 Networks of Switches Use switches to create networks that represent CMOS logic circuits. To implement a function F, create a network s.t. there is a path through the network whenever F=1 and no path when F=0. Two basic structures: Transistors in Series Transistors in Parallel
9 Transistors in Series/Parallel nmos in Series a X X:X Y Y:Y a b b Path between points a and b exists if both X and Y are 1 X Y X nmos in Parallel a Y X:X b a b Y:Y Path between points a and b exists if either X or Y are 1 X+Y pmos in Series a X X:X Y Y:Y a b b Path between points a and b exists if both X and Y are 0 X Y X pmos in Parallel a Y X:X b a b Y:Y Path between points a and b exists if either X or Y are 0 X +Y
10 Networks of Switches (cont.) In general: 1. nmos in series is used to implement AND logic 2. pmos in series is used to implement NOR logic 3. nmos in parallel is used to implement OR logic 4. pmos in parallel is used to implement NAND logic Observe that: 1 is the complement of 3, and vice-versa 2 is the complement of 4, and vice-versa
11 CMOS Inverter +V X F = X X F = X Logic symbol GRD Transistor-level schematic Operation: X=1 nmos switch conducts (pmos is open) and draws from GRD F=0 X=0 pmos switch conducts (nmost is open) and draws from +V F=1
12 CMOS Inverter Technology Complementary MOS, or CMOS, needs both PMOS and NMOS devices for the logic gates to be realized The concept of CMOS was introduced in 1963 by Wanlass and Sah, but it did not become common until the 1980 s as NMOS microprocessors were dissipating as much as 50 W and alternative design technique was needed CMOS dominates digital IC design today
13 CMOS Inverter Technology The CMOS inverter consists of a PMOS device stacked on top on an NMOS device, but they need to be fabricated on the same wafer To accomplish this, the technique of n-well implantation is needed in this cross-section of a CMOS inverter WARNING: ensure you connect the source and drains of the transistors as shown since if you get them the wrong way around the transistors will conduct and burn out
14 CMOS Inverter (a) (b) (c) Circuit schematic for a CMOS inverter Simplified operation model with a high input applied Simplified operation model with a low input applied
15 CMOS Inverter Operation When v I is pulled high (to V DD ), the PMOS transistor is turned off, while the NMOS device is turned on pulling the output down to V SS When v I is pulled low (to V SS ), the NMOS transistor is turned off, while the PMOS device is turned on pulling the output up to V DD
16 Static Characteristics of the CMOS Inverter The figure shows the two static states of operation with the circuit and simplified models Notice that V H = 5V and V L = 0V, and that I D = 0A which means that there is no static power dissipation
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