HW#3 Solution. Dr. Parker. Fall 2015
|
|
- Barry Hines
- 6 years ago
- Views:
Transcription
1 HW#3 Solution Dr. Parker Fall 2015 Assume for the problems below that V dd = 1.8 V, V tp0 is -.7 V. and V tn0 is.7 V. V tpbodyeffect is -.9 V. and V tnbodyeffect is.9 V. Assume ß n (k n )= W/L µ A(microamps)/V 2 and ß p (k p )= 51 W/L µ A/V 2 lambda = 100nm 1. (10%) A PMOS transistor has Vs = 1.3 V, V d =.9 V. V g =.2 V. What region of operation is it in? Vgd= -.7; Vgd= Vg- Vd Vtpbodyeffect= -.9 V (there is body effect; the source is not tied to the highest potential) Vds=.9-1.3= -.4 V Vgs=.2-1.3= -1.1 V Is the transistor ON? Vgs Vtpbodyffect? ? True, so transistor is ON Vds > Vgs-Vtp? -.4 > -1.1 (-.9)? -.4 > -.2? False, transistor is in SATURATION region 2. (10 %) An NMOS transistor has Vs =.2 V. V d = 1.3 V. Is the transistor in the saturation region of operation when Vgs =1.3 V? Vds =Vd-Vs = =1.1 V There is body effect since the source of the transistor is not connected to the lowest potential. Vgs Vtnbodyffect? 1.3.9? True, transistor is ON Vds> Vgs Vtnbodyeffect? 1.1 > ? 1.1 >.4? The transistor is in SATURATION region
2 3. (5%) Show a cross section and identify the parasitic transistors that cause latch up. How does a twinwell technology prevent latchup? The twin-well technology separates the nmos and pmos transistors by using n-well and p-well while using Si material as the substrate. The two wells are separated so there is no current flow between, either by spacing or by very light doping at the well boundaries. 4. (5%) Assume the channel between drain and source of an NMOS transistor is formed so that the transistor is in linear region. If we continuously decrease slowly Vgs voltage while keeping Vds constant, what would happen to the electrons underneath the gate area? Would the transistor be at t=infinity in linear, saturation, or cut off region? The transistor is initially in linear region Vds< Vgs Vt, by decreasing Vgs, the transistor moves to saturation first, then to cut off. Electrons move away from the channel and eventually the transistor moves into cut off region. 5. (7%) Give us 2 design rules that prevent short circuits and 2 design rules that prevent open circuits. Short Circuit: In general, the distance between two materials is considered for the prevention of short circuits. For example, the separation between two n-well materials or the separation between two metal wires of the same type has a minimum distance to prevent short circuits. Open circuit: In general, the minimum width of any material is used to prevent open circuits. An example is the minimum width of a metal wire which is 3 lambda or the minimum width of a poly line which is 2 lambda. Another rule that may help to prevent open circuits is the extension of materials outside the contact cut so that layers can effectively be connected.
3 6. (10%) Identify on the graph the portion(s) affected by the term Vds/2. Why do we typically ignore this term? When can't this term be ignored? The red boxes identify the nonlinear portions of the curve in linear region. We typically ignore this term because we usually want to operate the transistor in linear region with a very small Vds voltage so that we have a linear relationship between current Idsn and voltage Vdsn. This term cannot be ignored when the magnitude of Vds is comparable to Vgs-Vt. 7. a) (5 %) A PMOS transistor is used as a pass transistor (switch). The input voltage is Vin = 0 V. The gate voltage Vg=.2 V. The voltage Vout = 1.4 V at time t = 0+. What is the final output voltage at t = infinity? The source is at the output and initially has a voltage of 1.4V. The gate voltage is fixed to.2v. Analysis at t=infinity We have bodyeffect at t=infinity because the source is not Vdd. the minimum voltage the transistor can send at the output is limited by the threshold of the transistor. Vout Vg+ Vtpbodyeffect for the transistor to be ON. Thus, the output voltage can go as low as Vg+ Vtpbodyeffect =.2+.9= 1.1 V. b) (3%) Does the PMOS transistor have body effect when t approaches infinity? Yes, there is body effect, the output source is different from Vdd.
4 c) (10%) Assume the transistor width is three times minimum size and the length is twice minimum size. Compute the drain current flow I DS at t = 0+ and at t=infinity. At t=0+, Vds= 0-1.4= -1.4 V Vgs=.2-1.4=-1.2 V Vtpbodyeffect= -.9 V (the source is lower than the highest potential) Vgs Vtpbodyeffect? If this condition is true, the transistor is ON ? The condition is true, so the transistor is ON. Vds > Vgs-Vtpbodyeffect? -1.4 > -1.2 (-.9)? -1.4 > -.3? False, so the transistor is in SATURATION region Idsp =.5*µp*Cox*W/L*(Vgs-Vtpbodyeffect)^2 =.5*(51x10^-6)((3*(3*lambda))/(2*(2*lambda))(-1.2- (-.9))^2 = ua (negative sign indicates the current flow direction) At t=infinity, Vs= Vout= (Vg+ Vtpbodyeffect )=.2+.9=-1.1 V Vds= 0-1.1V = -1.1 Vgs=.2-1.1= -.9 V Vtpbodyeffect= -.9 V Vgs Vtpbodyeffect? If this condition is true, the transistor is ON ? The condition is true, but Vgs is increasing so transistor eventually turns off. Analysis with Vgs=-.9 V: Vds > Vgs-Vtpbodyeffect? If the condition is true the transistor is in linear region -1.1 > -.9 (-.9)? -1.1 > 0? True, so the transistor is in LINEAR region Idsp = µp*cox*w/l*vds*(vgs-vtpbodyeffect Vds/2) Idsp= 0 A 8. a) (7 %) Identify the sources and drains in a transmission gate at t=0+ when Vin = 1.1 V and Vout =.3 V. Vgn = 1.4 V, and Vgp = 0 V.
5 b) (8 %) What regions are the two transistors in when t approaches infinity? Be sure to justify your answers. NMOS: We have body effect because the source terminal of the nmos is not at the lowest potential. First, let s investigate if the transistor is ON: Vgs= =.3 V Vgs Vtpbodyffect?.3.9? False, so the transistor is in cut-off PMOS: The pmos transistor is ON at t=infinity, the difference in potential between source and gate is sufficiently large to satisfy the condition Vgs Vtpbodyeffect. Vgs= -1.1 V Vds= 0 V Vds < Vgs-Vtpbodyeffect? If this condition is true, then the transistor is in saturation region. 0 < -1.1 (-.9)? False, the PMOS transistor is in LINEAR region 9. a) (10%) In the circuit below, what are the voltages at node A and Out at t=infinity? NMOS: source is connected to node A and drain is connected to node In. PMOS: source is connected to node Out and drain is connected to node A. Initially both transistors are active and in saturation and node VA receives current from both transistors. Since the size of transistors is unknown, we do not know the current flow across each transistor and so the voltage at node A at t=infinity is unknown. The voltage at the output is also unknown, since charge is being removed from the output capacitance (not an ideal voltage source). The voltage at node A can be different according to the assumption made. Charge is shared between capacitances at node A and Out. Different answers will be accepted!
6 b) (5%) If the input Vin cannot be transferred to the output, what would be the range of voltages that you could apply to the gate of the nmos and/or pmos transistors to transfer Vin. Assume you can use a negative power supply. Vgn should be greater than or equal to 1.9 for the NMOS to transfer a 1V to node A. Vgp should be less than or equal than.1 V to ensure that the output node can go down to 1V. Different answers will be accepted! 10. (5%) What is the effective channel resistance of a PMOS transistor of 1.2 microns width and minimum length? Assume Vgs=-1.7 V, Vds= -.5V, Vg=0. Let s first verify that the transistor is ON and in LINEAR region Vgs = -1.7 V Vgs = Vg Vs Vs = Vg Vgs = 1.7 V (we have body effect) Vgs Vtpbodyeffect? True, therefore the transistor is ON. Vds = -.5 V Vds> Vgs Vtpbodyeffect? -.5 > -1.7 (-.9)? -.5 > -.8? This is true, so the PMOS transistor is in LINEAR region. Rchp = 1/( ß p *W/L*(Vgs-Vtpbodyeffect)) Rchp = 1/(51X10^-6*((12*lambda)/(2*lambda))*(-1.7-(-.9)) Rchp = KΩ
HW#3 Solution. Dr. Parker. Fall 2014
HW#3 Solution Dr. Parker Fall 2014 Assume for the problems below that V dd = 1.8 V, V tp0 is -.7 V. and V tn0 is.7 V. V tpbodyeffect is -.9 V. and V tnbodyeffect is.9 V. lambda=100 nm. Assume ß n (k n
More informationHW#3 Solution. Dr. Parker. Spring 2014
HW#3 olution r. Parker pring 2014 Assume for the problems below that V dd = 1.8 V, V tp0 is -.7 V. and V tn0 is.7 V. V tpbodyeffect is -.9 V. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V
More informationDIGITAL VLSI LAB ASSIGNMENT 1
DIGITAL VLSI LAB ASSIGNMENT 1 Problem 1: NMOS and PMOS plots using Cadence. In this exercise, you are required to generate both NMOS and PMOS I-V device characteristics (I/P and O/P) using Cadence (Use
More informationSolution HW4 Dr. Parker EE477
Solution HW4 Dr. Parker EE477 Assume for the problems below that V dd = 1.8 v, V tp0 is -.7 v. and V tn0 is.7 V. V tpbodyeffect is -.9 v. and V tnbodyeffect is.9 V. Assume ß n (k n )= 219.4 W/L µ A(microamps)/V
More informationLearning Outcomes. Spiral 2-6. Current, Voltage, & Resistors DIODES
26.1 26.2 Learning Outcomes Spiral 26 Semiconductor Material MOS Theory I underst why a diode conducts current under forward bias but does not under reverse bias I underst the three modes of operation
More informationENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits
ENEE307 Lab 7 MOS Transistors 2: Small Signal Amplifiers and Digital Circuits In this lab, we will be looking at ac signals with MOSFET circuits and digital electronics. The experiments will be performed
More informationCMOS Transistor and Circuits. Jan 2015 CMOS Transistor 1
CMOS Transistor and Circuits Jan 2015 CMOS Transistor 1 Latchup in CMOS Circuits Jan 2015 CMOS Transistor 2 Parasitic bipolar transistors are formed by substrate and source / drain devices Latchup occurs
More informationSession 10: Solid State Physics MOSFET
Session 10: Solid State Physics MOSFET 1 Outline A B C D E F G H I J 2 MOSCap MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor: Al (metal) SiO2 (oxide) High k ~0.1 ~5 A SiO2 A n+ n+ p-type Si (bulk)
More informationMOS TRANSISTOR THEORY
MOS TRANSISTOR THEORY Introduction A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the
More informationLecture 4. MOS transistor theory
Lecture 4 MOS transistor theory 1.7 Introduction: A MOS transistor is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage
More information8. Combinational MOS Logic Circuits
8. Combinational MOS Introduction Combinational logic circuits, or gates, witch perform Boolean operations on multiple input variables and determine the output as Boolean functions of the inputs, are the
More informationBasic Fabrication Steps
Basic Fabrication Steps and Layout Somayyeh Koohi Department of Computer Engineering Adapted with modifications from lecture notes prepared by author Outline Fabrication steps Transistor structures Transistor
More informationLecture 16. Complementary metal oxide semiconductor (CMOS) CMOS 1-1
Lecture 16 Complementary metal oxide semiconductor (CMOS) CMOS 1-1 Outline Complementary metal oxide semiconductor (CMOS) Inverting circuit Properties Operating points Propagation delay Power dissipation
More informationproblem grade total
Fall 2005 6.012 Microelectronic Devices and Circuits Prof. J. A. del Alamo Name: Recitation: November 16, 2005 Quiz #2 problem grade 1 2 3 4 total General guidelines (please read carefully before starting):
More informationIntroduction to the Long Channel MOSFET. Dr. Lynn Fuller
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Introduction to the Long Channel MOSFET Dr. Lynn Fuller Webpage: http://people.rit.edu/lffeee Electrical and 82 Lomb Memorial Drive Rochester,
More informationDepletion-mode operation ( 공핍형 ): Using an input gate voltage to effectively decrease the channel size of an FET
Ch. 13 MOSFET Metal-Oxide-Semiconductor Field-Effect Transistor : I D D-mode E-mode V g The gate oxide is made of dielectric SiO 2 with e = 3.9 Depletion-mode operation ( 공핍형 ): Using an input gate voltage
More informationMOSFET Terminals. The voltage applied to the GATE terminal determines whether current can flow between the SOURCE & DRAIN terminals.
MOSFET Terminals The voltage applied to the GATE terminal determines whether current can flow between the SOURCE & DRAIN terminals. For an n-channel MOSFET, the SOURCE is biased at a lower potential (often
More informationELEC 2210 EXPERIMENT 12 NMOS Logic
ELEC 2210 EXPERIMENT 12 NMOS Logic Objectives: The experiments in this laboratory exercise will provide an introduction to NMOS logic. You will use the Bit Bucket breadboarding system to build and test
More information8. Characteristics of Field Effect Transistor (MOSFET)
1 8. Characteristics of Field Effect Transistor (MOSFET) 8.1. Objectives The purpose of this experiment is to measure input and output characteristics of n-channel and p- channel field effect transistors
More informationLecture 13. Biasing and Loading Single Stage FET Amplifiers. The Building Blocks of Analog Circuits - III
Lecture 3 Biasing and Loading Single Stage FET Amplifiers The Building Blocks of Analog Circuits III In this lecture you will learn: Current biasing of circuits Current sources and sinks for CS, CG, and
More informationEE 330 Laboratory 7 MOSFET Device Experimental Characterization and Basic Applications Spring 2017
EE 330 Laboratory 7 MOSFET Device Experimental Characterization and Basic Applications Spring 2017 Objective: The objective of this laboratory experiment is to become more familiar with the operation of
More information3.CMOS Inverter-homework
3.CMOS Inverter-homework 1. for a CMOS inverter, when the pmos and nmos are long-channel devices,or when the supply voltage is low, velocity does not occur, under these circumstances,vm(vin=vout)=? 2.
More informationENEE 307 Laboratory#2 (n-mosfet, p-mosfet, and a single n-mosfet amplifier in the common source configuration)
Revised 2/16/2007 ENEE 307 Laboratory#2 (n-mosfet, p-mosfet, and a single n-mosfet amplifier in the common source configuration) *NOTE: The text mentioned below refers to the Sedra/Smith, 5th edition.
More informationLecture 16: MOS Transistor models: Linear models, SPICE models. Context. In the last lecture, we discussed the MOS transistor, and
Lecture 16: MOS Transistor models: Linear models, SPICE models Context In the last lecture, we discussed the MOS transistor, and added a correction due to the changing depletion region, called the body
More informationStudy of Differential Amplifier using CMOS
Study of Differential Amplifier using CMOS Mr. Bhushan Bangadkar PG Scholar Mr. Amit Lamba Assistant Professor Mr. Vipin Bhure Assistant Professor Electronics and Communication Electronics and Communication
More informationMicroelectronics Circuit Analysis and Design. MOS Capacitor Under Bias: Electric Field and Charge. Basic Structure of MOS Capacitor 9/25/2013
Microelectronics Circuit Analysis and Design Donald A. Neamen Chapter 3 The Field Effect Transistor In this chapter, we will: Study and understand the operation and characteristics of the various types
More informationMicroelectronics, BSc course
Microelectronics, BSc course MOS circuits: CMOS circuits, construction http://www.eet.bme.hu/~poppe/miel/en/14-cmos.pptx http://www.eet.bme.hu The abstraction level of our study: SYSTEM + MODULE GATE CIRCUIT
More informationBuilding Blocks of Integrated-Circuit Amplifiers
Building Blocks of ntegrated-circuit Amplifiers 1 The Basic Gain Cell CS and CE Amplifiers with Current Source Loads Current-source- or active-loaded CS amplifier Rin A o R A o g r r o g r 0 m o m o Current-source-
More informationEE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits
EE311: Electrical Engineering Junior Lab, Fall 2006 Experiment 4: Basic MOSFET Characteristics and Analog Circuits Objective This experiment is designed for students to get familiar with the basic properties
More informationEECS 141: FALL 98 FINAL
University of California College of Engineering Department of Electrical Engineering and Computer Science J. M. Rabaey 511 Cory Hall TuTh9:30-11am ee141@eecs EECS 141: FALL 98 FINAL For all problems, you
More informationConduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor
Conduction Characteristics of MOS Transistors (for fixed Vds)! Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
More informationTopic 2. Basic MOS theory & SPICE simulation
Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris, Ch 2 & 5.1-5.3 Rabaey, Ch 3) URL: www.ee.ic.ac.uk/pcheung/
More informationConduction Characteristics of MOS Transistors (for fixed Vds) Topic 2. Basic MOS theory & SPICE simulation. MOS Transistor
Conduction Characteristics of MOS Transistors (for fixed Vds) Topic 2 Basic MOS theory & SPICE simulation Peter Cheung Department of Electrical & Electronic Engineering Imperial College London (Weste&Harris,
More informationEE 230 Lab Lab 9. Prior to Lab
MOS transistor characteristics This week we look at some MOS transistor characteristics and circuits. Most of the measurements will be done with our usual lab equipment, but we will also use the parameter
More informationECE520 VLSI Design. Lecture 5: Basic CMOS Inverter. Payman Zarkesh-Ha
ECE520 VLSI Design Lecture 5: Basic CMOS Inverter Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Wednesday 2:00-3:00PM or by appointment E-mail: pzarkesh@unm.edu Slide: 1 Review of Last Lecture
More informationd. Why do circuit designers like to use feedback when they make amplifiers? Give at least two reasons.
EECS105 Final 5/12/10 Name SID 1 /20 2 /30 3 /20 4 /20 5 /30 6 /40 7 /20 8 /20 Total 1. Give a short answer to each question a. Your friend from Stanford says that he has designed a three-stage high gain
More information! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)
ESE370: ircuit-level Modeling, Design, and Optimization for Digital Systems Today! PN Junction! MOS Transistor Topology! Threshold Lec 7: September 16, 2015 MOS Transistor Operating Regions Part 1! Operating
More information6.012 Microelectronic Devices and Circuits
Page 1 of 13 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Microelectronic Devices and Circuits Final Eam Closed Book: Formula sheet provided;
More informationELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC)
ELEC451 Integrated Circuit Engineering Fall 2009 Solution to CAD Assignment 2 Inverter Voltage Transfer Characteristic (VTC) The plot below shows how the inverter's threshold voltage changes with the relative
More informationECE315 / ECE515 Lecture 8 Date:
ECE35 / ECE55 Lecture 8 Date: 05.09.06 CS Amplifier with Constant Current Source Current Steering Circuits CS Stage Followed by CG Stage Cascode as Current Source Cascode as Amplifier ECE35 / ECE55 CS
More informationMetal Oxide Semiconductor Field-Effect Transistors (MOSFETs)
Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) Device Structure N-Channel MOSFET Providing electrons Pulling electrons (makes current flow) + + + Apply positive voltage to gate: Drives away
More informationExperiment 5 Single-Stage MOS Amplifiers
Experiment 5 Single-Stage MOS Amplifiers B. Cagdaser, H. Chong, R. Lu, and R. T. Howe UC Berkeley EE 105 Fall 2005 1 Objective This is the first lab dealing with the use of transistors in amplifiers. We
More informationMOSFET & IC Basics - GATE Problems (Part - I)
MOSFET & IC Basics - GATE Problems (Part - I) 1. Channel current is reduced on application of a more positive voltage to the GATE of the depletion mode n channel MOSFET. (True/False) [GATE 1994: 1 Mark]
More informationLab 3: Circuit Simulation with PSPICE
Page 1 of 11 Laboratory Goals Introduce text-based PSPICE as a design tool Create transistor circuits using PSPICE Simulate output response for the designed circuits Introduce the Curve Tracer functionality.
More informationLecture # 16 Logic with a State Dependent Device. Logic Gates How are they built in practice?
EECS 42 Introduction to Digital Electronics Andrew R. Neureuther These viewgraphs will be handed out in class 1/21/ Lecture # 16 Logic with a State Dependent Device S&O pp. 9-9, 4-6 (read for graphs and
More informationPower dissipation in CMOS
DC Current in For V IN < V TN, N O is cut off and I DD = 0. For V TN < V IN < V DD /2, N O is saturated. For V DD /2 < V IN < V DD +V TP, P O is saturated. For V IN > V DD + V TP, P O is cut off and I
More information4.1 Device Structure and Physical Operation
10/12/2004 4_1 Device Structure and Physical Operation blank.doc 1/2 4.1 Device Structure and Physical Operation Reading Assignment: pp. 235-248 Chapter 4 covers Field Effect Transistors ( ) Specifically,
More informationModeling MOS Transistors. Prof. MacDonald
Modeling MOS Transistors Prof. MacDonald 1 Modeling MOSFETs for simulation l Software is used simulate circuits for validation l Original program SPICE UC Berkeley Simulation Program with Integrated Circuit
More informationCourse Number Section. Electronics I ELEC 311 BB Examination Date Time # of pages. Final August 12, 2005 Three hours 3 Instructor
Course Number Section Electronics ELEC 311 BB Examination Date Time # of pages Final August 12, 2005 Three hours 3 nstructor Dr. R. Raut M aterials allowed: No Yes X (Please specify) Calculators allowed:
More informationLecture 4. The CMOS Inverter. DC Transfer Curve: Load line. DC Operation: Voltage Transfer Characteristic. Noise in Digital Integrated Circuits
Noise in Digital Integrated Circuits Lecture 4 The CMOS Inverter i(t) v(t) V DD Peter Cheung Department of Electrical & Electronic Engineering Imperial College London URL: www.ee.ic.ac.uk/pcheung/ E-mail:
More informationECE 2274 MOSFET Voltmeter. Richard Cooper
ECE 2274 MOSFET Voltmeter Richard Cooper Pre-Lab for MOSFET Voltmeter Voltmeter design: Build a MOSFET (2N7000) voltmeter in LTspice. The MOSFETs in the voltmeter act as switches. To turn on the MOSFET.
More informationLab 6: MOSFET AMPLIFIER
Lab 6: MOSFET AMPLIFIER NOTE: This is a "take home" lab. You are expected to do the lab on your own time (still working with your lab partner) and then submit your lab reports. Lab instructors will be
More informationCPE/EE 427, CPE 527 VLSI Design I CMOS Inverter. CMOS Inverter: A First Look
CPE/EE 427, CPE 527 VLSI Design I CMOS Inverter Department of Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic CMOS Inverter: A First Look C L 9/11/26 VLSI
More informationThe George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE 20 - LAB
The George Washington University School of Engineering and Applied Science Department of Electrical and Computer Engineering ECE 20 - LAB Experiment # 11 MOSFET Amplifiers testing and designing Equipment:
More informationUNIVERSITY OF NORTH CAROLINA AT CHARLOTTE Department of Electrical and Computer Engineering
UNIVERSITY OF NORTH CAROLINA AT CHARLOTTE Department of Electrical and Computer Engineering EXPERIMENT 8 MOSFET AMPLIFIER CONFIGURATIONS AND INPUT/OUTPUT IMPEDANCE OBJECTIVES The purpose of this experiment
More informationUNIT 3: FIELD EFFECT TRANSISTORS
FIELD EFFECT TRANSISTOR: UNIT 3: FIELD EFFECT TRANSISTORS The field effect transistor is a semiconductor device, which depends for its operation on the control of current by an electric field. There are
More information55:041 Electronic Circuits
55:041 Electronic Circuits Mosfet Review Sections of Chapter 3 &4 A. Kruger Mosfet Review, Page-1 Basic Structure of MOS Capacitor Sect. 3.1 Width 1 10-6 m or less Thickness 50 10-9 m or less ` MOS Metal-Oxide-Semiconductor
More information1. The simple, one transistor current source
1. The simple, one transistor current source The test schematic (srs-simpla-mos.asc): 1. Design the NMOS source for a 40µA output current and the minimum allowed output voltage V omin =50mV. The design
More informationBasic Circuits. Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair,
Basic Circuits Current Mirror, Gain stage, Source Follower, Cascode, Differential Pair, CCS - Basic Circuits P. Fischer, ZITI, Uni Heidelberg, Seite 1 Reminder: Effect of Transistor Sizes Very crude classification:
More informationElectronic CAD Practical work. Week 1: Introduction to transistor models. curve tracing of NMOS transfer characteristics
Electronic CAD Practical work Dr. Martin John Burbidge Lancashire UK Tel: +44 (0)1524 825064 Email: martin@mjb-rfelectronics-synthesis.com Martin Burbidge 2006 Week 1: Introduction to transistor models
More informationEE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu 511 Sutardja Dai Hall (SDH)
EE105 Fall 2015 Microelectronic Devices and Circuits: MOSFET Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 7-1 Simplest Model of MOSFET (from EE16B) 7-2 CMOS Inverter 7-3 CMOS NAND
More informationMEASUREMENT AND INSTRUMENTATION STUDY NOTES UNIT-I
MEASUREMENT AND INSTRUMENTATION STUDY NOTES The MOSFET The MOSFET Metal Oxide FET UNIT-I As well as the Junction Field Effect Transistor (JFET), there is another type of Field Effect Transistor available
More informationLaboratory #9 MOSFET Biasing and Current Mirror
Laboratory #9 MOSFET Biasing and Current Mirror. Objectives 1. Review the MOSFET characteristics and transfer function. 2. Understand the relationship between the bias, the input signal and the output
More informationTransistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced.
Unit 1 Basic MOS Technology Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell Labratories. In 1961, first IC was introduced. Levels of Integration:- i) SSI:-
More informationThis Week s Subject. DRAM & Flexible RRAM. p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor
DRAM & Flexible RRAM This Week s Subject p-channel MOSFET (PMOS) CMOS: Complementary Metal Oxide Semiconductor CMOS Logic Inverter NAND gate NOR gate CMOS Integration & Layout GaAs MESFET (JFET) 1 Flexible
More informationShort Channel Bandgap Voltage Reference
Short Channel Bandgap Voltage Reference EE-584 Final Report Authors: Thymour Legba Yugu Yang Chris Magruder Steve Dominick Table of Contents Table of Figures... 3 Abstract... 4 Introduction... 5 Theory
More informationHomework 2 Solutions. Perform.op analysis, the small-signal parameters of M1 and M2 are shown below.
Problem 1 Homework 2 Solutions 1) Circuit schematic Perform.op analysis, the small-signal parameters of M1 and M2 are shown below. Small-signal parameters of M1 gds = 9.723u gm = 234.5u region = 2 vds
More informationECE315 / ECE515 Lecture 9 Date:
Lecture 9 Date: 03.09.2015 Biasing in MOS Amplifier Circuits Biasing using Single Power Supply The general form of a single-supply MOSFET amplifier biasing circuit is: We typically attempt to satisfy three
More informationECE 546 Lecture 12 Integrated Circuits
ECE 546 Lecture 12 Integrated Circuits Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu ECE 546 Jose Schutt Aine 1 Integrated Circuits IC Requirements
More informationEE 42/100 Lecture 23: CMOS Transistors and Logic Gates. Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 23 p. 1/16 EE 42/100 Lecture 23: CMOS Transistors and Logic Gates ELECTRONICS Rev A 4/15/2012 (10:39 AM) Prof. Ali M. Niknejad University
More informationLecture 34: Designing amplifiers, biasing, frequency response. Context
Lecture 34: Designing amplifiers, biasing, frequency response Prof J. S. Smith Context We will figure out more of the design parameters for the amplifier we looked at in the last lecture, and then we will
More informationEEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families
EEC 118 Lecture #11: CMOS Design Guidelines Alternative Static Logic Families Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Homework 5 this week Lab
More informationWeek 9a OUTLINE. MOSFET I D vs. V GS characteristic Circuit models for the MOSFET. Reading. resistive switch model small-signal model
Week 9a OUTLINE MOSFET I vs. V GS characteristic Circuit models for the MOSFET resistive switch model small-signal model Reading Rabaey et al.: Chapter 3.3.2 Hambley: Chapter 12 (through 12.5); Section
More informationEE 501 Lab 1 Exploring Transistor Characteristics
Objectives: Tasks: EE 501 Lab 1 Exploring Transistor Characteristics Lab report due on Sep 8th, 2011 1. Make sure you have your cadence 6 work properly 2. Familiar with characteristics of MOSFET such as
More informationEE 2274 MOSFET BASICS
Pre Lab: Include your CN with prelab. EE 2274 MOSFET BASICS 1. Simulate in LTspice a family of output characteristic curves (cutve tracer) for the 2N7000 NMOS You will need to add the 2N7000 model to LTspice
More informationLecture Integrated circuits era
Lecture 1 1.1 Integrated circuits era Transistor was first invented by William.B.Shockley, Walter Brattain and John Bardeen of Bell laboratories. In 1961, first IC was introduced. Levels of Integration:-
More informationECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices
ECE 5745 Complex Digital ASIC Design Topic 2: CMOS Devices Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5950 Simple Transistor
More informationLecture 27: MOSFET Circuits at DC.
Whites, EE 30 Lecture 7 Page 1 of 8 Lecture 7: MOSFET Circuits at C. We will illustrate the C analysis of MOSFET circuits through a number of examples in this lecture. Example N7.1 (similar to text Example
More informationDesign of a High Speed Mixed Signal CMOS Mutliplying Circuit
Brigham Young University BYU ScholarsArchive All Theses and Dissertations 2004-03-12 Design of a High Speed Mixed Signal CMOS Mutliplying Circuit David Ray Bartholomew Brigham Young University - Provo
More informationSession 2 MOS Transistor for RF Circuits
Session 2 MOS Transistor for RF Circuits Session Speaker Chandramohan P. Session Contents MOS transistor basics MOS equivalent circuit Single stage amplifiers Opamp design Session objectives To understand
More informationMOS Inverters Dr. Lynn Fuller Webpage:
ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING MOS Inverters Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu
More informationHomework Assignment 07
Homework Assignment 07 Question 1 (Short Takes). 2 points each unless otherwise noted. 1. A single-pole op-amp has an open-loop low-frequency gain of A = 10 5 and an open loop, 3-dB frequency of 4 Hz.
More informationECE315 / ECE515 Lecture 5 Date:
Lecture 5 ate: 20.08.2015 MOSFET Small Signal Models, and Analysis Common Source Amplifier Introduction MOSFET Small Signal Model To determine the small-signal performance of a given MOSFET amplifier circuit,
More informationEECS 312: Digital Integrated Circuits Lab Project 2 Extracting Electrical and Physical Parameters from MOSFETs. Teacher: Robert Dick GSI: Shengshuo Lu
EECS 312: Digital Integrated Circuits Lab Project 2 Extracting Electrical and Physical Parameters from MOSFETs Teacher: Robert Dick GSI: Shengshuo Lu Due 3 October 1 Introduction In this lab project, we
More informationModule 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits
Module 4 : Propagation Delays in MOS Lecture 19 : Analyzing Delay for various Logic Circuits Objectives In this lecture you will learn the following Ratioed Logic Pass Transistor Logic Dynamic Logic Circuits
More informationCS/ECE 5710/6710. Composite Layout
CS/ECE 5710/6710 Introduction to Layout Inverter Layout Example Layout Design Rules Composite Layout Drawing the mask layers that will be used by the fabrication folks to make the devices Very different
More informationESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems. Today. MOSFET Ids vs. Vgs, Vds MOSFET. Preclass. MOSFET I vs.
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Day 2: September 7, 2012 Transistor Introduction Today MOSFET Capacitive and resistive loads Zero-th order transistor model
More informationECE4902 C2012 Lab 3. Qualitative MOSFET V-I Characteristic SPICE Parameter Extraction using MOSFET Current Mirror
ECE4902 C2012 Lab 3 Qualitative MOSFET VI Characteristic SPICE Parameter Extraction using MOSFET Current Mirror The purpose of this lab is for you to make both qualitative observations and quantitative
More informationToday's Goals. Finish MOS transistor Finish NMOS logic Start CMOS logic
Bi Today's Goals Finish MOS transistor Finish Start Bi MOS Capacitor Equations Threshold voltage Gate capacitance V T = ms Q i C i Q II C i Q d C i 2 F n-channel - - p-channel ± ± + + - - Contributions
More informationPart II: The MOS Transistor Technology. J. SÉE 2004/2005
Part II: The MOS Transistor Technology J. SÉE johann.see@ief.u-psud.fr 2004/2005 Lecture plan Towards the nanotechnologies... data storage The data processing through the ages MOS transistor in logic-gates
More informationIntroduction to MOSFET MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
Microelectronic Circuits Introduction to MOSFET MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Slide 1 MOSFET Construction MOSFET (Metal Oxide Semiconductor Field Effect Transistor) Slide 2
More informationIntegrated Circuit Amplifiers. Comparison of MOSFETs and BJTs
Integrated Circuit Amplifiers Comparison of MOSFETs and BJTs 17 Typical CMOS Device Parameters 0.8 µm 0.25 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS t ox (nm) 15 15 6 6 2.7 2.7 C ox (ff/µm 2 )
More informationWeek 7: Common-Collector Amplifier, MOS Field Effect Transistor
EE 2110A Electronic Circuits Week 7: Common-Collector Amplifier, MOS Field Effect Transistor ecture 07-1 Topics to coer Common-Collector Amplifier MOS Field Effect Transistor Physical Operation and I-V
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More informationChapter 6: Field-Effect Transistors
Chapter 6: Field-Effect Transistors Islamic University of Gaza Dr. Talal Skaik MOSFETs MOSFETs have characteristics similar to JFETs and additional characteristics that make then very useful. There are
More informationCMOS VLSI Design (A3425)
CMOS VLSI Design (A3425) Unit III Static Logic Gates Introduction A static logic gate is one that has a well defined output once the inputs are stabilized and the switching transients have decayed away.
More informationField Effect Transistors (FET s) University of Connecticut 136
Field Effect Transistors (FET s) University of Connecticut 136 Field Effect Transistors (FET s) FET s are classified three ways: by conduction type n-channel - conduction by electrons p-channel - conduction
More informationField-Effect Transistors
Field-Effect Transistors The field-effect transistor 1 is a semiconductor device which depends for its operation on the control of current by an electric field. There are two types of field-effect transistors,
More informationLaboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 20, 2014, at the beginning of your lab section
Laboratory 1 Single-Stage MOSFET Amplifier Analysis and Design Due Date: Week of February 20, 2014, at the beginning of your lab section Objective To analyze and design single-stage common source amplifiers.
More informationElectronic Circuits for Mechatronics ELCT 609 Lecture 6: MOS-FET Transistor
Electronic Circuits for Mechatronics ELCT 609 Lecture 6: MOS-FET Transistor Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Introduction Why we call it Transistor? The name came as an
More information