Deep Submicron Interconnect. 0.18um vs. 013um Interconnect

Transcription

1 Deep Submicron Interconnect R. Dept. of ECE University of British Columbia 0.18um vs. 013um Interconnect 0.18µm 5-layer Al Metal Process 0.13µm 8-layer Cu Metal Process 1

2 Interconnect Scaling Effects Dense multilayer metal increases coupling capacitance Old Assumption DSM Long/narrow line widths further increases resistance of interconnect Effect of Advanced Interconnect 2

3 Effect of Wire Scaling on Delay What happens to wire delay? Many people claim that wire delay goes up, as shown in the famous plot from the 1995 SIA roadmap But it depends on how you scale the wires and which wires you are talking about. In a technology shrink (s< 1) There are really two types of wires a. Wires that scale L directly by s, b. Wires of constant percentage of die size, the global wires of the increasing complex chips Delay is different for these two cases as shown here: Delay (ps) um Gate L=43um T=0.8um Total Interconnect Source: SIA Technology Roadmap Shrinking Process a b 0.13um Example of Wire Length Distribution L crit Short Wires Long wires Source: M. Horowitz et. al. 3

4 FO4 vs. Wire Delay Delay (ps) mm mm FO4 1mm Technology (nm) Buffer Insertion for Long Wires Make Long wires into short wires by inserting buffers periodically. Divide interconnect into N sections as follows: 2W M R w M R R w M w M R w W C w /2 C w /2 C w /2 C w /2 R eff = R eqn /M C self =C j 3W*M C fanout = C g 3W*M R w = R int L/N C w = C int L/N Then delay through buffers and interconnect is given by: t p = N *[R eff (C self + C W /2) + (R eff + R W )(C W /2+C fanout )] What is the optimal number of buffers? Find N such that t P / N = 0 N sqrt(0.4r int C int L 2 /t pbuf ) where t pbuf = R eff (C self + C fanout ) What size should the buffers be? Find M such that t P / M = 0 M = sqrt((r eqn /C g 3W)(C int /R int )) 4

5 Technology Scaling Effects At 0.5um and above: Simple capacitance At 0.35um and below: Resistance Iavg v t... At 0.18um and below : Coupling Capacitance At 0.10um and below: Inductance R L C Coupling Between Lines in DSM Layout Over 80% of interconnections in a UDSM chip are parallel crossing lines with 3D effects 5

6 Interconnect Capacitance Profiles Total capacitance can be decomposed into three components: Area capacitance Lateral capacitance Fringe capacitance Horizontal spacing between conductors S W H Vertical spa ci ng bet ween conduct or s T Heightabove Substrate H C total = C area + C lateral + C fringe Wire Dimensions T=wire thickness, H=vertical wire separation, S=horizontal wire separation, W=wire width, L=wire length Metal 2 L2 T2 H2 T1 H1 S1 W1 S1 W1 Metal 1 Ground Plane T and H are fixed parameters based on the fabrication process W, S and L are under the designer s control 6

7 Computation of Area Capacitances Metal 2 Metal 1 H W C a C a Area capacitance per unit length can be simply calculated using: C a = ε ox W = 0.035fF/um (W/H) t ox Computation of Lateral Capacitances Metal 2 Metal 1 Closely spaced wires T S C L C L Lateral capacitance per unit length for closely spaced wires can be calculated using: C L = ε ox T = 0.035fF/um (T/S) t ox For widely spaced wires, C L drops off as 1/S 7

8 Computation of Fringe Capacitances Metal 2 Widely separated wires H C a Metal 1 C f T C f C a Fringing capacitance per unit length for widely spaced wires can be approximated to be (actually depends on H and T which are fixed): C f 0.05fF/um Computation of Total Capacitances Metal 2 C f C a C f Metal 1 T C L C L C a For closely spaced wires, assume fringe is small C total = 2C a + 2C L = 0.2fF/um For widely spaced wires, assume lateral is small For medium spaced wires, C f and C L will both exist and vary with S C total = 2C a + 2C f = 0.2fF/um 8

9 Coupling Effects New model of interconnect A B C D Each driver connected to A,B,C or D can act as aggressor Agressor V DD C C Rup C C Victim Rdn C C g g Coupling capacitance could inject noise or affect delay First-Order Delay Analysis If aggressor is not switching ( ) C = C + C Q = C + C V load C g C g S If aggressor switches in same direction. Rup Rdn C C C g Cload = Cg Q = Cg VS Rdn C g If aggressor switches in opposite direction: Miller factor ( ) C = 2C + C Q = 2C + C V load C g C g S V Rup DD Multiplying factor ranges from 0 to 2 (Actual range is 1 to 3) Rdn C C C g 9

10 Signal Integrity Effect on Timing Net delay due to a single coupled aggressor net Net delay due to multiple coupled aggressor nets Victim net without coupling Victim net without coupling Victim net with coupling delay Victim net with coupling delay Aggressor net Aggressor nets Performance impact: 300 picosecond delay (3% of a clock cycle) Performance impact: over 2 nanosecond delay (20+% of a clock cycle) First-order Noise Analysis Assume that aggressor and driver resistances are negligible V 1 C c (V 1 -V 2 ) = C g V 2 C c C g V 2 V 2 = C c V 1 C c + C g V 2 = C c V 1 C c + C g If V 1 changes by V DD, what change V do we expect to see at the internal node in the worst case? V 2 = C c V dd C c + C g Looks like the feedthrough equation Produces results that are somewhat pessimistic 10

11 2nd-order Noise Analysis How much noise is actually injected into the victim aggressor line by a voltage transition on the aggressor line? C g C C Treat RC problem as a resistive divider: Vdd C g victim V O = Z dn V DD Z dn + Z up V DD Rup C C Z dn Z dn + Z up = R dn 1 + sc g R dn R dn 1 + sc g R dn + (R up + 1/sC c ) Rdn C g = sc c s 2 R up C c C g + s(c c + C c R up /R dn + C g ) + 1/R dn Capacitive Coupling What is the maximum value of spike? Depends on values of R,C Worst case would be large C c, small C g, small Rup, large Rdn Look at some limits: V peak < Vdd*Rdn/(Rdn+Rup) (set Cc infinite, Cg=0) V peak < Vdd*Cc/(Cc+Cg) (set Rup=0, Rdn infinite) V DD Rup C C Voltage spike response depends on RC ratios Rdn C g going up, time constant is R up C c going down, time constant is R dn (C g + C c ) Rdn*(Cg+Cc) < RupCc Amplitude based on resistor ratio Rdn*(Cg+Cc) > RupCc Amplitude based oncapacitance ratio 11

12 Signal Integrity Issues at FF s What happens if a glitch occurs in a clock signal? Positive-Edge Triggered Flip-Flop DQ Clk Clk Flip-flop captures and propagates incorrect data Could view any signal that, if glitched, could cause a logic upset as a clock signal Need to space out clocks/signals or shield them Signal Integrity Issues at FF s What happens if a glitch occurs in data signal? Positive-Edge Triggered Flip-Flop DQ Clk Clk Flip-flop captures and propagates incorrect data Need to insure that data signal is stable during FF setup time Shielding with stable signals or spacing is needed 12

13 Reducing Coupling Capacitance Space out the signals as much as possible, but it cost area. A B A B (a) higher coupling cap./less area (b) lower coup. cap./ more area Use Vdd and Gnd to shield wires wherever required A B A Vdd B Gnd (a) higher coupling cap./less area (b) higher tot. cap./ more area Reducing Coupling Capacitance Copper and low-k dielectrics Dual Damascene process metal and vias fabricated together try to reduce k from 3.9 to 2 Cu lower coupling caps better electromigration reliability ε1 Low-k Dielectrics ε2 ε2 ε2 ε1 TiN, TaN, or WN Barrier copper cladding silicon Multiple Levels of Metal M5 via5 M4 via4 M3 via3 M2 via2 M1 cont 13

14 Inductance Complete interconnect model should include inductance + V - V=Ldi i dt R L C With increasing frequency and a decrease in resistance due to wide wires and the use of copper, inductance will begin to influence clocks/busses: Z = R + jωl Inductance, by definition, is for a loop not a wire inductance of a wire in an IC requires knowledge of return path(s) inductance extraction for a whole chip is virtually impossible... Lumped RLC line Inductance Effects V in V O R L C V O = Z o Z t V in Treat RC problem as a resistive divider: 1 sc Z o Z t = 1 sc g + (R + sl) ω n = 1/sqrt(LC) ζ=rc/2sqrt(lc) = damping factor = 1 s 2 LC + src + 1 = ω n 2 s 2 + s2ζω n + ω n 2 Poles are P 1,2 = ω n [ ζ + - sqrt(ζ 2 1)] ζ > 1 we have two real poles (RC effects) ζ < 1 we have two complex poles (RLC effects) 14

15 Impact of on-chip self-inductance R S >> jωl Driver Model + wire Most gates behave this way (RC) R S < jωl Clocks behave this way (RLC): overshoot/ringing sharp edges reflections Other Inductance Effects For most gates R on is in the order of KΩ so typically R >> jωl response is dominant by RC delay for most signals Only the large drivers have a small enough R on to allow the inductance to control the dynamic response clocks busses For clocks, self-inductance term can dominate the response (especially if shielding is used) For busses, mutual inductance term dominates and creates noise events that could cause malfunction For power supplies, inductance can also be a problem due to the Ldi/dt drop (in addition to the IR drop) as supplies scale down 15

16 Capacitive and Inductive Noise R L C For most wires, jωl < (Rwire+Rdrive) for the frequency and R of interest. So, for delay, L is not a big issue currently. But ωl can be 20-30% of R so noise may be seen on adjacent line (mutual coupling) Dangerous scenario is a combination of localized capacitive coupling noise and long range mutual inductive coupling noise + - R L C - + R L C R L C R L C Return path current R L C Double noise events Antenna Effects As each metal layer is placed on the chip during fabrication, charge builds up on the metal layers due to CMP 1, etc. If too much charge accumulates on gate of MOS transistor, it could damage the oxide and short the gate to the bulk terminal Poly Metal This transistor could be damaged Metal 2 Antenna Ratio = Area wire Area gate Higher levels of metal accumulate more charge so they are more troublesome (i.e., metal 5 is worse than metal 1) Need to discharge metal lines during processing sequence to avoid transistor damage (becomes a design/layout issue) 1. CMP is chemical mechanical polishing which is used to planarize each layer before the next layer is placed on the wafer. 16

17 Preventing Antenna Effects A number of different approaches for antenna repairs: Diode Insertion - Make sure all metal lines are connected to diffusion somewhere to discharge the metal lines during fabrication n+ p diodes costs area - need to optimize number and location - causes problems for design verification tool Antenna diode Preventing Antenna Effects Note that there are always diodes connecting to source/drain regions of all transistors and charge on each layer is drained before next layer is added so why are we worried? Should put antenna diode here. Keep area of upper layer metals small near next transistor Gate input of next device may not be connected to a diode until it s too late charge accumulation on metal exceeds threshold 17

18 Preventing Antenna Effects Second approach is to add buffers to interconnect to break up long wire routes and provide more gate area for antenna ratio Third approach is to use metal jumpers to from one layer of metal to another Metal 1/polish vias (charge removed) Metal2/polish