1. Introduction. Institute of Microelectronic Systems. Status of Microelectronics Technology. (nm) Core voltage (V) Gate oxide thickness t OX

Transcription

1 Threshold voltage Vt (V) and power supply (V) 1. Introduction Status of s Technology V dd V t t OX Gate oxide thickness t OX (nm) Future VLSI chip CMOS feature size 0.1 µm Core voltage (V) V Chip size 520 mm mm 2 Transistors/cm 2 40 M 100 M DRAM bits /chip 17.2 G 0.05 µm V 275 G Number of wiring levels (Source: International Technology Roadmap for Semiconductors 1998 update) MOSFET channel length (µm) 2

2 ASIC Outlook 1997: Semiconductor and Electronic Equipment Sales Trends ( ) 3 Interconnect Technology Requirements: Inductive effects will become increasingly important Additional metal patterns or ground planes for inductive shielding Thinner metallization Lower line-to-line capacitance Increasing pitch and thickness at each conductor level to alleviate the impact of interconnect delay Global Intermediate Local Source: SIA Roadmap 1999 Passivation Dielectric Etch stop layer Dielectric diffusion barrier Copper conductor with metal barrier liner Pre-metal dielectric Tungsten contact plug 4

3 Productivity Gap: Technology vs. CAD 5 Productivity Gap: Technology vs. CAD Need to increase Designers Productivity in order to make use of new Technologies SIA Roadmap for the Design Technology Requirements (near term) 6

4 Productivity Gap: Beyond 2008 SIA Roadmap for the Design Technology Requirements (far term) 7 EDA: High-Level Design architecture structural of first_tap is signal x_q,red : std_logic_vector(bitwidth-1 downto 0); signal mult : std_logic_vector(2*bitwidth-1 downto 0); begin delay_register: process(reset,clk) begin if reset='1' then x_q <= (others => '0'); elsif (clk'event and clk='1') then x_q <= x_in; end if; end process; mult <= signed(coef)*signed(x_q); VHDL-Description RTL-Synthesis (Synopsys) Gate-Level Netlist Production Placement & Routing (Cadence/Mentor) ASIC Layout 8

5 Challenge: System-on-a-Chip Design? System on a Chip Design Complexity Gates RTL Synthesis Reuse, IP Cores Polygons Transistors Masks Place & Route Design Productivity Chasing the design gap 9 Traditional ASIC market ASICs are customer specific Ics If application-specific processor: ASIP The product is made only once an application is found Non-standard IC ASIC (customer specific) Semicustom Custom One or more customised layers All layers customised ASIP (application specific) Programmable Circuit with fuse, antifuse or memory that can be programmed 10

6 SoC: Silicon Components Categories Silicon components Integrated circuits Discrete devices and and optoelectronics Analogand and Mixed signal Logic Logic Logic Logic Gate Gate arrays Cell Cell based FPLDs SoC Other Memory DRAMs SRAMs Flash Other Microcomponets Microcomponents Microprocessors Microcontrolers Microcontrollers Microperipherals Modern SoCs can integrate different components 11 Market for -on-a-chip Source: Hugo De Man EIS 99, Darmstadt Services Broadband Network Area Examples: Multimedia Mobile Communication Automotive... WWW SoC Java Configurable Multi-Standard Info Plug... -> Domain Specific Computing 100Mb/sWLAN RF LAN 20Gop/s <1 Watt MPEG Gop/s 5 Gtr/s 10 Watt?? 12

7 Application: Single-Chip Integrated CMOS Radio Berkeley Wireless Centre Conventional cellular Phone Solution Research into Technology and Design Methodologies for CMOS single Chip Radios Exploring future Applications of wireless Technology, 4th Generation and beyond 13 Application Example: Transceiver Design Receiver Oscillator Low Noise Amplifier Filter Mixer Demodulator AD/DA Converter Digital Baseband Memory CMOS Logic AD/DA Converter Transmitter Oscillator Power Amplifier Filter Mixer Modulator 14