Digital Integrated Circuits Lecture 20: Package, Power, Clock, and I/O

Transcription

1 Digital Integrated Circuits Lecture 20: Package, Power, Clock, and I/O Chih-Wei Liu VLSI Signal Processing LAB National Chiao Tung University DIC-Lec20 1

2 Outline Packaging Power Distribution Clock Distribution I/O DIC-Lec20 2

3 Packages Package functions Electrical connection of signals and power from chip to board Little delay or distortion Mechanical connection of chip to board Removes heat produced on chip Protects chip from mechanical damage Compatible with thermal expansion Inexpensive to manufacture and test DIC-Lec20 3

4 Package Types Through-hole vs. surface mount DIC-Lec20 4

5 Multichip Modules Pentium Pro MCM Fast connection of CPU to cache Expensive, requires known good dice DIC-Lec20 5

6 Chip-to-Package Bonding Traditionally, chip is surrounded by pad frame Metal pads on μm pitch Gold bond wires attach pads to package Lead frame distributes signals in package Metal heat spreader helps with cooling DIC-Lec20 6

7 Advanced Packages Bond wires contribute parasitic inductance Fancy packages have many signal, power layers Like tiny printed circuit boards Flip-chip places connections across surface of die rather than around periphery Top level metal pads covered with solder balls Chip flips upside down Carefully aligned to package (done blind!) Heated to melt balls Also called C4 (Controlled Collapse Chip Connection) DIC-Lec20 7

8 Package Parasitics Use many V DD, GND in parallel Inductance, I DD Package Signal Pins Signal Pads Chip Chip V DD Chip GND Bond Wire Lead Frame Package Capacitor Board V DD Board GND DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 8

9 Heat Dissipation 60 W light bulb has surface area of 120 cm 2 Itanium 2 die dissipates 130 W over 4 cm 2 Chips have enormous power densities Cooling is a serious challenge Package spreads heat to larger surface area Heat sinks may increase surface area further Fans increase airflow rate over surface area Liquid cooling used in extreme cases ($$$) DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 9

10 Thermal Resistance ΔT = θ ja P ΔT: temperature rise on chip θ ja : thermal resistance of chip junction to ambient P: power dissipation on chip Thermal resistances combine like resistors Series and parallel θ ja = θ jp + θ pa Series combination DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 10

11 Example Your chip has a heat sink with a thermal resistance to the package of 4.0 C/W. The resistance from chip to package is 1 C/W. The system box ambient temperature may reach 55 C. The chip temperature must not exceed 100 C. What is the maximum chip power dissipation? ( C) / (4 + 1 C/W) = 9 W DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 11

12 Power Distribution Power Distribution Network functions Carry current from pads to transistors on chip Maintain stable voltage with low noise Provide average and peak power demands Provide current return paths for signals Avoid electromigration & self-heating wearout Consume little chip area and wire Easy to lay out DIC-Lec20 12

13 Power Requirements V DD = V DDnominal V droop Want V droop < +/- 10% of V DD Sources of V droop IR drops L di/dt noise I DD changes on many time scales Power Max clock gating Average Min Time DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 13

14 Power System Model Power comes from regulator on system board Board and package add parasitic R and L Bypass capacitors help stabilize supply voltage But capacitors also have parasitic R and L Simulate system for time and frequency responses Voltage Regulator Printed Circuit Board Planes Package and Pins Solder Bumps Chip V DD Bulk Capacitor Ceramic Capacitor Package Capacitor On-Chip Capacitor On-Chip Current Demand Board Package DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 14

15 Bypass Capacitors Need low supply impedance at all frequencies Ideal capacitors have impedance decreasing with ω Real capacitors have parasitic R and L Leads to resonant frequency of capacitor Ω 1 μf 0.25 nh impedance frequency (Hz) DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 15

16 Frequency Response Use multiple capacitors in parallel Large capacitor near regulator has low impedance at low frequencies But also has a low self-resonant frequency Small capacitors near chip and on chip have low impedance at high frequencies Choose caps to get low impedance at all frequencies impedance frequency (Hz) DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 16

17 Clock Distribution On a small chip, the clock distribution network is just a wire And possibly an inverter for clkb On practical chips, the RC delay of the wire resistance and gate load is very long Variations in this delay cause clock to get to different elements at different times This is called clock skew Most chips use repeaters to buffer the clock and equalize the delay Reduces but doesn t eliminate skew DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 17

18 Example Skew comes from differences in gate and wire delay With right buffer sizing, clk 1 and clk 2 could ideally arrive at the same time. But power supply noise changes buffer delays clk 2 and clk 3 will always see RC skew 3 mm gclk 3.1 mm 0.5 mm clk pf clk 2 clk pf 0.4 pf DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 18

19 Review: Skew Impact Ideally full cycle is available for work Skew adds sequencing overhead Increases hold time too F1 clk Q1 D2 clk clk Q1 t pcq Combinational Logic T c t pdq D2 t setup clk F2 t skew ( setup skew ) tpd Tc tpcq + t + t sequencing overhead F1 D2 Q1 clk F2 CL t t t + t cd hold ccq skew clk t skew t hold Q1 t ccq D2 t cd DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 19

20 Cycle Time Trends Much of CPU performance comes from higher f f is improving faster than simple process shrinks Sequencing overhead is bigger part of cycle 10 SpecInt Pentium Pentium II / III MHz Pentium Pentium II / III Fanout-of-4 (FO4) Inverter Delay (ps) VDD = VDD = 3.3 VDD = FO4 inverter delays / cycle Pentium Pentium II / III Process DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 20

21 Solutions Reduce clock skew Careful clock distribution network design Plenty of metal wiring resources Analyze clock skew Only budget actual, not worst case skews Local vs. global skew budgets Tolerate clock skew Choose circuit structures insensitive to skew DIC-Lec20 21

22 Clock Dist. Networks Ad hoc Grids H-tree Hybrid DIC-Lec20 22

23 Clock Grids Use grid on two or more levels to carry clock Make wires wide to reduce RC delay Ensures low skew between nearby points But possibly large skew across die DIC-Lec20 23

24 Alpha Clock Grids Alpha Alpha Alpha PLL gclk grid gclk grid Alpha Alpha Alpha DIC-Lec20 24

25 H-Trees Fractal structure Gets clock arbitrarily close to any point Matched delay along all paths Delay variations cause skew A and B might see big skew A B DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 25

26 Itanium 2 H-Tree Four levels of buffering: Primary driver Repeater Second-level clock buffer Gater Route around obstructions Repeaters Typical SLCB Locations Primary Buffer DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 26

27 Hybrid Networks Use H-tree to distribute clock to many points Tie these points together with a grid Ex: IBM Power4, PowerPC H-tree drives sector buffers Buffers drive total of 1024 points All points shorted together with grid DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 27

28 Input / Output Input/Output System functions Communicate between chip and external world Drive large capacitance off chip Operate at compatible voltage levels Provide adequate bandwidth Limit slew rates to control di/dt noise Protect chip against electrostatic discharge Use small number of pins (low cost) DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 28

29 I/O Pad Design Pad types V DD / GND Output Input Bidirectional Analog DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 29

30 Output Pads Drive large off-chip loads (2 50 pf) With suitable rise/fall times Requires chain of successively larger buffers Guard rings to protect against latchup Noise below GND injects charge into substrate Large nmos output transistor p+ inner guard ring n+ outer guard ring In n-well DIC-Lec20 30

31 Input Pads Level conversion Higher or lower off-chip V May need thick oxide gates A V DDH V DDL V Y A Y DDL weak Noise filtering Schmitt trigger A weak Y Y Hysteresis changes V IH, V IL A Protection against electrostatic discharge DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 31

32 ESD Protection Static electricity builds up on your body Shock delivered to a chip can fry thin gates Must dissipate this energy in protection circuits before it reaches the gates Diode clamps ESD protection circuits R PAD Current limiting resistor Current Thin limiting gate resistor oxides Diode clamps ESD testing 1500 Ω Human body model 100 pf Views human as charged capacitor Device Under Test DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 32

33 Bidirectional Pads Combine input and output pad Need tristate driver on output Use enable signal to set direction Optimized tristate avoids huge series transistors PAD En Dout Din NAND Dout En Y Dout NOR DIC-Lec20 cwliu@twins.ee.nctu.edu.tw 33

34 Analog Pads Pass analog voltages directly in or out of chip No buffering Protection circuits must not distort voltages DIC-Lec20 34

35 MOSIS I/O Pad 1.6 μm two-metal process Protection resistors Protection diodes Guard rings Field oxide clamps PAD 600/3 En Out Out Ω 185 Ω In In_unbuffered In_b DIC-Lec20 35