Signal Integrity Design of TSV-Based 3D IC

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1 Signal Integrity Design of TSV-Based 3D IC October 24, 21 Joungho Kim at KAIST 1

2 Contents 1) Driving Forces of TSV based 3D IC 2) Signal Integrity Issues 3) Noise Coupling Issues 4) Noise Isolation Methods 5) Conclusion 2

3 TSV Based 3D IC Chip ADC, DAC Memory RF Memory Silicon Interposer ADC, GPUDAC ADC, Analog DAC Inductor n+ n+ NMOS Cap p+ p+ n-well Memory Package ground power PCB ground 3

4 Major Advantages of TSV-based 3D IC - Large interconnection density - Small for factor - High performance: high-bandwidth, high I/O counts - Low power - Potentially low cost 4

5 Key Technology for 3D IC: TSV (Through Silicon Via) 3 rd Chip (Thinned Substrate) Under fill Dielectric Short Interconnection Length Reduced Delays Low Impedance for PDN Low Power Consumption Heat Dissipation Through Via 2 nd Chip (Thinned Substrate) 1 st Chip Dielectric Under fill Multi-level On-chip Interconnect SiO2 Less Space for Interconnection High Density Chip Wiring Large Number of I/O Small Area Package Si-Substrate 3D TSV Stacked IC 5

6 High-frequency Channel Loss in TSV S21(magnitude) [db].1µm Frequency [GHz] Si SiO 2 Ta Cu 6

7 Frequency-dependent Loss of Through Silicon Via Frequency dependent term -1 C insulator G Si sub Leakage current Cu SiO 2 Si Insertion loss (db) Capacitive region Resistive region Loss term Frequency (GHz) 7

8 TSV Channel Loss with Various Insulator Thickness of TSV Signal Top Ground Top C Insulator =1.6 pf C Insulator /2 C Insulator /2 -.5 C Insulator =2.6 pf S21 magnitude (db) C Insulator =7.8 pf Insulator thickness of TSV Signal Bottom C Insulator /2 C Insulator /2 Leakage current Ground Bottom -3 [A ] Frequency (GHz) 2 ( t =.5um ) ( t =.3um ) ( t =.1um ) 8

9 The Proposed TSV Equalizer using an Ohmic Contact Ohmic contact (Al/n+ type) Signal TSV Ground TSV n+ high doped Silicon n-type Silicon Substrate Bump Bump 9

10 TSV Equalizer Performance Insertion loss (db) Insertion loss of 8 TSVs without TSV equalizer -3.8 db 1 db -4.8 db.7db -8 Insertion loss of 8 TSVs with TSV equalizer Frequency(GHz) 2 1

11 Eye opening by the TSV Equalizer Pk-pk jitter : 16 ps Voltage (V) Eye opening: Voltage (V) 1 mv Time (ps) Time (ps) 11

12 High speed channel loss by TSV - High frequency loss - Non uniform loss - Loss increases as higher die stack and TSV numbers - Passive and active equalization methods needed 12

13 Noise Coupling Paths in Stacked Dies using TSV P-Substrate 3 rd Chip Inductor TSV TSV TSV TSV N+ P+ P+ N+ N+ P+ N-Well 2 N+ P+ N-Well P-Substrate N+ N+ 3 P+ N+ Metal N-Well to Metal Coupling 2 nd Chip TSV to Active Circuit Coupling Inductor 1 TSV TSV TSV to TSV Coupling N+ P+ P+ N+ N+ P+ N-Well N+ P+ N-Well N+ N+ P+ N+ N-Well P-Substrate 1 st Chip 13

14 Coupling between TSVs Cm Co x R L Cp 1 Csi Gsi M Gsi Csi + C parasitics -4 Cox -5 Measurement Model Freq [GHz]

15 Noise Coupling from TSV to Active Circuits conta ct C sub silicon substrate R sub C TSV TSV ILD/IM D Distance between contact and TSV : 1 μm Substrate height : 1 μm TSV diameter : 3 μm TSV SiO 2 thickness :.5 μm Coupling coefficient [db] A B C TSV SiO2 capacitance dominant Silicon resistance dominant Silicon capacitance dominant -6 1M 1M 1G 1G Frequency [GHz] 15

16 Shielding Methods for TSV Coupling 16

17 Shielding Effect Measurement: Guard Ring w/o guard ring w/ guard ring Freq [GHz]

18 Shielding Methods for TSV Coupling 18

19 Crosstalk between TSV - High frequency coupling - Dependent on TVS designs: dimensions and materials - Proper shielding methods are needed - Shielding structures can be significant overhead of chip area - Special I/O scheme may be needed to compensate or to avoid the crosstalk effects 19

20 Vertical Noise Coupling Issues in Mixed-Signal 3D-IC Transmitter Receiver Si Clock Only Tree tens µm Interconnection distance : Tight near-field Inductor coupling and Interconnection conductive coupling Substrate TSV N+ P+ Guard ring ~tens µm RF /Analog Chip Substrate Noise coupling through silicon substrate in 2D SoC N+ P+ N-Well Digital Logic Digital Block Logic Chip Substrate ~hundreds µm RF/Analog Block Substrate 2

21 3D IC for 2.4GHz VCO in Zigbee module V D Port #2 D Port #3 Port #2 Port #3 V DD Differential On-Chip Inductor Model L(1nH) L (1nH) Vertical Coupling Path Model + - V control V out + V out - On-Chip Clock Tree Model Clock Tree Port #1 V bias 3 turn Differential On-Chip Inductor Noise Source at Port #1 : DDR 3 Clock Rising/Falling Time (T r /T f ) Operation Frequency(1/T D ) 35ps 8MHz (1.25ns) V peak 1.5V Spur. & Phase noise at VCO output 21

22 Impact of Vertical Coupling on VCO Output Spur. DDR3 Clock spectrum (Aggressor at Bottom Voltage Chip) Transfer Ratio 2 Clock Spectrum [dbv] 2.4 GHz G 1G 1G 2G Frequency(Hz) -1 Voltage Transfer Ratio [db] VCO Output Spectrum [dbm] Target Spur. Mask for Zigbee Intermodulated with VCO output 2.4 GHz VCO Output Spectrum (without vertical coupling) VCO Output Spectrum (with vertical coupling) Vertical coupling causes Spur. Mask Violation! Frequency(GHz) 22

23 Solutions to Reduce Vertical Coupling in Mixed-Signal 3D-IC RF/Analog Chip RF/Analog Chip Mesh Shield using Back-side RDL RF/Analog Chip Adhesive Digital Logic Chip (Noise Aggressor) Mixed-signal 3D-IC Mesh shield using back-side re-distribution layer (RDL) Magnetic material shielding Additional chip Additional chip : For dedicated power/ground with on-chip de-cap. For re-distribution layer Dedicated chip for on-chip decoupling cap or re-distribution layer 23

24 Vertical Coupling from On-Chip DC-DC Converter to LNA PCB 2MHz, Duty.5 Clock at DC-DC Converter Driver Off-Chip Port : LNA Output; Out + Off-Chip Port : LNA Output; Out - On-Chip Port : DC-DC Converter Output; VDD out LNA chip Epoxy 5µm/1µm 2µm On-chip DC-DC Converter Chip PCB 24

25 Inductive and Capacitive Coupling Model VDD VDD in On-chip L M = 6pH C C = 6fF 12nH Out+ Q1 37nH VDD out 5Ω On-chip Q2 Equiv. Model of Q2 Simplified Model of On-Chip DC-DC Converter Simplified Model of LNA 25

26 Measurement of Vertical Coupling : Coupled Noise at LNA output(mv) LNA Out+ LNA Out- 5ns (2MHz) LNA Out+ LNA ~4mV pp ripple at VDD out 88mV pp /48mV pp coupled noise x 1at -8 LNA Out +/- Out- Vertical coupling from DC-DC Converter to LNA On-Chip Port : DC-DC Converter Outut; VDD out Time from Triggered point(ns) DUT 1-5µm Typical RF signal at LNA output: start from -9dBm (2µV pp with 5Ω load)? 26

27 SSN Sensitive Circuits in IC - VCO: Voltage Controlled Oscillator - PLL: Phase Locked Loop - ADC: Analog to Digital Converter - DAC: Digital to Analog Converter - LNA: Low Noise Amplifier - RF Mixers 27

28 Hierarchical PDN in 3D IC Chip ADC, DAC Memory RF Memory Silicon Interposer ADC, GPUDAC ADC, Analog DAC Inductor n+ n+ NMOS Cap p+ p+ n-well Memory Package ground power PCB ground 28

29 PDN Impedance Curves in 3D IC Figure Fig. 3-(a) Peak ( region V ) Mode number a, b, d, f (1,), (2,), (3,), (4,)/(,1) - DRAM c, e (2,1), (3,1) - Interposer 29

30 PDN Impedance of 3D IC with On-chip Decoupling Capacitors 3

31 Lowering PDN impedance in TSV based 3D IC - On-chip and Off-chip decoupling capacitors - Lower inductance TSV, - Higher number of TSV - Lower inductance of PDN interconnections in RDL, on-chip, and interposer - Lower resistance of PDN interconnections in RDL, on-chip, and interposer 31

32 PDN Noise coupling pathes in3d IC Chip ADC, DAC Memory RF Memory Silicon Interposer ADC, GPUDAC ADC, Analog DAC Inductor n+ n+ NMOS Cap p+ p+ n-well Memory Package ground power PCB ground 32

33 SSN Noise Coupling Paths - On-chip and Off-chip PDN - Si substrate - Interposer substrate - RDL patterns - TSV - Coupling 33

34 Clock Jitter Due to the SSN Coupling w/o PDN Noise 1MHz PDN Noise Noise Level 1.45 ps ps 8MHz PDN Noise 1GHz PDN Noise 33 ps 2.3 ps Duty Cycle Distortion 34

35 Jitter w/o and w PDN Models Noise level : 1 mv Input Clock Frequency of DLL = 1 GHz Voltage of SSN w/o PDN models Jitter due to SSN w/o PDN models Voltage of SSN w PDN models Jitter due to SSN w PDN models Jitter (ps) Coupling Ratio M 1G Noise Freq. (Hz)

36 Noise Isolation Techniques Applicable to 3D ICs At Low Frequency Region ( < several hundred MHz ) Off-chip decap Split P/G planes At Mid. Frequency Region ( < several GHz ) On-chip decap Embedded cap in interposer Trench, MiM cap with a high K material At High Frequency Region ( > tens GHz) On-chip EBG in the interposer Connected with TSVs Design issues : High Q inductor and Low ESR Chip Interposer Package PCB MOScap Trench Cap MiM Cap Source Gate Drain 3um n+ n+ Bulk 5um TiN High K SiO2 Metal Metal dielectric Spiral inductor Slotted P/G Planes 36

37 On-Interposer EBG Structure Capacitive P/G mesh W S Width: 8um Space: 12um Inductive P/G mesh S W Width: 4um Space: 36um 37

38 Measurement Results of On-interposer EBG -1 Mesh PDN TV A (Mesh) TV B (EBG) Coupling Coefficients, S21 (db) Stopband Interposer EBG Frequency (GHz) 38

39 Measurement Results of On-interposer EBG Coupled Noise Spectrum (dbm) GHz TV A (Mesh) TV B (EBG) Frequency (GHz) 39

40 On-chip CMOS Active EBG Spiral inductor W inductor Winductor 1.5 mm Port 1 Port 2 t top Si-substrate NMOS cap. 1.2 mm 4

41 SEM Photograph of On-chip Active CMOS EBG Spiral inductor (portion) Via t metal t top t IMD M6 M5 M4 M3 M2 M1 Gate (1µm) Gate finger Sisubstrate * MagnaChip.18μm standard CMOS Process 41

42 Measured S21 of On-chip Active CMOS EBG -1-2 TV A (Meshed plane) TV B (Decap. Array) TV C (Active EBG) S21 [db] ~ 11.3 GHz (9 GHz) Frequency [GHz] 42

43 Tuning of On-chip Active CMOS EBG -1 TV C with V power (OFF) TV C with 1.8V power (ON) -2 S21 [db] ~ 13.3 GHz 2.3 ~ 11.3 GHz Frequency [GHz] 43

44 Measured SSN Waveforms with a 3-GHz Clock Noise Input 15 1 TV A 15 1 TV B Coupled SSN [mv] mV Coupled SSN [mv] mV Coupled SSN [mv] Time [ns] (a) TV C with V power 23.4mV Time [ns] (c) Coupled SSN [mv] Time [ns] (b) TV C with 1.8V power 5.1mV Time [ns] (d) 44

45 Summary -TSV is the most critical interconnection structure in 3D IC. - TSV can cause significant channel loss for high-speed signaling. - Equalizer or specific I/O schemes are needed to support low power and high-speed data transmissions. -Crosstalk and coupling between TSV and active circuit need to be considered when designing the TSV arrangement configurations. -Vertical coupling should be considered in mixed mode 3D IC. - Shielding structures are needed to reduce the TSV crosstalks and noise couplings. 45

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