TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 TC5565AFL-10, TC5565AFL-12, TC5565AFL-15
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- Verity Gibbs
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1 TOSHIBA MOS MEMORY PRODUCTS TC5565APL-10, TC5565APL-12, TC5565APL-15 DESCRIPTION The TC5565APL/AFL is 65,536 bit static random access memory organized as 8,192 words by 8 bits using CMOS technology, and operates from a single 5V supply. Advanced circuit techniques provide both high speed and low power features with a maximum operating current of 5mA/MHz and maximum access time of 100ns/120ns/150ns. When CE2 is a logical low or \CEl is a logical high, the device is placed in low power standby mode in which standby current is 2uA typically. The TC5565APL/AFL has three control inputs. Two chip enable (\CE1, CE2) allow for device selection and data retention control, and an output enable input (\OE) provides fast memory access. Thus the TC5565APL/AFL is suitable for use in various microprocessor application systems where high speed, low power, and battery back up are required. The TC5565APL also features pin compatibility with the 64K bit EPROM (TMM2764D). RAM and EPROM are then interchangeable in the same socket, resulting in flexibility in the definition of the quantity of RAM versus EPROM in microprocessor application systems. The TC5565APL is offered in a dual-in-line 28 pin standard plastic package. The TC5565AFL is offered in 28 pin mini Flat Package. FEATURES Low Power Dissipation 27.5mW/MHz(Max.) operating Standby Current: 100uA(Max.) Ta=70 C Access Time TC5565APL/AFL-10 : 100ns(Max.) TC5565APL/AFL-12 : 120ns(Max.) TC5565APL/AFL-15 : 150ns(Max.) 5V Single Power Supply - Power Down Features: CE2, \CE1 Fully Static Operation Data Retention Supply Voltage: V PIN CONNECTION (TOP VIEW) Directly TTL Compatible : All Inputs and Outputs Pin Compatible with 2764 type EPROM TC5565APL Family (Package Type) Package Type Device Name 600 mil DIP TC5565APL 300 mil DIP *TC5563APL (Slim Package) Flat Package TC5565AFL (SOP) * See TC5563APL Technical Data. BLOCK DIAGRAM AO-A12 R/W \OE \CE1, CE2 I/O1 I/O8 V DD GND N.C. Address Inputs Read/Write Control Input Output Enable Input Chip Enable Inputs Data Input/Output Power (+5V) Ground No Connection
2 OPERATION MODE \CE1 CE2 \OE R/W 1/01-T/08 POWER Read L H L H D OUT I DDO Write L H * L D IN I DDO Output Deselect L H H H High-Z I DDO Standby H * * * High-Z I DDS L * * High-Z I DDS MAXIMUM RATINGS SYMBOL ITEM RATING UNIT V DD Power Supply Voltage -0.3~7.0 v V IN Input Voltage *-0.3~7.0 v V I/O Input and Output Voltage -0-5-VDD+0.5 v P D Power Dissipation 1.0/0.6** W T solder Soldering Temperature C sec T stg Storage Temperature -55~150 C T opr Operating Temperature 0-70 C * -3.0V at pulse width 50ns MAX. **Flat package D.C RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER MIN. Typ. MAX. UNIT V DD Power Supply Voltage v V IH Input High Voltage V DD +0.3 v V IL Input Low Voltage V V DH Data-Retention Supply Voltage V
3 D.C and OPERATING CHARACTERISTICS (Ta=0~70 C, V DD = 5V±10%) SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT I IL Input Leakage Current V IN= O~V DD - - ±1.0 ua I OH Output High Current VOH-2-4V ma I OL Output Low Current VOL-0.4V ma I LO Output Leakage Current V IH or CE2-VOL or \CE1 = V IH or CE2=V OL 0r R/W = V IL or \OE=V IH - - ±1.0 ua V OUT =0~V DD t cycle =1.0us 10 ma TC5565APL-10 TC556SAFL-10 t cycle =100ns ma I DDO1 V DD =5.5V \CE1=V IL CE2=V IH Other input= V IH /V IL TC5565APL-12 TC5565AFL-12 t cycle =120ns ma Operating Current TC5565A?L-15 TC5565AFL-15 t cycle =150ns ma t cycle=1.0us ma I DD02 V DD= 5.5V \CEl=O.2V CE2=V DD 0.2V Other lnput= V DD - 0.2V/0.2V TC5565APL-10 TC5565AFL-10 TC5565AFL-12 TC5565AFL-12 t cycle =100ns ma t cycle =120ns ma TC5565APL-15 TC5565AFL-15 t cycle =150ns ma I DDS1 \Cel = V IH or CE2 = V IL 3 ma V DD = 5.5V ua Standby Current \CE1 = V DD 0.2V or *I DDS2 V CE2 = 0.2V DD = 3.0V ua Note * In standby mode with \CE1>= V DD 0.2V, these specification limits are guaranteed under the condition of CE2 >= V DD 0.2V or CE2 <= 0.2V. CAPACITANCE (Ta=25 C) SYMBOL PARAMETER TEST CONDITION MIN. TYP. MAX. UNIT C IN Input Capacitance V IN = GND pf C OUT Output Capacitance V OUT = GND pf * This parameter periodically sampled is not 100% tested.
4 A.C. CHARACTERISTICS (Ta=0~70 C, V DD = 5V±10%) Read Cycle SYMBOL PARAMETER TC5565APL-10 TC5565AFL-10 TC5565APL-12 TC5565APL-15 TC5565AFL-12 TC5565AFL-15 MIN. MAX. MIN. MAX. MIN. MAX t RC Read Cycle Time t ACC Address Access Time t COL \CE1 Access Time t C02 CE2 Access Time t OE Output Enable to Output Valid t COE Chip Enable (\CE1, CE2) to Output in Low-Z t OEE Output Enable to Output in Low-Z t OD Chip Enable (CE1, CE2) to Output in High-Z t ODO Output Enable to Output in High-Z t OH Output Data Hold Time Write Cycle SYMBOL PARAMETER TC5565APL-10 TC5565AFL-10 TC5565APL-12 TC5565APL- 5 TC5565AFL-12 TC5565AFL- 5 MIN. MAX. MIN. MAX. MIN. MAX.. t WC Write Cycle Time t WP Write Pulse Width t CW Chip Selection to End of Write t AS Address Set up Time r WR Write Recovery Time t ODW R/W to Output High-Z r OEW R/W to Output Low-Z t DS Data Set up Time t DH Data Hold Time A.C. TEST CONDITION Output Load : 100pF + 1 TTL Gate Input Pulse Level : 0.6V, 2.4V Timing Measurement V IN : 0.8V, 2.2V Reference Level V OUT : 0.8V, 2.2V t r, t f : 5ns
5 TIMING WAVEFORMS READ CYCLE (1) TC5565APL-10, TC5565APL-12, TC5565APL-15 WRITE CYCLE 1 (4) (R/W Controlled Write)
6 WRITE CYCLE 2 (4) (\CE1 Controlled Write) WRITE CYCLE 3 (4) (CE2 Controlled Write)
7 Note 1. R/W is High for Read Cycle. 2. Assuming that \CE1 Low transition of CE2 High transition occurs coincident with or after R/W Low transition, Outputs remain in a high impedance state. 3. Assuming that \CEl High transition or CE2 Low transition occurs coincident with or prior to R/W High transition, Outputs remain in a high impedance state. 4. Assuming that \OE is High for Write Cycle, Outputs are in high impedance state during this period. DATA RETENTION CHARACTERISTICS (Ta=0~70 C) SYMBOL PARAMETER MIN. TYP. MAX. UNIT V DH Data Retention Supply Voltage V Stand by Supply Current VDD=3.0V I DDS2 ua VDD=5.5V t CDR Chip Deselection to Data Retention Mode us t R Recovery Mode trc(1) - - us Note (1) : Read cycle Time. \CE1 Controlled Data Retention Mode (2) CE2 Controlled Data Retention Mode (4)
8 Note 2 : In \CE1 controlled data retention mode, minimum standby current mode is achieved under the condition Of CE2<= O.2V Or CE2>= V DD -0.2V. 3 : If the V IH of \CE1 is 2.2V in operation, I DDS1 current flows during the period that the V DD voltage is going down from 4.5V to 2.4V, 4 ; In CE2 controlled data retention mode, minimum standby current mode is achieved under the condition of CE2 <= 0.2V. DEVICE INFORMATION The TC5565APL/AFL is an synchronous RAM using address activated circuit technology, thus the internal operation is synchronous. Then once row address change occur, the precharge operation is executed by internal pulse generated from row address transient. Therefore the peak current flows only after row address change, as shown in the following figure. This peak current may induce the noise on V DD /GND lines. Thus the use of about 0.1uF decoupling capacitor for every device is recommended to eliminate such noise.
9 DIP 28 PIN OUTLINE DRAWING (6D28A-P) Unit in mm Note) Lead pitch is 2.54 and tolerance is +\-0.25 against theoretical center of each lead that is obtained on the basis of No.1 and No.28 leads. MFP 28 PIN OUTLINE DRAWING (F28GC-P) Unit in mm Note) Lead pitch is 1.27 and tolerance is +\-0.12 against theoretical center of each lead that is obtained on the basis of No.1 and N0.28 leads
Pin Connection (Top View)
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SRM2B256SLMX55/70/10
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Functional Block Diagram. Row Decoder. 512 x 512 Memory Array. Column I/O. Input Data Circuit. Column Decoder A 9 A 14. Control Circuit
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Features Fast Read Access Time 150 ns Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer Fast Write Cycle Times Page Write Cycle Time: 3 ms or 10 ms Maximum
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Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
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FEATURES Wide operation voltage : 24~55V Very low power consumption : = 30V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade:
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7
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PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible
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I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
Features High speed t AA = 12 ns Low active power 1320 mw (max.) Low CMOS standby power (Commercial L version) 2.75 mw (max.) 2.0V Data Retention (400 µw at 2.0V retention) Automatic power-down when deselected
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89LV1632 16 Megabit (512K x 32Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32bit) SRAM MCM CS 14 Address OE, WE 89LV1632 Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM FEATURES: I/O 7 I/O 815 I/O
5V 128K X 8 HIGH SPEED CMOS SRAM
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CY Features. Logic Block Diagram
Features Temperature Ranges -Commercial:0 to 70 -Industrial: -40 to 85 -Automotive: -40 to 125 High speed: 55ns and 70 ns Voltage range : 4.5V 5.5V operation Low active power (70ns, LL version, Com l and
2 Mbit ROM + 1 Mbit / 2Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR021 / SST30VR022 / SST30VR023
FEATURES: SST30VR021/022/0232 Mb Mask ROM (x8) + 1 Mb / 2Mb / 256 Kb SRAM (x8) Combo ROM + SRAM SST30VR021: 256K x8 ROM + 128K x8 SRAM SST30VR022: 256K x8 ROM + 256K x8 SRAM SST30VR023: 256K x8 ROM + 32K
28C010T. 1 Megabit (128K x 8-Bit) EEPROM. Memory FEATURES: DESCRIPTION: Logic Diagram
28C1T 1 Megabit (128K x 8-Bit) EEPROM FEATURES: 128k x 8-bit EEPROM RAD-PAK radiation-hardened agait natural space radiation Total dose hardness: - > 1 krad (Si), depending upon space mission Excellent
4Mb Ultra-Low Power Asynchronous CMOS SRAM. Features. Power Supply (Vcc) Operating Temperature A 0 -A 17 I/O 0 -I/O 15 V CC V SS
4Mb Ultra-Low Power Asynchronous CMOS SRAM 256K 16 bit N04L63W2A Overview The N04L63W2A is an integrated memory device containing a 4 Mbit Static Random Access Memory organized as 262,144 words by 16 bits.
I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 A 16 I/O 7 A 15 7
Features High speed t AA = 12 ns Low active power 495 mw (max.) Low CMOS standby power 11 mw (max.) (L Version) 2.0V Data Retention Automatic power-down when deselected TTL-compatible inputs and outputs
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Features Fast Read Access Time 90 ns Dual Voltage Range Operation Unregulated Battery Power Supply Range, 2.7V to 3.6V or Standard 5V ± 10% Supply Range Compatible with JEDEC Standard AT27C010 Low Power
128K x 8 Static RAM CY7C1019B CY7C10191B. Features. Functional Description. Logic Block Diagram. Pin Configurations
128K x 8 Static RAM Features High speed t AA = 10, 12, 15 ns CMOS for optimum speed/power Center power/ground pinout Automatic power-down when deselected Easy memory expansion with and OE options Functionally
16 Meg FPM DRAM AS4LC4M4. 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT ACTIVE POWER DISSIPATION PERFORMANCE RANGE
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS MIL-STD-883 FEATURES Fast Page Mode Operation CAS\-before-RAS\ Refresh Capability RAS\-only and
SERIAL I/O REAL TIME CLOCK
SERIAL REAL TIME CLOCK GENERAL DESCRIPTION The NJU6355 series is a serial real time clock suitable for 4 bits microprocessor. It contains quartz crystal oscillator, counter, shift register, voltage regulator,
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
4-Megabit (512K x 8) OTP EPROM AT27C040
Features Fast Read Access Time 70 ns Low Power CMOS Operation 100 µa Max Standby 30 ma Max Active at 5 MHz JEDEC Standard Packages 32-lead PDIP 32-lead PLCC 32-lead TSOP 5V ± 10% Supply High Reliability
Rev. No. History Issue Date Remark
8K X 8 BIT CMOS SRAM Document Title 8K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 9, 2004 Preliminary 1.0 Remove non-pb-free package type July 3, 2006
SOIC (SOP) NC A8 A9 A10 A11 A12 A13 A14 A15 A16 NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 BYTE/VPP GND O15/A-1 GND O7 O14 O6 O13 O5 O12 O4 VCC
Features Read Access Time - 100 ns Word-wide or Byte-wide Configurable 8-Megabit Flash and Mask ROM Compatable Low Power CMOS Operation -100 µa Maximum Standby - 50 ma Maximum Active at 5 MHz Wide Selection
UM61512A Series 64K X 8 BIT HIGH SPEED CMOS SRAM. Features. General Description. Pin Configurations UM61512AV UM61512A
Series 64K X 8 BIT HIGH SPEE CMOS SRAM Features Single +5V power supply Access times: 15/20/25ns (max.) Current: Operating: 160mA (max.) Standby: 10mA (max.) Full static operation, no clock or refreshing
R1RP0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. Ordering Information. REJ03C Z Rev Mar.12.
4M High Speed SRAM (256-kword 16-bit) REJ03C0108-0100Z Rev. 1.00 Mar.12.2004 Description The R1RP0416D Series is a 4-Mbit high speed static RAM organized 256-k word 16-bit. It has realized high speed access
IS62/65WV102416EALL IS62/65WV102416EBLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating (typical): - 10.8mW (1.8V), 18mW (3.0V) CMOS Standby (typical): - 48
EEPROM AS8ER128K32 FUNCTIONAL BLOCK DIAGRAM. 128K x 32 Radiation Tolerant EEPROM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
128K x 32 Radiation Tolerant EEPROM AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38534 FEATURES Access time of 150ns, 200ns, 250ns Operation with single 5V + 10% supply Power Dissipation: Active: 1.43
PART TEMP RANGE PIN-PACKAGE SPEED
Rev 0; 8/06 General Description The is a 16Mb reflowable nonvolatile (NV) SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These
UNISONIC TECHNOLOGIES CO., LTD CD4069
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IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
NMC27C32B Bit (4096 x 8) CMOS EPROM
NMC27C32B 32 768-Bit (4096 x 8) CMOS EPROM General Description The NMC27C32B is a 32k UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications where fast turnaround pattern
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 467 mw (max, 12 ns L version) Low standby power 0.275 mw (max, L version) 2V data retention ( L version only) Easy memory
DS Tap High Speed Silicon Delay Line
www.dalsemi.com FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances
NM27C ,288-Bit (64K x 8) High Performance CMOS EPROM
NM27C512 524,288-Bit (64K x 8) High Performance CMOS EPROM General Description The NM27C512 is a high performance 512K UV Erasable Electrically Programmable Read Only Memory (EPROM). It is manufactured
Rev. No. History Issue Date Remark
32K X 8 BIT CMOS SRAM Document Title 32K X 8 BIT CMOS SRAM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue February 2, 2001 Preliminary 0.1 Add ultra temp grade and 28-pin DIP package
Revision No History Draft Date Remark. 10 Initial Revision History Insert Jul Final
128Kx8bit CMOS SRAM Document Title 128K x8 bit 5.0V Low Power CMOS slow SRAM Revision History Revision No History Draft Date Remark 10 Initial Revision History Insert Jul.14.2000 Final 11 Marking Information
I/O1 ~ I/O8 I/O9 ~ I/O16 I/O9 ~ I/O16 I/O1 ~ I/O8
Document Title 64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges. Revision History Rev. No. History Draft Data Remark Rev. 0.0 Initial release
PSRAM 2-Mbit (128K x 16)
PSRAM 2-Mbit (128K x 16) Features Wide voltage range: 2.7V 3.6V Access Time: 55 ns, 70 ns Ultra-low active power Typical active current: 1mA @ f = 1 MHz Typical active current: 14 ma @ f = fmax (For 55-ns)
256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. 256K (32K x 8) Static RAM Features Temperature Ranges Commercial: 0 C to
Multiplexer for Capacitive sensors
DATASHEET Multiplexer for Capacitive sensors Multiplexer for Capacitive Sensors page 1/7 Features Very well suited for multiple-capacitance measurement Low-cost CMOS Low output impedance Rail-to-rail digital
256K (32K x 8) Static RAM
256K (32K x 8) Static RAM Features High speed 55 ns Temperature Ranges Commercial: 0 C to 70 C Industrial: 40 C to 85 C Automotive: 40 C to 125 C Voltage range 4.5V 5.5V Low active power and standby power
27C Bit ( x 8) UV Erasable CMOS PROM Military Qualified
27C256 262 144-Bit (32 768 x 8) UV Erasable CMOS PROM Military Qualified General Description The 27C256 is a high-speed 256K UV erasable and electrically reprogrammable CMOS EPROM ideally suited for applications
M74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation
28LV Megabit (128K x 8-Bit) EEPROM. Memory DESCRIPTION: FEATURES: 28LV011A. Logic Diagram
28LV11 1 Megabit (128K x 8-Bit) EEPROM V CC V SS High Voltage Generator I/O I/O7 RDY/Busy RES OE I/O Buffer and Input Latch CE WE RES Control Logic Timing 28LV11A A A6 Y Decoder Y Gating A7 Address Buffer
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM
NM27C010 1,048,576-Bit (128K x 8) High Performance CMOS EPROM General Description The NM27C010 is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
I/O 1 I/O 2 I/O 3 A 10 6
Features High speed 12 ns Fast t DOE CMOS for optimum speed/power Low active power 495 mw (Max, L version) Low standby power 0.275 mw (Max, L version) 2V data retention ( L version only) Easy memory expansion
FST Bit Low Power Bus Switch
2-Bit Low Power Bus Switch General Description The FST3306 is a 2-bit ultra high-speed CMOS FET bus switch with TTL-compatible active LOW control inputs. The low on resistance of the switch allows inputs
GLS27SF / 1 / 2 / GLS27SF010 / GLS27SF020
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash FEATURES: GLS27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories Organized as 64K x8 / 128K x8 / 256K x8 4.5-5.5V Read Operation
AS4C256K16E0. 5V 256K 16 CMOS DRAM (EDO) Features. Pin designation. Pin arrangement. Selection guide
5V 256K 16 CMOS DRAM (EDO) Features Organization: 262,144 words 16 bits High speed - 30/35/50 ns access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time Low power consumption
M74HC51TTR DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE
DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE HIGH SPEED: t PD = 11ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
Radiation Hardened 32K x 8 CMOS EEPROM
Radiation Hardened 32K x 8 CMOS EEPROM Introduction The W28C256 is a 32K x 8 radiation hardened EEPROM designed by Sandia National Laboratories, Albuquerque, NM, and manufactured by the Northrop Grumman
A 4 A 3 A 2 ROW DECODER 64K x 16 RAM Array I/O 1 I/O X 2048 I/O 9 I/O 16
021 CY7C1021 Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 1320 mw (max.) Automatic power-down when deselected Independent Control of Upper and Lower bits Available in
128K (16K x 8-Bit) CMOS EPROM
1CY 27C1 28 fax id: 3011 CY27C128 128K (16K x 8-Bit) CMOS EPROM Features Wide speed range 45 ns to 200 ns (commercial and military) Low power 248 mw (commercial) 303 mw (military) Low standby power Less
LY62L K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY Revision Description Issue Date Rev. 1.0 Initial Issue Jul.25.2004 Rev. 1.1 Adding PKG type : 32 SOP Mar.3.2006 Adding PKG type : 32 P-DIP Revised Test Condition of ISB1/IDR May.14.2007