BSI BH62UV8000. Ultra Low Power/High Speed CMOS SRAM 1M X 8 bit

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1 FEATURES Wide low operation voltage : 1.65V ~ 3.6V Ultra low power consumption : = 3.0V = 2.0V High speed access time : ns at 1.V at 5 O C Ultra Low Power/High Speed CMOS SRAM 1M X bit Operation current : 5.0mA at 70ns at 25 O C Standby current : 2.5uA at 25 O C 1.5mA at 1MHz at 25 O C Data retention current : 2.5uA at 25 O C Automatic power down when chip is deselected Easy expansion with, and OE options Three state outputs and TTL compatible Fully static operation, no clock, no refreash Data retention supply voltage as low as 1.0V DESCRIPTION The is a high performance, ultra low power CMOS Static Random Access Memory organized as 1,04,576 by bits and operates in a wide range of 1.65V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical operating current of 1.5mA at 1MHz at 3.6V/25 O C and maximum access time of 70ns at 1.V/5 O C. Easy memory expansion is provided by an active LOW chip enable (), an active HIGH chip enable () and active LOW output enable (OE) and three-state output drivers. The has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The is available in DICE form and 4-ball BGA package. PRODUCT FAMILY PRODUCT FAMILY OPERATING TEMPERATURE RANGE SPEED (ns) POWER CONSUMPTION STANDBY (ICCSB1, Max) Operating (ICC, Max) PKG TYPE =1.~3.6V =3.6V =1.V =3.6V =1.V AI DI +0 O C to +70 O C 70 13uA 10uA 10mA 7mA 1.65V ~ 3.6V -25 O C to +5 O C 70 15uA 12uA 10mA 7mA BGA DICE PIN CONFIGURATIONS BLOCK DIAGRAM A B C DQ0 OE A0 A3 A5 A1 A2 A4 A6 D04 A12 A11 A10 A9 A A7 A6 A5 A4 A3 Address Input Buffer 10 Row Decoder 1024 Memory Array 1024 x 1192 D E F VSS VCC D3 DQ1 DQ2 A17 VSS A14 A7 A16 A15 DQ5 DQ6 VCC VSS DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Data Input Buffer Data Output Buffer 192 Column I/O Write Driver Sense Amp 1024 Column Decoder G H A1 A A12 A9 A13 A10 WE A11 A19 WE OE Control 10 Address Input Buffer 4-ball BGA top view VCC GND A19 A1 A17 A15 A14 A13 A16 A2 A1 A0 Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice. Detailed product characteristic test report is available upon request and being accepted. R0201- Revision 1.0 1

2 PIN DESCRIPTIONS Name Function A0-A19 Address Input These 20 address inputs select one of the 1,04,576 x bit in the RAM Chip Enable 1 Input Chip Enable 2 Input WE Write Enable Input OE Output Enable Input DQ0-DQ7 Data Input/Output Ports is active LOW and is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. bi-directional ports are used to read data from or write data into the RAM. Power Supply V SS Ground TRUTH TABLE MODE WE OE I/O OPERATION CURRENT Chip De-selected (Power Down) H X X X X L X X High Z I CCSB, I CCSB1 Output Disabled L H H H High Z I CC Read L H H L I CC Write L H L X D IN I CC NOTES: H means V IH; L means V IL; X means don t care (Must be V IH or V IL state) ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS V TERM T BIAS Terminal Voltage with Respect to GND Temperature Under Bias -0.5 (2) to 4.6V V -40 to +125 T STG Storage Temperature -60 to +150 P T Power Dissipation 1.0 W I OUT DC Output Current 20 ma 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability V in case of AC pulse width less than 30 ns O C O C OPERATING RANGE RANG AMBIENT TEMPERATURE Commercial 0 O C to + 70 O C 1.65V ~ 3.6V Industrial -25 O C to + 5 O C 1.65V ~ 3.6V CAPACITAE (1) (T A = 25 O C, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS C IN Input Capacitance V IN = 0V 6 pf C IO Input/Output Capacitance V I/O = 0V pf 1. This parameter is guaranteed and not 100% tested. R0201- Revision 1.0 2

3 DC ELECTRICAL CHARACTERISTICS (T A = -25 O C to +5 O C) PARAMETER PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS Power Supply V V IL V IH I IL I LO V OL V OH I CC I CC1 I CCSB I CCSB1 Input Low Voltage Input High Voltage Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Operating Power Supply Current Operating Power Supply Current Standby Current TTL Standby Current CMOS V IN = 0V to, = V IH or = V IL V I/O = 0V to, = V IH or = V IL or OE = V IH VCC=1.V 0.4 VCC=1.V (2) V (3) V ua ua = Max, I OL = 0.1mA VCC=1.V = Max, I OL = 2.0mA 0.4 = Min, I OH = -0.1mA VCC=1.V -0.2 = Min, I OH = -1.0mA 2.4 = V IL, = V IH, I DQ = 0mA, f = F MAX (4) = V IL and = V IH, I DQ = 0mA, f = 1MHz = V IH, or = V IL, I DQ = 0mA 1. Typical characteristics are at T A=25 O C. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: +1.0V in case of pulse width less than 20 ns. 4. F MAX=1/t RC. 5. I CCSB1(MAX.) is 10uA/13uA at =1.V/3.6V and T A=0 O C ~ 70 O C. -0.2V or 0.2V, V IN -0.2V or V IN 0.2V DATA RETENTION CHARACTERISTICS (T A = -25 O C to +5 O C) V V VCC=1.V VCC=1.V VCC=1.V VCC=1.V SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS ma ma ma ua V DR I CCDR (3) t CDR t R for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time -0.2V or 0.2V, VIN -0.2V or VIN 0.2V -0.2V or 0.2V, VIN -0.2V or VIN 0.2V See Retention Waveform 1. T A=25 O C. 2. t RC = Read Cycle Time. 3. I CCDR(MAX.) is 2.5uA /10uA at =1.0V/2.0V and T A=0 O C ~ 70 O C V VCC=1.0V VCC=2.0V ua ns t RC (2) ns LOW DATA RETENTION WAVEFORM (1) ( Controlled) Data Retention Mode t CDR V DR 1.0V t R V IH - 0.2V V IH R0201- Revision 1.0 3

4 LOW DATA RETENTION WAVEFORM (2) ( Controlled) Data Retention Mode V DR 1.0V t CDR t R V IL 0.2V V IL AC TEST CONDITIONS (Test Load and Input/Output Reference) Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level t CLZ1, t CLZ2, t OLZ, t CHZ1, Output Load t CHZ2, t OHZ, t WHZ, t OW Others Output 1 TTL C L (1) GND 1. Including jig and scope capacitance. 10% / 0V 1V/ns 0.5Vcc C L = 5pF+1TTL C L = 30pF+1TTL ALL INPUT PULSES 90% Rise Time: 1V/ns 90% 10% Fall Time: 1V/ns KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOW CENTER LINE IS HIGH INPEDAE OFF STATE AC ELECTRICAL CHARACTERISTICS (T A = -25 O C to +5 O C) READ CYCLE JEDEC PARAMETER PARANETER DESCRIPTION CYCLE TIME : 70ns MIN. TYP. MAX. UNITS t AVAX t RC Read Cycle Time ns t AVQX t AA Address Access Time ns t E1LQV t ACS1 Chip Select Access Time () ns t E2LQV t ACS2 Chip Select Access Time () ns t GLQV t OE Output Enable to Output Valid ns t E1LQX t CLZ1 Chip Select to Output Low Z () ns t E2LQX t CLZ2 Chip Select to Output Low Z () ns t GLQX t OLZ Output Enable to Output Low Z ns t E1HQZ t CHZ1 Chip Select to Output High Z () ns t E2HQZ t CHZ2 Chip Select to Output High Z () ns t GHQZ t OHZ Output Enable to Output High Z ns t AVQX t OH Data Hold from Address Change ns R0201- Revision 1.0 4

5 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) t RC ADDRESS t OH t AA t OH READ CYCLE 2 (1,3,4) t ACS1 t CLZ t ACS2 t CHZ1, t CHZ2 READ CYCLE 3 (1, 4) t RC ADDRESS t AA OE t OE t OH t OLZ t CLZ1 t ACS1 t ACS2 t CLZ2 t OHZ (1,5) t CHZ1 t CHZ2 (2,5) NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when = V IL and = V IH. 3. Address valid prior to or coincident with transition low and/or transition high. 4. OE = V IL. 5. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. R0201- Revision 1.0 5

6 AC ELECTRICAL CHARACTERISTICS (T A = -25 O C to +5 O C) WRITE CYCLE JEDEC PARAMETER PARANETER DESCRIPTION CYCLE TIME : 70ns MIN. TYP. MAX. UNITS t AVAX t WC Write Cycle Time ns t AVWL t AS Address Set up Time ns t AVWH t AW Address Valid to End of Write ns t ELWH t CW Chip Select to End of Write ns t WLWH t WP Write Pulse Width ns t WHAX t WR1 Write Recovery Time (, WE) ns t E2LAX t WR2 Write Recovery Time () ns t WLQZ t WHZ Write to Output High Z ns t DVWH t DW Data to Write Time Overlap ns t WHDX t DH Data Hold from Write Time ns t GHQZ t OHZ Output Disable to Output in High Z ns t WHQX t OW End of Write to Output Active ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) ADDRESS twc OE t WR1 (3) t CW (11) WE t AS t AW t CW (11) t WP (2) t WR2 (3) t OHZ (4,10) t DH t DW D IN R0201- Revision 1.0 6

7 WRITE CYCLE 2 (1,6) t WC ADDRESS t CW (11) WE t AW t CW (11) t WP (2) t WR2 (3) t AS t WHZ (4,10) t OW (7) () t DW t DH (,9) D IN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of and active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. t WR is measured from the earlier of or WE going high or going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the low transition or the high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = V IL). 7. is the same phase of write data of this write cycle.. is the read data of next address. 9. If is low and is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured ± 500mV from steady state with C L = 5pF. The parameter is guaranteed but not 100% tested. 11. t CW is measured from the later of going low or going high to the end of write. R0201- Revision 1.0 7

8 ORDERING INFORMATION X X Z Y Y SPEED 70: 70ns PKG MATERIAL -: Normal G: Green GRADE I: -25 o C ~ +5 o C PACKAGE A: BGA D: DICE Note: Brilliance Semiconductor Inc. () assumes no responsibility for the application or use of any product or circuit described herein. does not authorize its products for use as critical components in any application in which the failure of the product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. 1.4 Max. BALL PITCH e = 0.75 D E N D1 E D1 E1 e VIEW A 4 mini-bga (6 x ) R0201- Revision 1.0

9 Revision History Revision No. History Draft Date Remark 1.0 Initial Production Version July 15,2005 Initial R0201- Revision 1.0 9

Very Low Power CMOS SRAM 2M X 8 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V

Very Low Power CMOS SRAM 2M X bit Pb-Free and Green package materials are compliant to RoHS BS62LV1600 FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption : = 3.0V Operation current