Very Low Power CMOS SRAM 64K X 16 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V

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1 Very Low Power CMOS SRAM 64K X 16 bit Pb-Free and Green package materials are compliant to RoHS BS616LV1010 FEATURES Wide operation voltage : 24V ~ 55V Very low power consumption : = 30V Operation current : 25mA (Max) at 55ns 2mA (Max) at 1MHz Standby current : 002uA (Typ) at 25 O C = 50V Operation current : 45mA (Max) at 55ns 5mA (Max) at 1MHz Standby current : 04uA (Typ) at 25 O C High speed access time : ns(Max) at =27~55V ns(Max) at =24~55V Automatic power down when chip is deselected Easy expansion with and OE options I/O Configuration x8/x16 selectable by LB and UB pin Three state outputs and TTL compatible Fully static operation Data retention supply voltage as low as 15V DESCRIPTION The BS616LV1010 is a high performance, very low power CMOS Static Random Access Memory organized as 65,536 by 16 bits and operates form a wide range of 24V to 55V supply voltage Advanced CMOS technology and circuit techniques provide both high speed and low power features with typical CMOS standby current of 002uA at 30V/25 O C and maximum access time of 55ns at 27V/85 O C Easy memory expansion is provided by an active LOW chip enable () and active LOW output enable (OE) and three-state output drivers The BS616LV1010 has an automatic power down feature, reducing the power consumption significantly when chip is deselected The BS616LV1010 is available in DI form, JEDEC standard 44-pin TSOP II and 48-ball BGA package POWER CONSUMPTION PRODUCT FAMILY BS616LV1010DC BS616LV1010AC BS616LV1010EC BS616LV1010AI BS616LV1010EI OPERATING TEMPERATURE Commercial +0 O C to +70 O C Industrial -40 O C to +85 O C STANDBY (ICCSB1, Max) =50V =30V POWER DISSIPATION Operating (ICC, Max) =50V =30V 1MHz 10MHz f Max 1MHz 10MHz f Max 30uA 05uA 4mA 24mA 44mA 15mA 14mA 24mA 50uA 15uA 5mA 25mA 45mA 2mA 15mA 25mA PKG TYPE DI BGA TSOP II-44 BGA TSOP II-44 PIN CONFIGURATIONS BLOCK DIAGRAM A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 DQ3 VCC VSS DQ4 DQ5 DQ6 DQ7 WE A15 A14 A13 A12 A BS616LV1010EC BS616LV1010EI LB OE A0 A1 A2 A5 A6 A7 OE UB LB DQ15 DQ14 DQ13 DQ12 VSS VCC DQ11 DQ10 DQ9 DQ8 A8 A9 A10 A11 A8 A13 A15 A14 A12 A7 A6 A5 A4 DQ0 DQ15 Address Input Buffer Row Decoder Data Input Buffer Data Output Buffer Memory Array 512 x Column I/O Write Driver Sense Amp 128 Column Decoder B C D8 D9 UB D10 A3 A5 A4 A6 D1 D0 D2 WE OE UB LB Control 7 Address Input Buffer D VSS D11 A7 D3 VCC A11 A9 A3 A2 A1 A0 A10 VCC E VCC D12 D4 VSS VSS F D14 D13 A14 A15 D5 D6 G D15 A12 A13 WE D7 H A8 A9 A10 A11 48-ball BGA top view Brilliance Semiconductor, Inc reserves the right to change products and specifications without notice 1 Revision 26 May 2006

2 PIN DESCRIPTIONS Name A0-A15 Address Input Function These 16 address inputs select one of the 65,536 x 16-bit in the RAM Chip Enable Input WE Write Enable Input OE Output Enable Input LB and UB Data Byte Control Input is active LOW Chip enable must be active when data read form or write to the device If chip enable is not active, the device is deselected and is in standby power mode The DQ pins will be in the high impedance state when the device is deselected The write enable input is active LOW and controls read and write operations With the chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location The output enable input is active LOW If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled The DQ pins will be in the high impendence state when OE is inactive Lower byte and upper byte data input/output control pins DQ0-DQ15 Data Input/Output Ports There 16 bi-directional ports are used to read data from or write data into the RAM Power Supply V SS Ground TRUTH TABLE MODE WE OE LB UB IO0~IO7 IO8~IO15 CURRENT Chip De-selected (Power Down) H X X X X High Z High Z I CCSB, I CCSB1 X X X H H High Z High Z I CCSB, I CCSB1 Output Disabled L H H L X High Z High Z I CC L H H X L High Z High Z I CC L L D OUT D OUT I CC Read L H L H L High Z D OUT I CC L H D OUT High Z I CC L L D IN D IN I CC Write L L X H L X D IN I CC L H D IN X I CC NOTES: H means V IH; L means V IL; X means don t care (Must be V IH or V IL state) 2 Revision 26 May 2006

3 ABSOLUTE MAXIMUM RATINGS (1) SYMBOL PARAMETER RATING UNITS V TERM T BIAS Terminal Voltage with Respect to GND Temperature Under Bias -05 (2) to 70 V -40 to +125 O C OPERATING RANGE RANG AMBIENT TEMPERATURE Commercial 0 O C to + 70 O C 24V ~ 55V Industrial -40 O C to + 85 O C 24V ~ 55V T STG Storage Temperature -60 to +150 O C P T Power Dissipation 10 W I OUT DC Output Current 20 ma 1 Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect reliability 2 20V in case of AC pulse width less than 30 ns CAPACITAE (1) (T A = 25 O C, f = 10MHz) SYMBOL PAMAMETER CONDITIONS MAX UNITS C IN C IO Input Capacitance Input/Output Capacitance V IN = 0V 6 pf V I/O = 0V 8 pf 1 This parameter is guaranteed and not 100% tested DC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) PARAMETER NAME PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS Power Supply V V IL Input Low Voltage -05 (2) V V IH Input High Voltage (3) V I IL Input Leakage Current V IN = 0V to = V IH ua I LO Output Leakage Current V I/O = 0V to, = V IH or OE = V IH ua V OL Output Low Voltage = Max, I OL = 20mA V V OH Output High Voltage = Min, I OH = -10mA V I CC Operating Power Supply Current = V IL, (4) I IO = 0mA, f = F MAX VCC=30V 25 VCC=50V ma I CC1 Operating Power Supply Current = V IL, I IO = 0mA, f = 1MHz VCC=30V 2 VCC=50V ma I CCSB Standby Current TTL = V IH, I IO = 0mA VCC=30V 05 VCC=50V ma I CCSB1 (6) Standby Current CMOS -02V V IN -02V or V IN 02V VCC=30V VCC=50V ua 1 Typical characteristics are at T A=25 O C and not 100% tested 2 Undershoot: -10V in case of pulse width less than 20 ns 3 Overshoot: +10V in case of pulse width less than 20 ns 4 F MAX=1/t RC(MIN) 5 I CC (MAX) is 24mA/44mA at =30V/50V and T A=70 O C 6 I CCSB1(MAX) is 05uA/30uA at =30V/50V and T A=70 O C 3 Revision 26 May 2006

4 DATA RETENTION CHARACTERISTICS (T A = -40 O C to +85 O C) SYMBOL PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNITS V DR for Data Retention -02V VIN -02V or VIN 02V V I CCDR (3) Data Retention Current -02V VIN -02V or VIN 02V ua t CDR Chip Deselect to Data Retention Time See Retention Waveform ns t R Operation Recovery Time t RC (2) ns 1 =15V, T A=25 O C and not 100% tested 2 t RC = Read Cycle Time 3 I CCDR(Max) is 03uA at T A=70 O C LOW DATA RETENTION WAVEFORM ( Controlled) Data Retention Mode t CDR V DR 15V t R V IH - 02V V IH AC TEST CONDITIONS (Test Load and Input/Output Reference) KEY TO SWITCHING WAVEFORMS Input Pulse Levels Vcc / 0V WAVEFORM INPUTS OUTPUTS Input Rise and Fall Times Input and Output Timing Reference Level Output Output Load t CLZ, t OLZ, t CHZ, t OHZ, t WHZ Others 1 TTL C L (1) GND 1 Including jig and scope capacitance 10% 1V/ns 05Vcc C L = 5pF+1TTL C L = 30pF+1TTL ALL INPUT PULSES 90% Rise Time: 1V/ns 90% 10% Fall Time: 1V/ns MUST BE STEADY MAY CHANGE FROM H TO L MAY CHANGE FROM L TO H DON T CARE ANY CHANGE PERMITTED DOES NOT APPLY MUST BE STEADY WILL BE CHANGE FROM H TO L WILL BE CHANGE FROM L TO H CHANGE : STATE UNKNOW NTER LINE IS HIGH INPEDAE OFF STATE 4 Revision 26 May 2006

5 AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) READ CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns (=27~55V) CYCLE TIME : 70ns (=24~55V) MIN TYP MAX MIN TYP MAX UNITS t AVAX t RC Read Cycle Time ns t AVQX t AA Address Access Time ns t ELQV t ACS Chip Select Access Time () ns t BLQV t BA Data Byte Control Access Time (LB, UB) ns t GLQV t OE Output Enable to Output Valid ns t ELQX t CLZ Chip Select to Output Low Z () ns t BLQX t BE Data Byte Control to Output Low Z (LB, UB) ns t GLQX t OLZ Output Enable to Output Low Z ns t EHQZ t CHZ Chip Select to Output High Z () ns t BHQZ t BDO Data Byte Control to Output High Z (LB, UB) ns t GHQZ t OHZ Output Enable to Output High Z ns t AVQX t OH Data Hold from Address Change ns SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) t RC ADDRESS t OH t AA t OH D OUT 5 Revision 26 May 2006

6 READ CYCLE 2 (1,3,4) t ACS LB, UB D OUT t CLZ t BA t BE t BDO t CHZ READ CYCLE 3 (1, 4) t RC ADDRESS t AA OE t OE t OH t OLZ t CLZ t OHZ (1,5) t CHZ LB, UB t BA t BE t BDO D OUT NOTES: 1 WE is high in read Cycle 2 Device is continuously selected when = V IL 3 Address valid prior to or coincident with transition low 4 OE = V IL 5 Transition is measured ± 500mV from steady state with C L = 5pF The parameter is guaranteed but not 100% tested 6 Revision 26 May 2006

7 AC ELECTRICAL CHARACTERISTICS (T A = -40 O C to +85 O C) WRITE CYCLE JEDEC PARAMETER NAME PARANETER NAME DESCRIPTION CYCLE TIME : 55ns (=27~55V) CYCLE TIME : 70ns (=24~55V) MIN TYP MAX MIN TYP MAX UNITS t AVAX t WC Write Cycle Time ns t AVWL t AS Address Set up Time ns t AVWH t AW Address Valid to End of Write ns t ELWH t CW Chip Select to End of Write () ns t BLWH t BW Data Byte Control to End of Write (LB, UB) ns t WLWH t WP Write Pulse Width ns t WHAX t WR Write Recovery Time (, WE) ns t WLQZ t WHZ Write to Output High Z ns t DVWH t DW Data to Write Time Overlap ns t WHDX t DH Data Hold from Write Time ns t GHQZ t OHZ Output Disable to Output in High Z ns t WHQX t OW End of Write to Output Active ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) ADDRESS twc OE t WR1 (3) t CW (11) LB, UB t BW WE t AS t AW t WP (2) t WR2 (3) t OHZ (4,10) D OUT t DH t DW D IN 7 Revision 26 May 2006

8 WRITE CYCLE 2 (1,6) t WC ADDRESS t CW (11) LB, UB (12) t BW WE t AS t AW t WHZ (4,10) t WP (2) t WR2 (3) t OW (7) (8) D OUT t DW t DH (8,9) D IN NOTES: 1 WE must be high during address transitions 2 The internal write time of the memory is defined by the overlap of and WE low All signals must be active to initiate a write and any one signal can terminate a write by going inactive The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write 3 t WR is measured from the earlier of or WE going high at the end of write cycle 4 During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied 5 If the low transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state 6 OE is continuously low (OE = V IL) 7 D OUT is the same phase of write data of this write cycle 8 D OUT is the read data of next address 9 If is low during this period, DQ pins are in the output state Then the data input signals of opposite phase to the outputs must not be applied to them 10 Transition is measured ± 500mV from steady state with C L = 5pF The parameter is guaranteed but not 100% tested 11 t CW is measured from the later of going low to the end of write 12 The change of Read/Write cycle must accompany with or address toggled 8 Revision 26 May 2006

9 ORDERING INFORMATION BS616LV1010 X X Z Y Y SPEED 55: 55ns 70: 70ns PKG MATERIAL -: Normal G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE C: +0 o C ~ +70 o C I: -40 o C ~ +85 o C PACKAGE D: DI A: BGA E: TSOP II-44 Note: BSI (Brilliance Semiconductor Inc) assumes no responsibility for the application or use of any product or circuit described herein BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments PACKAGE DIMENSIONS TSOP II-44 9 Revision 26 May 2006

10 PACKAGE DIMENSIONS (continued) NOTES : 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS 12 Max BALL PITCH e = 075 D E N D1 E D1 E1 e VIEW A 48 mini-bga (6 x 8mm) 10 Revision 26 May 2006

11 Revision History Revision No History Draft Date Remark 25 Add Icc1 characteristic parameter Jan 13, Change I-grade operation temperature range May 25, from 25 O C to 40 O C 11 Revision 26 May 2006

Very Low Power CMOS SRAM 2M X 8 bit. Pb-Free and Green package materials are compliant to RoHS. STANDBY (ICCSB1, Max) V CC=3.0V

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