89LV Megabit (512K x 32-Bit) Low Voltage MCM SRAM 89LV1632 FEATURES: DESCRIPTION: Logic Diagram. 16 Megabit (512k x 32-bit) SRAM MCM

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89LV1632 16 Megabit (512K x 32Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32bit) SRAM MCM CS 14 Address OE, WE 89LV1632 Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM FEATURES: I/O 7 I/O 815

1 89LV Megabit (512K x 32Bit) Low Voltage MCM SRAM 16 Megabit (512k x 32bit) SRAM MCM CS 14 Address OE, WE 89LV1632 Power 4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM Ground MCM FEATURES: I/O 7 I/O 815 I/O 1623 I/O 2431 DESCRIPTION: Logic Diagram Four 512k x 8 SRAM die RADPAK Technology radiationhardend agait natural space radiation Total dose hardness: > 1 krad (Si), depending upon space mission Excellent Single Event Effects: SEL > 11MeVcm 2 /mg SEU threshold = 3 MeVcm 2 /mg SEU saturated cross section: 6E9 cm 2 /bit Package: 68pin quad flat package Completely static memory no clock or timing strobe required Fast Access Time:, 25, 3 Access Times Internal bypass capacitor Highspeed silicongate CMOS Technology 3.3 V ± 1% power supply Equal address and chip enable access times Threestate outputs All inputs and outputs are TTL compatible Maxwell Technologies 89LV1632 highperformance 16 Megabit MultiChip Module (MCM) Static Random Access features a greater than 1 krad(si) total dose tolerance, depending upon space mission. The four 4Megabit SRAM die and bypass capacitors are incorporated into a highreliable hermetic quad flatpack ceramic package. With highperformance silicongate CMOS technology, the 89LV1632 reduces power coumption and eliminates the need for external clocks or timing strobes. It is equipped with output enable (OE) and four byte chip enables (CS1 CS4) inputs to allow greater system flexibility. When OE input is high, the output is forced to high impedance. Maxwell Technologies' patented RADPAK packaging technology incorporates radiation shielding in the microcircuit package.it eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or a space mission. In a GEO orbit, RADPAK packaging provides greater than 1 krad(si) total radiation dose tolerance. This product is available with screening up to Maxwell Technologies selfdefined Class K Rev 4 1 (619) 5333 Fax: (619) Maxwell Technologies.

2 TABLE 1. PINOUT DESCRIPTION PIN SYMBOL DESCRIPTION 3428, 4236, 6264, 7, 8 AA18 Address Enable 65 WE WriteEnable 66 OE Output Enable 36 CS1 CS4 Chip Enable 4346, 4851,5356, 5861, I/OI/O31 Data Input/Output 912, 1417, 1922, , 67, 68 NC No Connection 1, 18, 35, 52 V CC +3.3V Power Supply 13, 23, 47, 57 V SS Ground TABLE 2. 89LV1632 ABSOLUTE MAXIMUM RATINGS (VOLTAGE REFERENCED TO V SS = V) PARAMETER SYMBOL MIN MAX UNITS Power Supply Voltage Relative to V SS V CC V Voltage Relative to V SS for Any Pin Except V CC V IN, V OUT.5 V CC +.5 V Weight 42 Grams Thermal Resistance TJC 3.6 C/W Power Dissipation P D 4. W Operating Temperature T A C Storage Temperature T S C TABLE 3. 89LV1632 RECOMMENDED OPERATING CONDITIONS = %, T A PARAMETER SYMBOL MIN MAX UNITS Supply Voltage, (Operating Voltage Range) V CC V Input High Voltage V IH 2.2 V CC +.5 (1) V Input Low Voltage V IL.5 (2).8 V 1. V IH (max) = V CC + 2V ac (pulse width < 1) for I < 8 ma. 2. V IL (min) = 2.V ac; (pulse width < 2 ) for I < 8 ma REV Maxwell Technologies.

3 TABLE 4. 89LV1632 DELTA LIMITS PARAMETER VARIATIONL I CC +1% of stated value in table 5 I SB +1% of stated value in table 5 I SB1 +1% of stated value in table 5 I LI +1% of stated value in table 5 TABLE 5. 89LV1632 DC ELECTRICAL CHARACTERISTICS = %, T A PARAMETER SYMBOL TEST CONDITIONS SUBGROUPS MIN TYP MAX UNITS Input Leakage Current I LI V IN = to V CC 1, 2, ua Output Leakage Current I LO CS = V IH, V OUT = V SS to V CC 1, 2, ua Operating Current : I CC Min. Cycle, 1% Duty, CS = V IL, I OUT = ma V IN = V IH or V IL Standby Power Supply Current I SB CS= V IH, Min Cycle 1, 2, 3 24 ma CMOS Standby Power Supply Current I SB1 CS > V CC.2V, f = MHz, V IN > V CC.2V or V IN <.2V 1, 2, ma 1, 2, 3 4 ma Output Low Voltage V OL I OL = + 8. ma 1, 2, 3.4 V Output High Voltage V OH I OH = 4. ma 1, 2, V Input Capacitance 1 CS1 CS4, OE, WE I/O7, I/O815, I/O1623, I/O2431 A A18 C IN V IN = V 4, 5, 6 Output Capacitance 1 C OUT V I/O = V 4, 5, 6 8 pf pf 1. Guaranteed by design. TABLE 6. 89LV1632 AC OPERATING CONDITIONS AND CHARACTERISTICS = %, T A PARAMETER MIN TYP MAX UNITS Input Pulse Level. 3. V REV Maxwell Technologies.

4 TABLE 6. 89LV1632 AC OPERATING CONDITIONS AND CHARACTERISTICS = %, T A PARAMETER MIN TYP MAX UNITS Output Timing Measurement Reference Level 1.5 V Input Rise/Fall Time 3. Input Timing Measurement Reference Level 1.5 V TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE = %, T A PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNITS Read Cycle Time t RC Address Access Time Chip Select Access Time t AA t CO Output Enable to Output Valid t OE Chip Enable to LowZ Output t OLZ Output Enable to LowZ Output t LZ Chip Enable Deselect to HighZ Output t OHZ Output Enable Deselect to HighZ Output t HZ REV Maxwell Technologies.

5 TABLE 7. 89LV1632 AC CHARACTORISTICS FOR READ CYCLE = %, T A PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNITS Output Hold from Address Change t OH Chip Select to Power Up Time T PU Chip Select to Power DownTime T PD TABLE 8. 89LV1632 FUNCTIONAL DESCRIPTION CS WE OE MODE I/O PIN SUPPLY CURRENT H X 1 X 1 Not Select HighZ I SB, I SB1 L H H Output Disable HighZ I CC 1. X = don t care. L H L Read D OUT I CC L L X 1 Write D IN I CC TABLE 9. 89LV1632 AC CHARACTORISTICS FOR WRITE CYCLE = %, T A PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNITS Write Cycle Time t WC Chip Select to End of Write t CW Address Setup Time t AS REV Maxwell Technologies.

6 TABLE 9. 89LV1632 AC CHARACTORISTICS FOR WRITE CYCLE = %, T A PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNITS Address Valid to End of Write t AW Write Pulse Width (OE High) t WP Write Pulse Width (OE Low) t WP Write Recovery Time Write to Output HighZ t WR t WHZ Data to Write Time Overlap t DW Data Hold from Write Time t DH End Write to Output LowZ t OW REV Maxwell Technologies.

7 FIGURE 1. AC TEST LOADS + 3.3V FIGURE 2. TIMING WAVEFORM OF READ CYCLE (1) (ADDRESS CONTROLLED) FIGURE 3. TIMING WAVEFORM OF READ CYCLE (2) (WE = V IH ) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first traition address REV Maxwell Technologies.

8 16 Megabit (512K x 32Bit)Low Voltage MCM SRAM 89LV t HZ and t OHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V OH or V OL levels. 4. At any given temperature and voltage conditio, t HZ (max) is less than t LZ (min) both for a given device and from device to device. 5. Traition is measured +2mV from steady state voltage with Load(B). This parameter is sampled and not 1% tested. 6. Device is continuously selected with CS = V IL. 7. Address valid prior to coincident with CS traition low. 8. For common I/O applicatio, minimization or elimination of bus contention conditio is necessary during read and write cycle. FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (1) (OE CLOCK) FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (2) (OE LOW FIIXED) REV Maxwell Technologies.

9 FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE (3) (CS CONTROLLED) 1. All write cycle timing is referenced from the last valid address to the first traition address. 2. A write occurs during the overlap of a low CS and WE. A write begi at the latest traition CS going low and WE going low. A write ends at the earliest traition CS going high or WE going high. t WP is measured from the beginning of write to the end of write. 3. t CW is measured from the later of CS going low to end of write. 4. t AS is measured from the address valid to the beginning of write. 5. t WR is measured from the end of write to the address change. t WR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pi are in the output lowz state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applicatio, minimization of elimination of bus contention conditio is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9. D OUT is the read data of the new address. 1.When CS is low, I/O pi are in the output state. The input signals in the opposite phase leading to the output should not be applied REV Maxwell Technologies.

10 16 Megabit (512K x 32Bit)Low Voltage MCM SRAM 89LV PIN RADPAK QUAD FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A b c D D1.8 e.5 BSC S1.339 F F L L L A N 68 Note: All dimeio in inches REV Maxwell Technologies.

11 16 Megabit (512K x 32Bit)Low Voltage MCM SRAM 89LV1632 Important Notice: These data sheets are created using the chip manufacturers published specificatio. Maxwell Technologies verifies functionality by testing key parameters either by 1% testing, sample testing or characterization. The specificatio presented within these data sheets represent the latest and most accurate information available to date. However, these specificatio are subject to change without notice and Maxwell Technologies assumes no respoibility for the use of this information. Maxwell Technologies products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim agait Maxwell Technologies must be made within 9 days from the date of shipment from Maxwell Technologies. Maxwell Technologies liability shall be limited to replacement of defective parts REV Maxwell Technologies.

12 Product Ordering Optio Model Number 89LV1632 RP Q X XX Feature Access Time Option Details 2 = 2 25 = 25 3 = 3 Screening Flow Multi Chip Module (MCM) 1 K = Maxwell SelfDefined Class K H = Maxwell SelfDefined Class H I = Industrial (testing at55 C, +25 C, +125 C) E = Engineering (testing at +25 C) Package Q = Quad Flat Pack Radiation Feature RP = RADPAK Package Base Product Nomenclature 16 Megabit (512K x 32Bit) MCM SRAM 1) Products are manufactured and screened to Maxwell Technologies selfdefined Class H and Class K flows REV Maxwell Technologies.

A13 A12 A11 A10 ROW DECODER DQ0 INPUT DATA CONTROL WE OE DESCRIPTION: DDC s 32C408B high-speed 4 Megabit SRAM

A13 A12 A11 A10 ROW DECODER DQ0 INPUT DATA CONTROL WE OE DESCRIPTION: DDC s 32C408B high-speed 4 Megabit SRAM 32C48B 4 Megabit (12K x 8-Bit) SRAM A13 A A1 A2 A3 A4 CS 1 36 NC A18 A17 A16 A1 OE A12 A11 A1 A9 A8 A7 A6 A A4 ROW DECODER MEMORY MATRIX 124 ROWS x 496 COLUMNS I/O1 I/O8 I/O2 Vcc Vss I/O3 32C48B I/O7 Vss