P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM

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Merry Hensley
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1 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial) 55 mw Active 5 (Commercial) 11 mw Standby (TTL Input) 55 mw Standby (CMOS Input) Single 5V ± 1% Power Supply Separate Input and Output Ports Three-State Outputs Fully TTL Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) 18 Pin 3 mil DIP 18 Pin CERPACK 18 Pin LCC (9 x 43 mils) 18 Pin LCC (95 x 335 mils) DESCRIPTION The P4C147 is a 4,96-bit ultra high speed static RAM organized as 4K x 1. The CMOS memory requires no clocks or refreshing, and have equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V ± 1% tolerance power supply. Access times as fast as 1 nanoseconds are available, permitting greatly enhanced system operating speeds. CMOS is utilized to reduce power coumption in both active and standby modes. In addition to very high performance, this device features latch-up protection and single-event-upset protection. The P4C147 is available in 18 pin 3 mil DIP packages, an 18-pin CERPACK package, and different LCC packages. FUNCTIONAL BLOCK DIAGRAM PIN CONFIGURATIONS DIP (P1, D1, C9), CERPACK (F1) SIMILAR LCC (L7, L7-1) 1 Revised October 5

2 MAXIMUM RATINGS (1) Symbol Parameter Value Unit V CC Power Supply Pin with.5 to +7 V Respect to GND Terminal Voltage with.5 to V TERM Respect to GND V CC +.5 V (up to 7.V) T A Operating Temperature 55 to +15 C Symbol Parameter Value Unit T BIAS Temperature Under 55 to +15 C Bias T STG Storage Temperature 65 to +15 C P T Power Dissipation 1. W I OUT DC Output Current 5 ma RECOMMENDED OPERATING CONDITIONS Grade () Commercial Military Ambient Temp C to 7 C -55 C to +15 C Gnd V V V CC 5.V ± 1% 5.V ± 1% CAPACITANCES (4) (V CC = 5.V, T A = 5 C, f = 1.MHz) Symbol Parameter Conditio Typ. Unit C IN Input Capacitance V IN = V 5 pf C OUT Output Capacitance V OUT = V 7 pf DC ELECTRICAL CHARACTERISTICS Over recommended operating temperature and supply voltage () Symbol Parameter Test Conditio P4C147 Min. Max. Unit V OH Output High Voltage (TTL Load) I OH = 4 ma, V CC = Min..4 V V OL Output Low Voltage (TTL Load) I OL = +8 ma, V CC = Min.4 V V IH Input High Voltage. V CC =+.5 V V IL Input Low Voltage.5 (3).8 V I LI Input Leakage Current V CC = Max., V IN = GND to V CC Mil. Comm l µa I LO I SB Output Leakage Current Standby Power Supply Current (TTL Input Levels) V CC = Max., CE = V IH, V OUT = GND to V CC CE V IH, V CC = Max., f=max., Output Open Mil. Comm l Mil. Comm l µa ma I SB1 Standby Power Supply Current (CMOS Input Levels) CE V HC, V CC = Max., f=, Output Open V IN.V or V IN V CC -.V Mil. Comm l 15 1 ma POWER DISSIPATION CHARACTERISTICS VS. SPEED Symbol Parameter Temperature Range Unit I CC Dynamic Operating Current Commercial Military 13 N/A 13 N/A N/A 1 ma ma Page of 1

3 AC CHARACTERISTICS READ CYCLE (V CC = 5V ± 1%, All Temperature Ranges) () Sym. Parameter Min Max Min Max Min Max Min Max Min Max Min Max Unit t RC Read Cycle Time t AA Address Access Time t AC Chip Enable Access Time t OH Output Hold from Address Change t LZ Chip Enable to Output in Low Z t HZ Chip Disable to Output in High Z t PU Chip Enable to Power Up Time t PD Chip Disable to Power Down Time TIMING WAVEFORM OF READ CYCLE NO. 1 (5) TIMING WAVEFORM OF READ CYCLE NO. (6) Notes: 1. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to MAXIMUM rating conditio for extended periods may affect reliability.. Extended temperature operation guaranteed with 4 linear feet per minute of air flow. 3. Traient inputs with V IL and I IL not more negative than 3.V and 1mA, respectively, are permissible for pulse widths up to. 4. This parameter is sampled and not 1% tested. 5. CE is LOW and WE is HIGH for READ cycle. 6. WE is HIGH, and address must be valid prior to or coincident with CE traition LOW. 7. Traition is measured ±mv from steady state voltage prior to change with specified loading in Figure 1. This parameter is sampled and not 1% tested. 8. Read Cycle Time is measured from the last valid address to the first traitioning address. Page 3 of 1

4 AC CHARACTERISTICS WRITE CYCLE Sym. Parameter Min Max Min Max Min Max Min Max Min Max Min Max (V CC = 5V ± 1%, All Temperature Ranges) () t WC Write Cycle Time t CW Chip Enable Time to End of Write t AW Address Valid to End of Write t AS Address Set-up Time t WP Write Pulse Width t Address Hold Time from AH End of Write t DW Data Valid to End of Write t DH Data Hold Time t WZ Write Enable to Output in High Z Output Active from End of Write t OW Unit TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (9) TIMING WAVEFORM OF WRITE CYCLE NO. (CE CONTROLLED) (9) Notes: 9. CE and WE must be LOW for WRITE cycle. 1. If CE goes HIGH simultaneously with WE high, the output remai in a high impedance state. 11. Write Cycle Time is measured from the last valid address to the first traition address. Page 4 of 1

5 AC TEST CONDITIONS Input Pulse Levels GND to 3.V Input Rise and Fall Times 3 Input Timing Reference Level 1.5V Output Timing Reference Level 1.5V Output Load See Figures 1 and TRUTH TABLE Mode CE WE Output Power Standby H X High Z Standby Read L H D OUT Active Write L L High Z Active Figure 1. Output Load * including scope and test fixture. Figure. Thevenin Equivalent Note: Due to the ultra-high speed of the P4C147, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A.1 µf high frequency capacitor is also required between V CC and ground. To avoid signal reflectio, proper termination must be used; for example, a 5Ω test environment should be terminated into a 5Ω load with 1.73V (Thevenin Voltage) at the comparator input, and a 116Ω resistor must be used in series with D OUT to match 166Ω (Thevenin Resistance). Page 5 of 1

6 ORDERING INFORMATION SELECTION GUIDE The P4C147 is available in the following temperature, speed and package optio. Temperature Range Commercial Temperature Military Temperature Military Processed* * Military temperature range with MIL-STD-883, Class B processing. N/A = Not Available Package Speed () Plastic DIP -1PC -1PC -15PC -PC -5PC N/A CERDIP N/A N/A -15DM -DM -5DM -35DM Side Brazed DIP N/A N/A -15CM -CM -5CM -35CM LCC (9 x 43 mil) N/A N/A -15LM -LM -5LM -35LM LCC (95 x 335 mil) N/A N/A -15LSM -LSM -5LSM -35LSM CERPACK N/A N/A -15FM -FM -5FM -35FM CERDIP N/A N/A -15DMB -DMB -5DMB -35DMB Side Brazed DIP N/A N/A -15CMB -CMB -5CMB -35CMB LCC (9 x 43 mil) N/A N/A -15LMB -LMB -5LMB -35LMB LCC (95 x 335 mil) N/A N/A -15LSMB -LSMB -5LSMB -35LSMB CERPACK N/A N/A -15FMB -FMB -5FMB -35FMB Page 6 of 1

7 # Pi C9 18 (3 Mil) Symbol Min Max A -. b.14.6 b.3.65 C.8.18 D -.96 E..3 ea e.3 BSC.1 BSC L.15. Q.15.7 S1.5 - S.5 - SIDE BRAZED DUAL IN-LINE PACKAGE # Pi D1 18 (3 Mil) Symbol Min Max A -. b.14.6 b C.8.18 D -.96 E..31 ea e.3 BSC.1 BSC L.15. Q.15.7 S1.5 - α 15 CERDIP DUAL IN-LINE PACKAGE Page 7 of 1

8 # Pi F1 18 Symbol Min Max A.45.9 b.15. c.4.9 D -.54 E e.5 BSC k.5.18 L.5.37 Q.6.45 S -.85 S1.5 - CERPACK CERAMIC FLAT PACKAGES # Pi L7 18 Symbol Min Max A.6.75 A B1..8 D.8.35 D1 D.15 BSC.75 BSC D E E1 E. BSC.1 BSC E e h j.5 BSC.4 REF. REF L L L ND NE 4 5 RECTANGULAR LEADLESS CHIP CARRIER Page 8 of 1

9 # Pi Symbol Min L Max A.6.75 A B1..8 D.8.35 D1 D.15 BSC.75 BSC D E E1 E. BSC.1 BSC E e h j.5 BSC.4 REF. REF L L L ND NE 4 5 RECTANGULAR LEADLESS CHIP CARRIER # Pi P1 18 Symbol Min Max A -.1 A b.14. b.45.7 C.8.14 D.88.9 E1.4.8 E.3.35 e.1 BSC eb -.43 L α 15 PLASTIC DUAL IN-LINE PACKAGE Page 9 of 1

10 REVISIONS DOCUMENT NUMBER: DOCUMENT TITLE: SRAM13 P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CHANGE DESCRIPTION OF CHANGE OR 1997 DAB New Data Sheet A Oct-5 JDB Change logo to Pyramid Page 1 of 1

P4C1257/P4C1257L. ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS. Separate Data I/O

P4C1257/P4C1257L. ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS. Separate Data I/O P4C1257/P4C1257L ULTRA HIGH SPEED 256K x 1 STATIC CMOS RAMS FEATURES Full CMOS High Speed (Equal Access and Cycle s) 12/15/20/25 ns (Commercial) 12/15/20/25 ns (Industrial) 25/35/45/55/70 ns (Military)