P4C150 ULTRA HIGH SPEED 1K X 4 RESETTABLE STATIC CMOS RAM

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Eric Harrison
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1 P4C5 UTRA IG SPEED K X 4 RESETTABE STATIC CMOS RAM FEATURES Full CMOS, 6T Cell igh Speed (Equal Access and Cycle Times) //5//5 (Commercial) 5//5/35 (Military) Chip Clear Function ow Power Operation Separate Input and Output Ports Three-State Outputs Fully TT Compatible Inputs and Outputs Standard Pinout (JEDEC Approved) 4-Pin 3 mil DIP 4-Pin 3 mil SOIC -Pin CC (35 x 55 mils) 4-Pin CERPACK Single 5V ± % Power Supply DESCRIPTION The P4C5 is a 4,96-bit ultra high-speed static RAM organized as K x 4 for high speed cache applicatio. The RAM features a reset control to enable clearing all words to zero within two cycle times. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs and outputs are fully TTcompatible. The RAM operates from a single 5V ± % tolerance power supply. Time required to reset is only for the SRAM. CMOS is used to reduce power coumption to a low level. The P4C5 is available in 4-pin 3 mil DIP and SOIC packages providing excellent board level deities. The device is also available in a -pin CC package as well as a 4-pin FATPACK for military applicatio. Access times as fast as nanoseconds are available permitting greatly enhanced system operating speeds. FUNCTIONA BOCK DIAGRAM PIN CONFIGURATIONS DIP (P4, C4, D4), SOIC (S4) CERPACK (F3) SIMIAR CC (5) Document # SRAM5 REV A Revised October 5

2 P4C5 MAXIMUM RATINGS () Symbol Parameter Value Unit V CC Power Supply Pin with.5 to +7 V Respect to GND Terminal Voltage with.5 to V TERM Respect to GND V CC +.5 V (up to 7.V) T A Operating Temperature 55 to +5 C Symbol Parameter Value Unit T BIAS Temperature Under 55 to +5 C Bias T STG Storage Temperature 65 to +5 C P T Power Dissipation. W I OUT DC Output Current 5 ma RECOMMENDED OPERATING CONDITIONS Grade () Commercial Military Ambient Temp C to 7 C -55 C to +5 C Gnd V V V CC 5.V ± % 5.V ± % CAPACITANCES (4) (V CC = 5.V, T A = 5 C, f =.Mz) Symbol Parameter Conditio Typ. Unit C IN Input Capacitance V IN = V 5 pf C OUT Output Capacitance V OUT = V 7 pf DC EECTRICA CARACTERISTICS Over recommended operating temperature and supply voltage () Symbol Parameter Test Conditio P4C5 Min. Max. Unit V O Output igh Voltage (TT oad) I O = 4 ma, V CC = Min..4 V V O Output ow Voltage (TT oad) I O = + ma, V CC = Min.4 V V I Input igh Voltage. V CC =+.5 V V I Input ow Voltage.5 (3). V I I Input eakage Current V CC = Max., V IN = GND to V CC 5 +5 µa I O Output eakage Current V CC = Max., CS = V I, V OUT = GND to V CC 5 +5 µa POWER DISSIPATION CARACTERISTICS VS. SPEED Symbol I CC Parameter Dynamic Operating Current Temperature Range Commercial Military N/A 3 N/A N/A Unit ma ma Notes:. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditio above those indicated in the operational sectio of this specification is not implied. Exposure to MAXIMUM rating conditio for extended periods may affect reliability.. Extended temperature operation guaranteed with 4 linear feet per minute of air flow. 3. Traient inputs with V I and I I not more negative than 3.V and ma, respectively, are permissible for pulse widths up to. 4. This parameter is sampled and not % tested. Document # SRAM5 REV A Page of

3 P4C5 AC CARACTERISTICS READ CYCE (V CC = 5V ± %, All Temperature Ranges) () Sym. t RC t AA t AC t O t Z t Z t OE t OZ t OZ Parameter Read Cycle Time Address Access Time Chip Select Access Time Output old from Address Change Chip Enable to Output in ow Z Chip Disable to Output in igh Z Output Enable to Data Valid Output Enable to Output in ow Z Output Disable to Output in igh Z Unit Min Max Min Max Min Max Min Max Min Max Min Max TIMING WAVEFORM OF READ CYCE NO. (5,6) TIMING WAVEFORM OF READ CYCE NO. (CS CONTROED) (5, 7) Notes: 5.WE is IG for READ cycle. 6.CS and OE are OW for READ cycle. 7.ADDRESS must be valid prior to, or concident with, CS traition OW, t AA must still be met.. Traition is measured ± mv from steady state voltage prior to change, with loading as specified in Figure. 9. Read Cycle Time is measured from the last valid address to the first traitioning address. Document # SRAM5 REV A Page 3 of

4 P4C5 TIMING WAVEFORM OF READ CYCE NO. 3 (OE OE Controlled) (5) AC CARACTERISTICS RESET CYCE (V CC = 5V ± %, All Temperature Ranges) () Symbol t RRC t WER t CR t RP t CR t WR t RZ t RZ Parameter Reset Cycle Time Write Enable igh to Beginning of Reset Chip Select ow to Beginning of Reset Reset Pulse Width Chip Select old after End of Reset Write Enable old after End of Reset Reset igh to Output in ow Z Reset ow to Output in igh Z Unit Min Max Min Max Min Max Min Max Min Max Min Max TIMING WAVEFORM OF RESET CYCE Document # SRAM5 REV A Page 4 of

5 P4C5 AC CARACTERISTICS WRITE CYCE Sym. (V CC = 5V ± %, All Temperature Ranges) () -35 Parameter - Min Max - Min Max -5 Min Max - Min Max -5 Min Max Min Max Unit t WC Write Cycle Time t CW Chip Enable Time to End of Write 3 5 t AW Address Valid to End of Write t AS Address Set-up Time t WP Write Pulse Width 3 5 t A t DW Address old Time from End of Write Data Valid to End of Write t D Data old Time t WZ Write Enable to Output in igh Z t OW Output Active from End of Write TIMING WAVEFORM OF WRITE CYCE NO. (WE CONTROED) () TIMING WAVEFORM OF WRITE CYCE NO. (CS CONTROED) () Notes:. CS and WE must be OW for WRITE cycle.. If CS goes IG simultaneously with WE high, the output remai in a high impedance state.. Write Cycle Time is measured from the last valid address to the first traition address. Document # SRAM5 REV A Page 5 of

6 P4C5 AC TEST CONDITIONS TRUT TABE Input Pulse evels GND to 3.V Mode RS CS OE WE Output Input Rise and Fall Times 3 Not Selected X X X igh Z Input Timing Reference evel.5v RESET X igh Z Output Timing Reference evel.5v Output Disabled igh Z Output oad See Figures and READ D OUT WRITE X igh Z Figure. Output oad Figure. Thevenin Equivalent * including scope and test fixture. Note: Due to the ultra-high speed of the P4C5, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. ong high-inductance leads that cause supply bounce must be avoided by bringing the V CC and ground planes directly up to the contactor fingers. A. µf high frequency capacitor is also required between V CC and ground. To avoid signal reflectio, proper termination must be used; for example, a 5Ω test environment should be terminated into a 5Ω load with.73v (Thevenin Voltage) at the comparator input, and a 6Ω resistor must be used in series with D OUT to match 66Ω (Thevenin Resistance). Document # SRAM5 REV A Page 6 of

7 P4C5 ORDERING INFORMATION SEECTION GUIDE The P4C5 is available in the following temperature, speed and package optio. Temperature Range Commercial Temperature Military Temperature Military Processed* * Military temperature range with MI-STD-3, Class B processing. N/A = Not Available Speed () Package Plastic DIP -PC -PC -5PC -PC -5PC N/A Plastic SOIC -SC -SC -5SC -SC -5SC N/A Side Brazed DIP N/A N/A -5CM -CM -5CM -35CM CERDIP N/A N/A -5DM -DM -5DM -35DM CERPACK N/A N/A -5FM -FM -5FM -35FM CC N/A N/A -5M -M -5M -35M Side Brazed DIP N/A N/A -5CMB -CMB -5CMB -35CMB CERDIP N/A N/A -5DMB -DMB -5DMB -35DMB CERPACK N/A N/A -5FMB -FMB -5FMB -35FMB CC N/A N/A -5MB -MB -5MB -35MB Document # SRAM5 REV A Page 7 of

8 P4C5 # Pi C4 4 (3 mil) A -. b.4.6 b C.. D -. E..3 ea e.3 BSC. BSC.5. Q.5.6 S.5 - S.5 - SIDE BRAZED DUA IN-INE PACKAGE # Pi D4 4 (3 mil) A -. b.4.6 b C.. D -. E..3 ea e.3 BSC. BSC.5. Q.5.6 S.5-5 α CERDIP DUA IN-INE PACKAGE Document # SRAM5 REV A Page of

9 P4C5 # Pi F3 4 A.6.9 b.5. c.4.9 D -.63 E.33.3 e.5 BSC k Q.6.45 S -.5 S.5 - CERPACK CERAMIC FAT PACKAGE # Pi 5 A.6.75 A.5.65 B.. D D D. BSC. BSC D E E E.4 BSC. BSC E e h j.5 BSC.4 REF. REF ND NE 5 9 RECTANGUAR EADESS CIP CARRIER Document # SRAM5 REV A Page 9 of

10 P4C5 # Pi P4 4 (3 Mil) A -. A.5 - b.4. b.45.7 C..4 D.3. E.4. E.3.35 e. BSC eb α 5 PASTIC DUA IN-INE PACKAGE # Pi S4 4 (3 Mil) A.93.4 A.4. b.3. C.9. D e.5 BSC E h α SOIC/SOP SMA OUTINE IC PACKAGE Document # SRAM5 REV A Page of

11 P4C5 REVISIONS DOCUMENT NUMBER: DOCUMENT TITE: SRAM5 P4C5 UTRA IG SPEED K x 4 RESETTABE STATIC CMOS RAM REV. ISSUE DATE ORIG. OF CANGE DESCRIPTION OF CANGE OR 997 DAB New Data Sheet A Oct-5 JDB Change logo to Pyramid Document # SRAM5 REV A Page of

P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM

P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial)