CMOS STATIC RAM 1 MEG (128K x 8-BIT)
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1 CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125 C) temperature options Equal access and cycle times Military: 15/17/20/25ns Industrial: 15/20ns Commercial: 12/15/17/20ns Two Chip Selects plus one Output Enable pin Bidirectional inputs and outputs directly TTL-compatible Low power consumption via chip deselect Available in 300 and 400 mil Plastic SOJ, and LCC packages Military product compliant to MIL-STD-3, Class B DESCRIPTION: The IDT71024 is a 1,04,576-bit high-speed static RAM organized as 12K x. It is fabricated using IDT s highperformance, high-reliability CMOS technology. This stateof-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71024 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ, 32-pin 400 mil Plastic SOJ, and 32-pin 400 x 20 mil LCC packages. FUNCTIONAL BLOCK DIAGRAM A0 DECODER 1,04,576-BIT MEMORY ARRAY A16 I/O0 I/O7 I/O CONTROL OE CONTROL LOGIC 2964 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. MAY Integrated Device Technology, Inc. DSC-2964/0 1
2 PIN CONFIGURATION NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A SO32-2 SO32-3 L A0 I/O I/O I/O GND VCC A15 A13 A A9 A11 OE A10 I/O7 I/O6 I/O5 I/O4 I/O drw 02 ABSOLUTE MAIMUM RATINGS (1) Symbol Rating Com l, Ind'l Mil. Unit VTERM (2) Terminal Voltage 0.5 to to +7.0 V Relative to GND TBIAS Temperature 55 to to +135 C Under Bias TSTG Storage 55 to to +150 C Temperature PT Power W Dissipation IOUT DC Output ma Current NOTES: 2964 tbl Stresses greater than those listed under ABSOLUTE MAIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. SOJ/LCC TOP VIEW TRUTH TABLE (1,2) INPUTS OE I/O FUNCTION H High-Z Deselected Standby (ISB) VHC (3) High-Z Deselected Standby (ISB1) L High-Z Deselected Standby (ISB) VLC (3) High-Z Deselected Standby (ISB1) H L H H High-Z Outputs Disabled H L H L DATAOUT Read Data L L H DATAIN Write Data NOTES: 2964 tbl H = VIH, L = VIL, = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE Grade Temperature GND VCC Commercial 0 C to +70 C 0V 5.0V ± 0.5V Industrial -40 C to +5 C 0V 5.0V ± 0.5V Military -55 C to +125 C 0V 5.0V ± 0.5V RECOMMENDED DC OPERATING CONDITIONS 2964 tbl 03 Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage V GND Supply Voltage V VIH Input High Voltage 2.2 Vcc+0.5 V VIL Input Low Voltage 0.5 (1) 0. V DC ELECTRICAL CHARACTERISTICS VCC = 5.0V ± 10% NOTE: 2964 tbl VIL (min.) = 1.5V for pulse width less than 10ns, once per cycle. IDT71024 Symbol Parameter Test Condition Min. Max. Unit ILI Input Leakage Current VCC = Max., VIN = GND to VCC 5 µa ILO Output Leakage Current VCC = Max., = VIH, = VIL, VOUT = GND to VCC 5 µa VOL Output LOW Voltage IOL = ma, VCC = Min. 0.4 V VOH Output HIGH Voltage IOH = 4mA, VCC = Min. 2.4 V 2964 tbl 05 2
3 DC ELECTRICAL CHARACTERISTICS (1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC 0.2V) 71024S S S S S25 Symbol Parameter Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Com'l. Mil. Unit ICC Dynamic Operating Current, VIH and ma VIH and VIL, Outputs Open, VCC = Max., f = fma (2) ISB Standby Power Supply Current (TTL Level) ma VIH or VIL, Outputs Open, VCC = Max., f = fma (2) ISB1 Full Standby Power Supply Current ma (CMOS Level) VHC, or VLC Outputs Open, VCC = Max., f = 0 (2), VIN VLC or VIN VHC NOTES: 2964 tbl All values are maximum guaranteed values. 2. fma = 1/tRC (all address inputs are cycling at fma); f = 0 means no address input lines are changing. DC ELECTRICAL CHARACTERISTICS (1) (VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC 0.2V) 71024S S20 Symbol Parameter Industrial Industrial Unit ICC Dynamic Operating Current, VIH and ma VIH and VIL, Outputs Open, VCC = Max., f = fma (2) ISB Standby Power Supply Current (TTL Level) ma VIH or VIL, Outputs Open, VCC = Max., f = fma (2) ISB1 Full Standby Power Supply Current ma (CMOS Level) VHC, or VLC Outputs Open, VCC = Max., f = 0 (2), VIN VLC or VIN VHC NOTES: 2964 tbl All values are maximum guaranteed values. 2. fma = 1/tRC (all address inputs are cycling at fma); f = 0 means no address input lines are changing. CAPACITANCE (TA = +25 C, f = 1.0MHz, SOJ package) Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 7 pf CI/O I/O Capacitance VOUT = 3dV pf NOTE: 2964 tbl 0 1. This parameter is guaranteed by device characterization, but is not production tested. 3
4 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and tbl 09 5V 5V 40Ω 40Ω DATAOUT DATAOUT 30pF 255Ω 5pF* 255Ω 2964 drw drw 04 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tclz, tolz, tchz, tohz, tow, and twhz) 4
5 AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges) 71024S12 (1) 71024S S17 (3) 71024S S25 (2) Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle trc Read Cycle Time ns taa Address Access Time ns tacs Chip Select Access Time ns tclz (4) Chip Select to Output in Low-Z ns tchz (4) Chip Deselect to Output in High-Z ns toe Output Enable to Output Valid ns tolz (4) Output Enable to Output in Low-Z ns tohz (4) Output Disable to Output in High-Z ns toh Output Hold from Address Change ns tpu (4) Chip Select to Power-Up Time ns tpd (4) Chip Deselect to Power-Down Time ns Write Cycle twc Write Cycle Time ns taw Address Valid to End-of-Write ns tcw Chip Select to End-of-Write ns tas Address Set-up Time ns twp Write Pulse Width ns twr Write Recovery Time ns tdw Data Valid to End-of-Write ns tdh Data Hold Time ns tow (4) Output Active from End-of-Write ns twhz (4) Write Enable to Output in High-Z ns NOTES: 2964 tbl C to +70 C temperature range only C to +125 C temperature range only C to +70 C and 55 C to +125 C temperature ranges only. 4. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 5
6 TIMING WAVEFORM OF READ CYCLE NO. 1 (1) t RC t AA OE t OE t (5) OLZ (3) t ACS DATA OUT (5) CLZ HIGH IMPEDANCE t DATA OUT t t (5) OHZ (5) CHZ VALID Vcc SUPPLY CURRENT Icc Isb t PU t PD 2964 drw 06 (1, 2, 4) TIMING WAVEFORM OF READ CYCLE NO. 2 trc toh taa toh DATAOUT PREVIOUS DATAOUT VALID DATAOUT VALID 2964 drw 07 NOTES: 1. is HIGH for Read Cycle. 2. Device is continuously selected, is LOW, is HIGH. 3. Address must be valid prior to or coincident with the later of transition LOW and transition HIGH; otherwise taa is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. 6
7 (1, 2, 5, 7) TIMING WAVEFORM OF WRITE CYCLE NO. 1 ( CONTROLLED TIMING) twc tcw taw tas (7) twp (3) twr (6) twhz (6) tow (6) tchz DATAOUT (4) HIGH IMPEDANCE tdw tdh (4) DATAIN DATAIN VALID 2964 drw 09 (1, 2, 5) TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( AND CONTROLLED TIMING) twc taw tas tcw twr (3) tdw tdh DATAIN DATAIN VALID 2964 drw 10 NOTES: 1. must be HIGH, must be HIGH, or must be LOW during all address transitions. 2. A write occurs during the overlap of a LOW, HIGH, and a LOW. 3. twr is measured from the earlier of either or going HIGH or going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the LOW transition or the HIGH transition occurs simultaneously with or after the LOW transition, the outputs remain in a high impedance state. and must both be active during the tcw write period. 6. Transition is measured ±200mV from steady state. 7. OE is continuously HIGH. During a controlled write cycle with OE LOW, twp must be greater than or equal to twhz + tdw to allow the I/O drivers to turn off and data to be placed on the bus for the required tdw. If OE is HIGH during a controlled write cycle, this requirement does not apply and the minimum write pulse is the specified twp. 7
8 ORDERING INFORMATION IDT S Device Type Power Speed Package Process/ Temperature Range Blank Commercial (0 C to +70 C) TY Y 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3) Speed in nanoseconds 2964 drw 11 IDT S Device Type Power Speed Package Process/ Temperature Range I Industrial ( 40 C to +5 C) Y 400-mil SOJ (SO32-3) Speed in nanoseconds 2964 drw 12 IDT S Device Type Power Speed Package Process/ Temperature Range B Military ( 55 C to +125 C) Compliant to MIL-STD-3, Class B L 400 x 20 mil LCC package (L32-2) Speed in nanoseconds 2964 drw 13
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64K x 16 HIGH-SPEED CMOS STATIC RAM OCTOBER 2006 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
DESCRIPTION DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
28K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY JUNE 2005 FEATURES High-speed access time: 8, 0 ns CMOS low power operation 756 mw (max.) operating @ 8 ns 36 mw (max.) standby @ 8 ns TTL compatible
IS62WV20488ALL IS62WV20488BLL
2M x 8 HIGH-SPEED LOW POWER CMOS STATIC RAM August 2016 FEATURES High-speed access times: 25, 35 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater noise immunity
IS61WV102416ALL IS61WV102416BLL IS64WV102416BLL
1M x 16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY MAY 2012 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for
Document Title. Revision History. 256Kx16 bit Low Power and Low Voltage CMOS Static RAM. Draft Date. Revision No. History. Remark.
Document Title 256Kx16 bit Low Power and Low Voltage CMOS Static RAM Revision History Revision No History Draft Date Remark 0.0 Initial draft July 29, 2002 Preliminary 0.1 Revised - Added Commercial product
IS61WV10248EDBLL IS64WV10248EDBLL
1M x 8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH ECC FEBRUARY 2013 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center power and ground pins for greater
IS62C10248AL IS65C10248AL
IS62C10248AL IS65C10248AL 1M x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM Long-term Support NOVEMBER 2016 FEATURES High-speed access time: 45ns, 55ns, 70ns CMOS low power operation 36 mw (typical)
IS62WV2568ALL IS62WV2568BLL
IS62WV2568ALL IS62WV2568BLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM DECEMBER 2008 FEATURES High-speed access time: 55ns, 70ns CMOS low power operation 36 mw (typical) operating 9 µw (typical)
IS64WV3216BLL IS61WV3216BLL
32K x 16 HIGH-SPEED CMOS STATIC RAM NOVEMBER 2005 FEATURES High-speed access time: 12 ns: 3.3V + 10% 15 ns: 2.5V-3.6V CMOS low power operation: 50 mw (typical) operating 25 µw (typical) standby TTL compatible
IS61/64WV5128EFALL IS61/64WV5128EFBLL. 512Kx8 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
512Kx8 HIGH SPEED AYHRONOUS CMOS STATIC RAM with ECC APRIL 2018 KEY FEATURES A0 A17 A18 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV5128EFALL) 2.4V-3.6V () Error Detection
Document Title. Revision History. 32Kx8 bit Low Power CMOS Static RAM. Remark. History. Revision No. Draft Data. Design target. Initial draft 0.
Document Title 32Kx8 bit Low Power CMOS Static RAM Revision History Revision No History Draft Data Remark 0.0 Initial draft May 18, 1997 Design target 0.1 First revision - KM62256DL/DLI ISB1 = 100 50µA
CMOS SRAM. KM684000B Family. Document Title. Revision History. 512Kx8 bit Low Power CMOS Static RAM. Revision No. History. Remark. Draft Date 0.
Document Title 512Kx8 bit Low Power CMOS Static RAM Revision History Revision No. History Draft Date Remark 0.0 Initial Draft December 7, 1996 Advance 0.1 Revise - Changed Operating current by reticle
IS62/65WV2568DALL IS62/65WV2568DBLL
IS62/65WV2568DALL IS62/65WV2568DBLL 256K x 8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2013 FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation 36 mw (typical) operating
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS IS64WV3216DBLL/DBLS
IS61WV3216DALL/DALS IS61WV3216DBLL/DBLS 32K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM MAY 2012 FEATURES HIGH SPEED: (IS61/64WV3216DALL/DBLL) High-speed access time: 8, 10, 12, 20 ns Low Active Power:
IS61WV6416DALL/DALS IS61WV6416DBLL/DBLS IS64WV6416DBLL/DBLS
ISWVDALL/DALS ISWVDBLL/DBLS K x HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM JANUARY 0 FEATURES HIGH SPEED: (IS/WVDALL/DBLL) High-speed access time:, 0,, 0 ns Low Active Power: mw (typical) Low Standby Power:
IS62C51216AL IS65C51216AL
IS62C51216AL IS65C51216AL 512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating 12 µw (typical) CMOS standby
IS61WV20488FALL IS61/64WV20488FBLL. 2Mx8 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
2Mx8 HIGH-SPEED ASYHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
IS62WV20488FALL/BLL IS65WV20488FALL/BLL. 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM NOVEMBER 2018
/BLL IS65WV20488FALL/BLL 2Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current:
IS62WV5128EALL/EBLL/ECLL IS65WV5128EBLL/ECLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2017
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 35ns, 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 3.7uA (typ)
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR IDT7210L Integrated Device Technology, Inc. FEATURES: 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction High-speed: 20ns
IS61WV102416FALL IS61/64WV102416FBLL. 1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY FUNCTIONAL BLOCK DIAGRAM
1Mx16 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V/1.8V SUPPLY PRELIMINARY INFORMATION DECEMBER 2016 FEATURES High-speed access time: 8ns, 10ns, 20ns High- performance, low power CMOS process Multiple
FAST CMOS OCTAL BUFFER/LINE DRIVER
Integrated Device Technology, Inc. FAST CMOS OCTAL BUFFER/LINE DRIVER IDT4/4FCT240/A/C IDT4/4FCT241/A/C IDT4/4FCT244/A/C IDT4/4FCT40/A/C IDT4/4FCT41/A/C FEATURES: IDT4/4FCT240/241/244/40/41 equivalent
Very Low Power/Voltage CMOS SRAM 1M X 16 bit DESCRIPTION. SPEED (ns) 55ns : 3.0~3.6V 70ns : 2.7~3.6V BLOCK DIAGRAM
Very Low Power/Voltage CMOS SRAM 1M X 16 bit (Dual CE Pins) FEATURES operation voltage : 27~36V Very low power consumption : = 30V C-grade: 45mA (@55ns) operating current I -grade: 46mA (@55ns) operating
IS61/64WV25616FALL IS61/64WV25616FBLL. 256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES DESCRIPTION
256Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM APRIL 2018 KEY FEATURES High-speed access time: 8, 10ns, 12ns Low Active Current: 35mA (Max., 10ns, I-temp) Low Standby Current: 10 ma (Max., I-temp) Single
IS62WV6416ALL IS62WV6416BLL
IS62WV6416ALL IS62WV6416BLL 64K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JANUARY 2008 FEATURES High-speed access time: 45ns, 55ns CMOS low power operation: 30 mw (typical) operating 15 µw (typical)
FUNCTIONAL BLOCK DIAGRAM
128Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 26mA (max) at 125 C CMOS Standby Current: 3.0
IS61WV25632ALL/ALS IS61WV25632BLL/BLS IS64WV25632BLL/BLS
256K x 32 HIGH-SPEED ASYNCHRONOUS CMOS STATIC RAM WITH 3.3V SUPPLY PRELIMINARY INFORMATION APRIL 2008 FEATURES High-speed access times: 8, 10, 20 ns High-performance, low-power CMOS process Multiple center
Distributed by: www.jameco.com 1-00-31-4242 The content and copyrights of the attached material are the property of its owner. FEATURES Wide operation voltage : 2.4V ~ 5.5V Very low power consumption :
FAST CMOS 1-TO-10 CLOCK DRIVER
Integrated Device Technology, Inc. FAST CMOS 1-TO-10 CLOCK DRIVER IDT54/74FCT807BT/CT FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 250ps (max.) Very low duty cycle distortion < 350ps (max.)
IS62C25616EL, IS65C25616EL
256Kx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM AUGUST 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 22 ma (max) at 85 C CMOS Standby Current: 5.0uA
Very Low Power/Voltage CMOS SRAM 512K X 16 bit DESCRIPTION. SPEED ( ns ) STANDBY. ( ICCSB1, Max ) 55ns : 3.0~5.5V 70ns : 2.7~5.5V
FEATURES Wide operation voltage : 24~55V Very low power consumption : = 30V C-grade: 30mA (@55ns) operating current I -grade: 31mA (@55ns) operating current C-grade: 24mA (@70ns) operating current I -grade:
HIGH-SPEED 128K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
HIGH-SPEED 8K x 9 SYHRONOUS PIPELINED DUAL-PORT STATIC RAM IDT70999L Features True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial:
IS66WV51216DALL IS66/67WV51216DBLL
8Mb LOW VOLTAGE, ULTRA LOW POWER PSEUDO CMOS STATIC RAM FEATURES High-speed access time: 70ns (IS66WV51216DALL, ) 55ns () CMOS low power operation Single power supply Vdd = 1.7V-1.95V (IS66WV51216DALL)
IS62WV25616DALL/DBLL, IS65WV25616DBLL 256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM
256K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC SRAM FEATURES High-speed access time: 35, 45, 55 ns CMOS low power operation 30 mw (typical) operating 6 µw (typical) CMOS standby TTL compatible interface
IS61/64WV12816EFALL IS61/64WV12816EFBLL. 128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC FUNCTIONAL BLOCK DIAGRAM APRIL 2018 KEY FEATURES
128Kx16 HIGH SPEED AYNCHRONOUS CMOS STATIC RAM with ECC KEY FEATURES A0 A17 A16 High-speed access time: 8ns, 10ns, 12ns Single power supply 1.65V-2.2V (IS61/64WV12816EFALL) 2.4V-3.6V () Error Detection
IS62WV5128EHALL/BLL IS65WV5128EHALL/BLL. 512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM JULY 2018 DESCRIPTION
512Kx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 25 ma (max.) CMOS Standby Current: 3.2 ua (typ., 25 C) TTL
IS62WV102416FALL/BLL IS65WV102416FALL/BLL. 1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM FUNCTIONAL BLOCK DIAGRAM MARCH 2018
1Mx16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM MARCH 2018 KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation Operating Current: 35mA (max.) CMOS standby Current: 5.5uA (typ.)