HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
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1 Integrated Device Technology, Inc. HIGH-PERFORMAE CMOS BUS TRANSCEIVERS IDT54/74FCT86A/B IDT54/74FCT863A/B FEATURES: Equivalent to AMD s Am bipolar registers in pinout/function, speed and output drive over full temperature and voltage supply extremes IDT54/74FCT86A/863A equivalent to FAST speed IDT54/74FCT86B/863B 25% faster than FAST High-speed symmetrical bidirectional transceivers IOL = 48mA (commercial) and 32mA (military) Clamp diodes on all inputs for ringing suppression CMOS power levels (mw typ. static) TTL input and output level compatible CMOS output level compatible Substantially lower input current levels than AMD s bipolar Am29800 Series (5µA max.) Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B DESCRIPTION: The IDT54/74FCT800 series is built using an advanced dual metal CMOS technology. The IDT54/74FCT860 series bus transceivers provide high-performance bus interface buffering for wide data/address paths or buses carrying parity. The IDT54/74FCT863 9-bit transceivers have NAND-ed output enables for maximum control flexibility. All of the IDT54/74FCT800 high-performance interface family are designed for high-capacitance load drive capability while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high- impedance state. FUTIONAL BLOCK DIAGRAMS IDT54/74FCT86 T0 T OER -T9 IDT54/74FCT863 T0 T -T8 OER OER2 R0 R- R9 OET R0 R- R8 OET OET2 260 drw 0 PRODUCT SELECTOR GUIDE 0-Bit Device The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor Co. 9-Bit Non-inverting IDT54/74FCT86 IDT54/74FCT863 APRIL Integrated Device Technology, Inc DSC-4620/3
2 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS PIN CONFIGURATIONS IDT54/74FCT86 0-BIT TRANSCEIVERS INDEX R R0 OER Vcc T0 T OER R0 R R2 R3 R4 R5 R6 R7 R8 R9 GND P24-, D24-, E24- & SO Vcc T0 T T2 T 3 T4 T5 T6 T7 T8 T9 OET R2 R3 R4 R5 R6 R L R8 R9 GND OET T9 T8 T2 T3 T4 T5 T6 T7 DIP/CERPACK/SOIC TOP VIEW LCC TOP VIEW IDT54/74FCT863 9-BIT TRANSCEIVERS INDEX R R0 OER Vcc T0 T OER R0 R Vcc T0 T R2 4 P24-, 2 T2 R3 5 D24-, 20 T 3 E24- R4 6 9 & T4 R5 7 SO T5 R6 R T6 T7 R8 0 5 T8 OER 2 4 OET 2 GND 2 3 OET R2 R3 R4 R5 R6 R L R8 OER 2 GND OET OET 2 T8 T2 T3 T4 T5 T6 T7 260 drw 02 DIP/CERPACK/SOIC TOP VIEW LCC TOP VIEW LOGIC SYMBOLS IDT54/74FCT86 IDT54/74FCT863 OET OET OET2 R 0 0 T R 9 9 T OER OER OER2 260 drw
3 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS PIN DESCRIPTION Name I/O Description IDT54/74FCT86 OER I When LOW in conjunction with OET HIGH activates the RECEIVE mode. OET I When LOW in conjunction with OER HIGH activates the TRANSMIT mode. RI I/O 0-bit RECEIVE input/output. TI I/O 0-bit TRANSMIT input/output. IDT54/74FCT863 OERI I When LOW in conjunction with OETI HIGH activates the RECEIVE mode. OETI I When LOW in conjunction with OERI HIGH activates the TRANSMIT mode. RI I/O 9-bit RECEIVE input/output. TI I/O 9-bit TRANSMIT input/output. FUTION TABLE () IDT54/74FCT86/863 (Non-inverting) OET Inputs Outputs OER RI TI RI TI Function L H L N/A N/A L Transmitting L H H N/A N/A H Transmitting H L N/A L L N/A Receiving H L N/A H H N/A Receiving H H X X Z Z High Z NOTE: 260 tbl 02. H = HIGH, L = LOW, Z = High Impedance, X = Don t Care, N/A = Not Applicable. 260 tbl 0 ABSOLUTE MAXIMUM RATINGS () Symbol Rating Commercial Military Unit VTERM (2) Terminal Voltage 0.5 to to +7.0 V with Respect to GND VTERM (3) Terminal Voltage 0.5 to VCC 0.5 to VCC V with Respect to GND TA Operating 0 to to +25 C Temperature TBIAS Temperature 55 to to +35 C Under Bias TSTG Storage 55 to to +50 C Temperature PT Power Dissipation W IOUT DC Output Current ma CAPACITAE (TA = +25 C, f =.0MHz) Symbol Parameter () Conditions Typ. Max. Unit CIN Input Capacitance VIN = 6 0 pf CI/O I/O Capacitance VOUT = 8 2 pf NOTE: 260 tbl 04. This parameter is guaranteed by characterization but not tested. NOTES: 260 tbl 03. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Inputs and VCC terminals only. 3. Outputs and I/O terminals only
4 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V, VHC = VCC 0.2V Commercial: TA = 0 C to +70 C, VCC = 5. ± 5%; Military: TA = 55 C to +25 C, VCC = 5. ± 0% Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2.0 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V IIH Input HIGH Current VCC = Max. VI = VCC 5 µa (Except I/O pins) VI = 2.7V 5 (4) IIL Input LOW Current VI = 0.5V 5 (4) µa (Except I/O pins) VI = GND 5 IIH Input HIGH Current VCC = Max. VI = VCC 5 (I/O pins Only) VI = 2.7V 5 (4) IIL Input LOW Current VI = 0.5V 5 (4) (I/O pins Only) VI = GND 5 VIK Clamp Diode Voltage VCC = Min., IN = 8mA V IOS Short Circuit Current VCC = Max. (3), VO = GND ma VOH Output HIGH Voltage VCC =, VIN = VLC or VHC, IOH = 32µA VHC VCC V VCC = Min. IOH = 300µA VHC VCC VIN = VIH or VIL IOH = 5mA MIL IOH = 24mA COM L VOL Output LOW Voltage VCC =, VIN = VLC or VHC, IOL = 300µA GND VLC V VCC = Min. IOL = 300µA GND VLC (4) VIN = VIH or VIL IOL = 32mA MIL. (5) IOL = 48mA COM L. (5) NOTES: 260 tbl 05. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient and maximum loading. 3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second. 4. This parameter is guaranteed but not tested. 5. These are maximum IOL values per output, for 0 outputs turned on simultaneously. Total maximum IOL (all outputs) is 480mA for commercial and 320mA for military. Derate IOL for number of outputs exceeding 0 turned on simultaneously
5 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS POWER SUPPLY CHARACTERISTICS VLC = 0.2V; VHC = VCC 0.2V Symbol Parameter Test Conditions () Min. Typ. (2) Max. Unit ICC Quiescent Power VCC = Max ma Supply Current VIN VHC ; VIN VLC ICC Quiescent Power Supply VCC = Max ma Current TTL Inputs HIGH VIN = 3.4V (3) ICCD Dynamic Power Supply Current (4) VCC = Max., Outputs Open VIN VHC ma/ OER or OET = GND VIN VLC MHz One Input Toggling 50% Duty Cycle IC Total Power Supply Current (6) VCC = Max., Outputs Open VIN VHC ma fi = 0MHz VIN VLC 50% Duty Cycle (FCT) OER or OET = GND VIN = 3.4V One Bit Toggling VIN = GND VCC = Max., Outputs Open VIN VHC (5) fi = 2.5MHz VIN VLC 50% Duty Cycle (FCT) OER or OET = GND VIN = 3.4V (5) Eight Bits Toggling VIN = GND NOTES: 260 tbl 06. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5., +25 C ambient. 3. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. 5. Values for these conditions are examples of the ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT +IINPUTS + IDYNAMIC IC = ICC + ICCDHNT + ICCD(fCP/2 + fini) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fcp = Clock Frequency for Register Devices (Zero for Non-Register Devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz
6 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS SWITCHING CHARACTERISTICS OVER OPERATING RANGE FCT86A/863A FCT86B/863B Com'l. Mil. Com'l. Mil. Symbol Parameter Condition () Min. (2) Max. Min. (2) Max. Min. (2) Max. Min. (2) Max. Unit tplh Propagation Delay CL = 50pF ns tphl RI to TI or TI to RI FCT86/863 CL = 300pF (3) tpzh Output Enable Time CL = 50pF ns tpzl OET to TI or OER to RI CL = 300pF (3) tphz tplz Output Disable Time OET to TI or OER to RI CL = 5pF (3) CL = 50pF ns NOTES: 260 tbl 07. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. This condition guaranteed but not tested
7 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS TEST CIRCUITS AND WAVEFORMS TEST CIRCUITS FOR ALL OUTPUTS Pulse Generator VIN R T VCC D.U.T. VOUT 50pF C L 500Ω 500Ω 7. SWITCH POSITION Test Open Drain Disable Low Enable Low All Other Tests Switch Closed Open DEFINITIONS: 260 tbl 08 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. SET-UP, HOLD AND RELEASE TIMES PULSE WIDTH DATA INPUT TIMING INPUT ASYHRONOUS CONTROL PRESET CLEAR ETC. SYHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC. tsu tsu trem th th LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw PROPAGATION DELAY ENABLE AND DISABLE TIMES SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh tphl tphl VOH VOL CONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITCH CLOSED tpzh SWITCH OPEN 3.5V tphz DISABLE tplz V VOL VOH 260 drw 03 NOTES:. Diagram shown for input Control Enable-LOW and input Control Disable- HIGH 2. Pulse Generator for All Pulses: Rate.0MHz; tf 2.5ns; tr 2.5ns
8 HIGH-PERFORMAE CMOS BUS TRANSCEIVERS ORDERING INFORMATION IDT XX FCT XXXX X X Temperature Range Device Type Package Process Blank B Commercial MIL-STD-883, Class B P D E L SO 86A 863A 86B 863B Plastic DIP CERDIP CERPACK Leadless Chip Carrier Small Outline IC 0-Bit Non-inverting Transceiver 9-Bit Non-inverting Transceiver -55 C to +25 C 0 to +70 C 260 drw
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Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and CMOS-Compatible Outputs Distributes One Clock Input to Eight Outputs Four Same-Frequency
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
MC3487 QUADRUPLE DIFFERENTIAL LINE DRIVER
Meets or Exceeds Requirements of ANSI EIA/TIA-422-B and ITU Recommendation V. -State, TTL-Compatible s Fast Transition Times High-Impedance Inputs Single -V Supply Power-Up and Power-Down Protection Designed
description V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
SN54ALS74A, SN54AS74A, SN74ALS74A, SN74AS74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE)
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (WITH 3-STATE) PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES SEPTEMBER 7, 2016 FEATURES: 0.5 MICRON CMOS Technology Input frequency range: 10MHz f2q Max.
PI74LPT V, 16-Bit Buffer/Line Driver. Features. Description. Block Diagram
Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to 5V bus Advanced Low Power CMOS Operation
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
SN54LS373, SN54LS374, SN54S373, SN54S374, SN74LS373, SN74LS374, SN74S373, SN74S374 OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SN54LS373, SN54LS374, SN54S373, SN54S374, Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package 3-State Bus-Driving s Full Parallel Access for Loading Buffered Control s Clock-Enable Has
MC3486 QUADRUPLE DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS
Meets or Exceeds the Requirements of ANSI Standards EIA/TIA-422-B and EIA/TIA-423-B and ITU Recommendations V.10 and V.11 3-State, TTL-Compatible s Fast Transition Times Operates From Single 5-V Supply
SN54HC573A, SN74HC573A OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS147B DECEMBER 1982 REVISED MAY 1997
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Bus-Structured Pinout Package Options Include Plastic Small-Outline (DW) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and
SN54ALS688, SN74ALS688 8-BIT IDENTITY COMPARATORS
Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
SN54HC245, SN74HC245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines Directly or up to LSTTL Loads Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages,
PI74LPT244. Fast CMOS 3.3V 8-Bit Buffer/Line Driver. Features. Description. Block Diagram. Pin Configuration
Fast CMOS 3.3V 8-Bit Buffer/Line Driver Features Compatible with LCX and LVT families of products Supports 5V Tolerant Mixed Signal Mode Operation Input can be 3V or 5V Output can be 3V or connected to
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
PO54G14A, PO74G14A. Pin Configuration. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: V CC 6A 6Y 5A 5Y 4A 4Y 1A 1Y 2A 2Y 3A 3Y GND
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 680MHz with 5pf load. Operating frequency up to 300MHz with 15pf load. Operating frequency up
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCLS140B DECEMBER 1982 REVISED MAY 1997
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
500MHz TTL/CMOS Potato Chip
FEATURES:. Patent pending technology. Max input frequency > 1GHz. Operating frequency up to 500MHz with 2pf load. Operating frequency up to 450MHz with 5pf load. Operating frequency up to 300MHz with 15pf
SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
QUICKSWITCH BASICS AND APPLICATIONS
QUICKSWITCH GENERAL INFORMATION QUICKSWITCH BASICS AND APPLICATIONS INTRODUCTION The QuickSwitch family of FET switches was pioneered in 1990 to offer designers products for high-speed bus connection and
54AC11241, 74AC11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS
SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
IDT71V424S/YS/VS IDT71V424L/YL/VL
.V CMOS Static RAM Meg (K x -Bit) IDT1V2S/YS/VS IDT1V2L/YL/VL Features K x advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise Equal access and cycle times Commercial
SN54ALS86, SN54AS86A, SN74ALS86, SN74AS86A QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input exclusive-or
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER
QUICKSWITCH PRODUCTS HIGH-SPEED CMOS QUICKSWITCH 16:8 MULTIPLEXER IDTQS32390 FEATURES: Enhanced N channel FET with no inherent diode to Vcc 16:8 multiplexer function with zero delay 5Ω bidirectional switches
QUICKSWITCH PRODUCTS HIGH-SPEED 32-BIT BUS EXCHANGE SWITCH IN MILLIPAQ
QUICKSWITCH PRODUCTS HIGH-SPEED 3-BIT BUS EXCHANGE SWITCH IN MILLIPAQ IDTQS3X33 FEATURES: 5Ω switches connect inputs to outputs Zero propagation delay Direct bus connect Live insertion capability Low power
PO74G16240A. Pin Configuration. Logic Block Diagram. Truth Table. 74 Series Noise Cancellation GHz Logic DESCRIPTION: FEATURES:
FEATURES:. Patented technology. Operating frequency up to.25ghz with 2pf load. Operating frequency up to 700MHz with 5pf load. Operating frequency up to 300MHz with 5pf load. Operating frequency up to
SN54ALS563B, SN74ALS563B OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS
-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
SN54HC175, SN74HC175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
Contain Four Flip-Flops With Double-Rail Outputs Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic Small-Outline (D), Thin Shrink Small-Outline
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) Description OBSOLESCENCE ORDER 71V016SA. Row / Column Decoders. Sense Amps and Write Drivers
3.3V CMOS Static RAM 1 Meg (4K x 1-Bit) IDT71V1 Features 4K x 1 advanced high-speed CMOS Static RAM Commercial ( to +7 C) and Industrial ( 4 C to +5 C) Equal access and cycle times Commercial and Industrial:
SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
AM26LS31 QUADRUPLE DIFFERENTIAL LINE DRIVER
AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
PI3C V/3.3V, High Bandwidth, Hot Insertion 10-Bit, 2-Port, Bus Switch
2.5V/3., High Bandwidth, Hot Insertion Features Near-Zero propagation delay 5-ohm switches connect inputs to outputs High Bandwidth (>400 MHz) Permits Hot Insertion. Rail-to-Rail, 3. or 2.5V ing 5V I/O
74AC11373 OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
SN54HCT373, SN74HCT373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Inputs Are TTL-Voltage Compatible Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Optio Include Plastic Small-Outline
PRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
SN54ACT241, SN74ACT241 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR
WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
CD74HCT4514, CD74HCT LINE TO 16-LINE DECODERS/DEMULTIPLEXERS WITH INPUT LATCHES
4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
SN75158 DUAL DIFFERENTIAL LINE DRIVER
SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
SN74ALVCH V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
PO74G139A. Pin Configuration. Logic Block Diagram. Pin Description. 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION:
FEATURES:. Patented technology. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 800MHz with 5pf load. Operating frequency up to 350MHz with 15pf load. VCC Operates from 1.65V
PO54G374A, PO74G374A
OCTAL EDGETRIGGERED DTYPE FLIPFLOP WITH 3STATE OUTPUTS FEATURES:. Patented technology. Specified From 40 C to 85 C, 40 C to 25 C, and 55 C to 25 C. Operating frequency is faster than 600MHz. VCC Operates
PO54G00A, PO74G00A. Pin Configuration. Pin Description. Logic Block Diagram. 54, 74 Series Noise Cancellation GHz Logic FEATURES: DESCRIPTION: V CC 1B
FEATURES:. Patented technology. Specified From 40 C to 85 C, 40 C to 125 C, and 55 C to 125 C. Operating frequency up to 1.125GHz with 2pf load. Operating frequency up to 750MHz with 5pf load. Operating
SN54LS245, SN74LS245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE