IDT74FCT16501AT/CT FAST CMOS 18-BIT REGISTERED TRANSCEIVER

Transcription

1 FAST MOS 18-BIT REGISTERE TRANSEIVER IT74FT16501AT/T FEATURES: 0.5 MIRON MOS Technology High-speed, low-power MOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input and output leakage 1µA (max.) ES > 200 per MIL-ST-883, Method 3015; > 20 using machine model ( = 200pF, R = 0) High drive outputs ( 32mA IOH, 64mA IOL) Power off disable outputs permit live insertion Typical VOLP (Output Ground Bounce) < 1. at = 5V, TA = 25 Available in TSSOP package ESRIPTION: The FT16501T 18-bit registered transceivers are built using advanced dual metal MOS technology. These high-speed, low-power 18-bit registered bus transceivers combine -type latches and -type flip-flops to allow data flow in transparent, latched and clocked modes. ata flow in each direction is controlled by output-enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (LKAB and LKBA) inputs. For A-to-B data flow, the device operates in transparent mode when LEAB is high. When LEAB is low, the A data is latched if LKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the low-to-high transition of LKAB. OEAB is the output enable for the B port. ata flow from the B port to the A port is similar but requires using OEBA, LEBA and LKBA. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin. The FT16501T are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers. FUNTIONAL BLOK IAGRAM OEAB 1 LKBA 30 LEBA 28 OEBA 27 LKAB 55 LEAB 2 A B1 TO 17 OTHER HANNELS The IT logo is a registered trademark of Integrated evice Technology, Inc. OTOBER Integrated evice Technology, Inc. S-5435/4

2 PIN ONFIGURATION ABSOLUTE MAXIMUM RATINGS (1) Symbol escription Max Unit OEAB 1 56 VTERM (2) Terminal Voltage with Respect to 0.5 to 7 V LEAB 2 55 LKAB VTERM (3) Terminal Voltage with Respect to 0.5 to +0.5 V A B1 TSTG Storage Temperature 65 to IOUT Output urrent 60 to +120 ma A2 A3 A4 A5 A B2 B3 B4 B5 B6 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. All device terminals except FT162XXX Output and I/O terminals. 3. Output and I/O terminals for FT162XXX A B7 A B8 APAITANE (TA = +25, f = 1.0MHz) A B9 Symbol Parameter (1) onditions Typ. Max. Unit A B10 IN Input apacitance VIN = pf A B11 OUT Output apacitance VOUT = pf A B12 NOTE: 1. This parameter is measured at characterization but not tested. A B13 Pin Names OEAB OEBA LEAB LEBA LKAB LKBA A x B x A14 A15 A16 A17 A18 OEBA LEBA PIN ESRIPTION TSSOP TOP VIEW B14 B15 B16 B17 B18 LKBA escription A-to-B Output Enable Input B-to-A Output Enable Input (Active LOW) A-to-B Latch Enable Input B-to-A Latch Enable Input A-to-B lock Input B-to-A lock Input A-to-B ata Inputs or B-to-A 3-State Outputs B-to-A ata Inputs or A-to-B 3-State Outputs FUNTION TABLE (1, 4) Inputs Outputs OEAB LEAB LKAB Ax Bx L X X X Z H H X L L H H X H H H L L L H L H H H L L X B (2) H L H X B (3) 1. A-to-B data flow is shown. B-to-A data flow is similar but uses OEBA, LEBA, and LKBA. 2. Output level before the indicated steady-state input conditions were established. 3. Output level before the indicated steady-state input conditions were established, provided that LKAB was HIGH before LEAB went LOW. 4. H = HIGH Voltage Level L = LOW Voltage Level X = on't are Z = High-impedance = LOW-to-HIGH Transition 2

3 ELETRIAL HARATERISTIS OVER OPERATING RANGE Following onditions Apply Unless Otherwise Specified: Industrial: TA = 40 to +85, = 5. ±10% Symbol Parameter Test onditions (1) Min. Typ. (2) Max. Unit VIH Input HIGH Level Guaranteed Logic HIGH Level 2 V VIL Input LOW Level Guaranteed Logic LOW Level 0.8 V IIH Input HIGH urrent (Input pins) (5) = Max. VI = ±1 µa Input HIGH urrent (I/O pins) (5) ±1 IIL Input LOW urrent (Input pins) (5) VI = ±1 Input LOW urrent (I/O pins) (5) ±1 IOZH High Impedance Output urrent = Max. VO = 2.7V ±1 µ A IOZL (3-State Output pins) (5) VO = 0.5V ±1 VIK lamp iode Voltage = Min., IIN = 18mA V IOS Short ircuit urrent = Max., VO = (3) ma VH Input Hysteresis 100 mv IL Quiescent Power Supply urrent = Max µ A IH VIN = or IZ OUTPUT RIVE HARATERISTIS Symbol Parameter Test onditions (1) Min. Typ. (2) Max. Unit IO Output rive urrent = Max., VO = 2.5V (3) ma VOH Output HIGH Voltage = Min. IOH = 3mA VIN = VIH or VIL IOH = 15mA V IOH = 32mA (4) 2 3 VOL Output LOW Voltage = Min. IOL = 64mA V VIN = VIH or VIL IOFF Input/Output Power Off Leakage (5) =, VIN or VO 4.5V ±1 μa 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical haracteristics for the applicable device type. 2. Typical values are at = 5., +25 ambient. 3. Not more than one output should be shorted at one time. uration of the test should not exceed one second. 4. uration of the condition can not exceed one second. 5. This test limit for this parameter is ±5µA at TA = 55. 3

4 POWER SUPPLY HARATERISTIS Symbol Parameter Test onditions (1) Min. Typ. (2) Max. Unit ΔI Quiescent Power Supply = Max ma urrent TTL Inputs HIGH VIN = 3.4V (3) I ynamic Power Supply urrent (4) = Max., VIN = µ A / Outputs Open VIN = MHz OEAB = OEBA = or One Input Toggling I Total Power Supply urrent (6) = Max., VIN = ma Outputs Open VIN = fp = 10MHz (LKAB) OEAB = OEBA = LEAB = VIN = 3.4V One Bit Toggling VIN = fi = 5MHz = Max., VIN = (5) Outputs Open VIN = fp = 10MHz (LKAB) OEAB = OEBA = LEAB = VIN = 3.4V (5) Eighteen Bits Toggling VIN = fi = 2.5MHz 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical haracteristics for the applicable device type. 2. Typical values are at = 5., +25 ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at or. 4. This parameter is not directly testable, but is derived for use in Total Power Supply alculations. 5. Values for these conditions are examples of the I formula. These limits are guaranteed but not tested. 6. I = IQUIESENT + IINPUTS + IYNAMI I = I + ΔI HNT + I (fpnp/2 + fini) I = Quiescent urrent (IL, IH and IZ) ΔI = Power Supply urrent for a TTL High Input (VIN = 3.4V) H = uty ycle for TTL Inputs High NT = Number of TTL Inputs at H I = ynamic urrent aused by an Input Transition Pair (HLH or LHL) fp = lock Frequency for Register evices (Zero for Non-Register evices) NP = Number of lock Inputs at fp fi = Input Frequency Ni = Number of Inputs at fi 4

5 SWITHING HARATERISTIS OVER OPERATING RANGE FT16501AT FT16501T Symbol Parameter ondition (1) Min. (2) Max. Min. (2) Max. Unit fmax LKAB or LKBA frequency (3) L = 50pF MHz tplh Propagation elay RL = 500Ω ns tphl Ax to Bx or Bx to Ax tplh Propagation elay ns tphl LEBA to Ax, LEAB to Bx tplh Propagation elay ns tphl LKBA to Ax, LKAB to Bx tpzh Output Enable Time ns tpzl OEBA to Ax, OEAB to Bx tphz Output isable Time ns tplz OEBA to Ax, OEAB to Bx tsu Set-up Time, HIGH or LOW ns Ax to LKAB, Bx to LKBA th Hold Time, HIGH or LOW 0 0 ns Ax to LKAB, Bx to LKBA tsu Set-up Time HIGH or LOW lock LOW 3 2 ns Ax to LEAB, Bx to LEBA lock HIGH th Hold Time, HIGH or LOW ns Ax to LEAB, Bx to LEBA tw LEAB or LEBA Pulse Width HIGH (3) 3 3 ns tw LKAB or LKBA Pulse Width HIGH or LOW (3) 3 3 ns tsk(o) Output Skew (4) ns 1. See test circuits and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation elays. 3. This parameter is guaranteed but not tested. 4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. 5

6 TEST IRUITS AN WAVEFORMS V 7. SWITH POSITION Pulse Generator VIN RT.U.T. VOUT 50pF L 500Ω 500Ω Test Open rain isable Low Enable Low All Other Tests Switch losed Open EFINITIONS: L = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Test ircuits for All Outputs ATA INPUT TIMING INPUT ASYNHRONOUS ONTROL PRESET LEAR ET. SYNHRONOUS ONTROL PRESET LEAR LOK ENABLE ET. tsu tsu trem th th LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE tw Pulse Width Set-up, Hold, and Release Times SAME PHASE INPUT TRANSITION OUTPUT OPPOSITE PHASE INPUT TRANSITION tplh tplh Propagation elay tphl tphl VOH VOL ONTROL INPUT OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH ENABLE tpzl SWITH LOSE tpzh SWITH OPEN 3.5V ISABLE tplz 0. tphz V VOL VOH Enable and isable Times 1. iagram shown for input ontrol Enable-LOW and input ontrol isable-high. 2. Pulse Generator for All Pulses: Rate 1.0MHz; tf 2.5ns; tr 2.5ns. 6

7 ORERING INFORMATION XX Temp. Range FT XXX Family XXXX evice Type XX Package PA PAG Thin Shrink Small Outline Package TSSOP - Green 501AT 501T 18-Bit Registered Transceiver 16 ouble-ensity, 5 Volt, High rive to +85 ORPORATE HEAQUARTERS for SALES: for Tech Support: 6024 Silver reek Valley Road or logichelp@idt.com San Jose, A fax: