SN54AHCT74, SN74AHCT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET

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1 Inputs Are TTL-Voltage ompatible Latch-Up Performance Exceeds 20 ma Per JESD 17 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A11-A) 1000-V harged-device Model (101) SN4AHT74...J OR W PAKAGE SN74AHT74... D, DB, DGV, N, NS, OR PW PAKAGE (TOP VIEW) 1LR 1D 1LK 1PRE V 2LR 2D 2LK 2PRE description/ordering information SN74AHT74... RGY PAKAGE (TOP VIEW) 1D 1LK 1PRE LR V LR 2D 2LK 2PRE 1LK N 1PRE N SN4AHT74... FK PAKAGE (TOP VIEW) 1D 1LR N V 2LR N N No internal connection 2D N 2LK N 2PRE The AHT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is traferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING QFN RGY Tape and reel SN74AHT74RGYR HB74 PDIP N Tube SN74AHT74N SN74AHT74N Tube SN74AHT74D SOI D AHT74 Tape and reel SN74AHT74DR 40 to 8 SOP NS Tape and reel SN74AHT74NSR AHT74 SSOP DB Tape and reel SN74AHT74DBR HB74 TSSOP PW Tube Tape and reel SN74AHT74PW SN74AHT74PWR HB74 TVSOP DGV Tape and reel SN74AHT74DGVR HB74 DIP J Tube SNJ4AHT74J SNJ4AHT74J to 12 FP W Tube SNJ4AHT74W SNJ4AHT74W L FK Tube SNJ4AHT74FK SNJ4AHT74FK Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2003, Texas Itruments Incorporated On products compliant to MIL-PRF-383, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFIE BOX 6303 DALLAS, TEXAS 726 1

2 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 logic diagram, each flip-flop (positive logic) PRE FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is notable; that is, it does not persist when PRE or LR retur to its inactive (high) level. LK Q D Q LR 2 POST OFFIE BOX 6303 DALLAS, TEXAS 726

3 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 7 V Input voltage range, V I (see Note 1) V to 7 V voltage range, V O (see Note 1) V to V + 0. V Input clamp current, I IK (V I < 0) ma clamp current, I OK (V O < 0 or V O > V ) ±20 ma ontinuous output current, I O (V O = 0 to V ) ±2 ma ontinuous current through V or ±0 ma Package thermal impedance, θ JA (see Note 2): D package /W (see Note 2): DB package /W (see Note 2): DGV package /W (see Note 2): N package /W (see Note 2): NS package /W (see Note 2): PW package /W (see Note 3): RGY package /W Storage temperature range, T stg to 10 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD 1-. recommended operating conditio (see Note 4) SN4AHT74 SN74AHT74 MIN MAX MIN MAX V Supply voltage V VIH High-level input voltage 2 2 V VIL Low-level input voltage V VI Input voltage V VO voltage V IOH High-level output current 8 8 ma IOL Low-level output current 8 8 ma t/ v Input traition rise or fall rate /V TA Operating free-air temperature NOTE 4: All unused inputs of the device must be held at V or to eure proper device operation. Refer to the TI application report, Implicatio of Slow or Floating MOS Inputs, literature number SBA004. POST OFFIE BOX 6303 DALLAS, TEXAS 726 3

4 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V IOH = 0 A IOH = 8 ma IOL = 0 A IOL = 8 ma 4V 4. 4V 4. TA = 2 SN4AHT74 SN74AHT74 MIN TYP MAX MIN MAX MIN MAX II VI =. V or to. V ±0.1 ±1* ±1 A I VI = V or, IO = 0. V A I One input at 3.4 V, Other inputs at V or. V ma i VI = V or V pf * On products compliant to MIL-PRF-383, this parameter is not production tested at V =. This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than or V. timing requirements over recommended operating free-air temperature range, V = V ± 0. V (unless otherwise noted) (see Figure 1) tw tsu Pulse duration Setup time before LK PARAMETER TA = 2 SN4AHT74 SN74AHT74 MIN MAX MIN MAX MIN MAX PRE or LR low LK Data PRE or LR inactive th Hold time, data after LK V V switching characteristics over recommended operating free-air temperature range, V = V ± 0. V (unless otherwise noted) (see Figure 1) FROM TO LOAD TA = 2 SN4AHT74 SN74AHT74 PARAMETER (INPUT) (OUTPUT) APAITANE MIN TYP MAX MIN MAX MIN MAX L = 1 pf 100** 160** 80** 80 fmax L = 0 pf ** 10.4** 1** 12** 1 12 PRE or LR QorQ Q L =1pF 7.6** 10.4** 1** 12** ** 7.8** 1** 9** 1 9 LK Q or Q L = 1 pf.8** 7.8** 1** 9** PRE or LR Q or Q L = 0 pf LK Q or Q L = 0 pf ** On products compliant to MIL-PRF-383, this parameter is not production tested. MHz 4 POST OFFIE BOX 6303 DALLAS, TEXAS 726

5 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 noise characteristics, V = V, L = 0 pf, T A = 2 (see Note ) PARAMETER SN74AHT74 (P) Quiet output, maximum dynamic 0.8 V (V) Quiet output, minimum dynamic 0.8 V (V) Quiet output, minimum dynamic 4 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V NOTE : haracteristics are for surface-mount packages only. operating characteristics, V = V, T A = 2 MIN MAX PARAMETER TEST ONDITIONS TYP pd Power dissipation capacitance No load, f = 1 MHz 32 pf POST OFFIE BOX 6303 DALLAS, TEXAS 726

6 SN4AHT74, SN74AHT74 WITH LEAR AND PRESET SLS263N DEEMBER 199 REVISED JULY 2003 PARAMETER MEASUREMENT INFORMATION From Under Test L (see Note A) Test Point From Under Test L (see Note A) RL = 1 kω S1 V Open TEST / tplz/tpzl tphz/tpzh Open Drain S1 Open V V LOAD IRUIT FOR TOTEM-POLE OUTPUTS LOAD IRUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS Input tw Timing Input Data Input tsu 1. V th TAGE WAVEFORMS PULSE DURATION TAGE WAVEFORMS SETUP AND HOLD TIMES Input ontrol In-Phase Out-of-Phase 0% V 0% V 0% V 0% V TAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Waveform 1 S1 at V (see Note B) Waveform 2 S1 at (see Note B) tpzl tpzh 0% V 0% V tplz + 0. tphz TAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING V 0. NOTES: A. L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditio such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 0 Ω, tr 3, tf 3. D. The outputs are measured one at a time with one input traition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load ircuit and Voltage Waveforms 6 POST OFFIE BOX 6303 DALLAS, TEXAS 726

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR

SN54AHCT174, SN74AHCT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR Inputs Are TTL-Voltage Compatible Contain Six Flip-Flops With Single-Rail s Applicatio Include: Buffer/Storage Registers Shift Registers Pattern Generators Latch-Up Performance Exceeds 250 ma Per JESD