54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
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1 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Distributed and Configuration Minimizes High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) -m Process 00-mA Typical Latch-Up Immunity at C Package Optio Include Plastic Thin Shrink Small-Outline (DGG) Package, 300-mil Shrink Small-Outline (DL) Package Using -mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using -mil Center-to-Center Pin Spacings description The AC64 are 6-bit bus traceivers organized as dual-octal noninverting 3-state traceivers designed for asynchronous two-way communication between data buses. The control function implementation minimizes external timing requirements These devices allow data tramission from the A bus to the B bus or from the B bus to the A bus, depending upon the logic level at the direction control (DIR) input. The output-enable input () can be used to disable the devices so that the buses are effectively isolated. 4AC64... WD PACKAGE 74AC64... DGG OR DL PACKAGE (TOP VIEW) DIR B B B3 B4 B B6 B7 B8 B B B3 B4 B B6 B7 B8 DIR A A A3 A4 A A6 A7 A8 A A A3 A4 A A6 A7 A8 The 74AC64 is packaged in TI s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 4AC64 is characterized for operation over the full military temperature range of C to C. The 74AC64 is characterized for operation from 40 C to 8 C. FUNCTION TABLE CONTROL INPUTS OPERATION DIR L L B data to A bus L H A data to bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applicatio of Texas Itruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Itruments Incorporated. UNLESS OTHERWISE NOTED this document contai PRODUCTION DATA information current as of publication date. Products conform to specificatio per the terms of Texas Itruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 996, Texas Itruments Incorporated POST OFFICE BOX 6303 DALLAS, TEXAS 76
2 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 logic symbol DIR DIR 48 4 G3 3 EN [BA] 3 EN [AB] G6 6 EN4 [BA] 6 EN [AB] A A A3 A4 A A6 A7 A8 A A A3 A4 A A6 A7 A B B B3 B4 B B6 B7 B8 B B B3 B4 B B6 B7 B8 This symbol is in accordance with ANSI/IEEE Std and IEC Publication 67-. logic diagram (positive logic) 48 DIR DIR 4 A 47 B A 36 3 B To Seven Other Traceivers To Seven Other Traceivers POST OFFICE BOX 6303 DALLAS, TEXAS 76
3 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V to 7 V Input voltage range, V I (see Note ) V to + 0. V Output voltage range, V O (see Note ) V to + 0. V Input clamp current, I IK (V I < 0 or V I > ) ±0 ma Output clamp current, I OK (V O < 0 or V O > ) ±0 ma Continuous output current, I O (V O = 0 to ) ±0 ma Continuous current through or ±400 ma Maximum power dissipation at T A = C (in still air) (see Note ): DGG package W DL package W Storage temperature range, T stg C to 0 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditio beyond those indicated under recommended operating conditio is not implied. Exposure to absolute-maximum-rated conditio for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.. The maximum package power dissipation is calculated using a junction temperature of 0 C and a board trace length of 70 mils. recommended operating conditio (see Note 3) 4AC64 74AC64 MIN NOM MAX MIN NOM MAX Supply voltage (see Note 4) V = 3 V.. VIH High-level input voltage = 4. V V =. V = 3 V VIL Low-level input voltage = 4. V.3.3 V =. V.6.6 VI Input voltage 0 0 V VO Output voltage 0 0 V = 3 V 4 4 IOH High-level output current = 4. V 4 4 ma =. V 4 4 = 3 V IOL Low-level output current = 4. V 4 4 ma =. V 4 4 t/ v Input traition rise or fall rate /V TA Operating free-air temperature 40 8 C NOTES: 3. All unused pi (input and I/O) must be held high or low to prevent them from floating. 4. All and pi must be connected to the proper voltage power supply. PRODUCT PREVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 6303 DALLAS, TEXAS 76 3
4 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = C 4AC64 74AC64 MIN TYP MAX MIN MAX MIN MAX 3 V IOH = 0 µa 4. V V VOH IOH = 4 ma 3 V V IOH = 4 ma 4. V V IOH = 7 ma. V V IOL = 0 µa 4. V V VOL IOL = ma 3 V V IOL =4mA 4. V V IOL = 7 ma. V.6.6 II VI = or. V ±0. ± ± µa IOZ VI = or. V ±0. ± ± µa ICC VI = or, IO = 0. V µa Ci VI = or V 4. Co VI = or V 6 Not more than one output should be tested at a time, and the duration of the test should not exceed 0 ms. For I/O ports, the parameter IOZ includes the input leakage current. switching characteristics over recommended operating free-air temperature range, = 3.3 V ± 0.3 V (see Figure ) pf PARAMETER tplh tphl tpzh tpzl tphz tplz FROM TO TA = C 4AC64 74AC64 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX BorA switching characteristics over recommended operating free-air temperature range, = V ± 0. V (see Figure ) PARAMETER tplh tphl tpzh tpzl tphz tplz FROM TO TA = C 4AC64 74AC64 (INPUT) (OUTPUT) MIN TYP MAX MIN MAX MIN MAX BorA PRODUCT PREVIEW information concer products in the formative or design phase of development. Characteristic data and other specificatio are design goals. Texas Itruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 6303 DALLAS, TEXAS 76
5 operating characteristics, = V, T A = C Cpd Power dissipation capacitance per latch 4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 PARAMETER TEST CONDITIONS TYP Outputs enabled Outputs disabled CL =0pF pf, f = MHz 43 8 pf PARAMETER MEASUREMENT INFORMATION From Output Under Test CL = 0 pf (see Note A) 00 Ω 00 Ω S Open TEST tplh/tphl tplz/tpzl tphz/tpzh S Open Input Output tplh LOAD CIRCUIT Output Control 0% 0% (low-level 0 V enabling) tpzl Output tplz 0% 0% Waveform 0% 0 V S at 0% VOL (see Note B) tphl tphz tpzh VOH Output Waveform VOH 0% 0% 80% S at 0% VOL (see Note B) 0 V VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform is for an output with internal conditio such that the output is low except when disabled by the output control. Waveform is for an output with internal conditio such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 0 Ω, tr = 3, tf = 3. D. The outputs are measured one at a time with one input traition per measurement. Figure. Load Circuit and Voltage Waveforms POST OFFICE BOX 6303 DALLAS, TEXAS 76
6 IMPORTANT NOTICE Texas Itruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditio of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specificatio applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applicatio, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applicatio assistance or customer product design. TI does not warrant or represent that any licee, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not cotitute TI s approval, warranty or endorsement thereof. Copyright 998, Texas Itruments Incorporated
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Operating Range 2-V to 5.5-V V CC 3-State s Directly Drive Bus Lines Latch-Up Performance Exceeds 250 ma Per JESD 17 description The AHC573 devices are octal traparent D-type latches designed for 2-V to
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AM6LS SLLSG JANUARY 979 REVISED FEBRUARY Meets or Exceeds the Requirements of ANSI TIA/EIA--B and ITU Recommendation V. Operates From a Single -V Supply TTL Compatible Complementary Outputs High Output
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Operating Range of 2 V to 5.5 V Max t pd of 10 at 5 V Low Power Coumption, 10-µ Max I CC ±8-m Drive at 5 V Latch-Up Performance Exceeds 250 m Per JESD 17 description/ordering information DBV OR DCK PCKGE
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WITH LEAR AND PRESET SDFS0A MARH 197 REVISED OTOBER 199 Package Optio Include Plastic Small-Outline Packages, eramic hip arriers, and Standard Plastic and eramic 00-mil DIPs description These devices contain
More informationDistributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Operating Range 2-V to 5.5-V V CC 3-State s Drive Bus Lines Directly Latch-Up
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3-State s Drive Bus Lines Directly PNP s Reduce dc Loading on Bus Lines Hysteresis at Bus s Improves Noise Margins Typical Propagation Delay Times Port to Port, 8 ns TYPE IOL (SINK CURRENT) IOH (SOURCE
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4.5-V to 5.5-V V CC Operation Fanout (Over Temperature Range) Standard s... 0 LSTTL Loads Bus-Driver s... 5 LSTTL Loads Wide Operating Temperature Range of 55 C to 25 C Balanced Propagation Delays and
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SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance
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-A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and
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Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
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Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
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SN, SN7 Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single -V Supply Differential Line Operation Dual-Channel Operation TTL Compatible ± -V Common-Mode Input Voltage Range Optional-Use
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PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
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A Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output
More informationdescription/ordering information
Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 ±24-mA Drive at 3.3 Latch-Up Performance Exceeds 250 ma Per JESD 17 description/ordering information This 16-bit (dual-octal) noninverting
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s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process
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SN54LS240, SN54LS241, SN54LS244, SN54S240, SN54S241, SN54S244 3-State s Drive Bus Lines or Buffer Memory Address Registers PNP s Reduce DC Loading Hysteresis at s Improves Noise Margins description These
More informationEN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.
EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping
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A Types Feature.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output
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18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS Members of Texas Itruments Widebus Family UT Traceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Traparent, Latched, Clocked, or Clock-Enabled
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