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1 Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has V CCB, which is set at 5 V, and A port has V CCA, which is set to operate at 3.3 V. This allows for translation from a 3.3-V to a 5-V environment and vice versa. The SN74ALVC is designed for asynchronous communication between data buses. To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. SN74ALVC DIR 1B1 1B2 1B3 1B4 (5 V) V CCB 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 (5 V) V CCB 2B5 2B6 2B7 2B8 2DIR DGG OR DL PACKAGE (TOP VIEW) OE 1A1 1A2 1A3 1A4 V CCA (3.3 V) 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 V CCA (3.3 V) 2A5 2A6 2A7 2A8 2OE TA 40 C to 85 C SSOP DL ORDERING INFORMATION PACKAGE Tube Tape and reel ORDERABLE PART NUMBER SN74ALVC164245DL SN74ALVC164245DLR TOP-SIDE MARKING ALVC TSSOP DGG Tape and reel SN74ALVC164245DGGR ALVC Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2001, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS
2 logic diagram (positive logic) 1DIR 1 2DIR OE 25 2OE 1A1 47 2A B1 13 2B1 To Seven Other Channels To Seven Other Channels absolute maximum ratings over operating free-air temperature range for V CCB at 5 V and V CCA at 3.3 V (unless otherwise noted) Supply voltage range: V CCA V to 4.6 V V CCB V to 6 V Input voltage range, V I : Except I/O ports (see Note 1) V to 6 V I/O port A (see Note 2) V to V CCA V I/O port B (see Note 1) V to V CCB V Input clamp current, I IK (V I < 0) ma clamp current, I OK (V O < 0) ma Continuous output current, I O ±50 ma Continuous current through each V CC or ±100 ma Package thermal impedance, θ JA (see Note 3): DGG package C/W DL package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 6 V maximum. 2. This value is limited to 4.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD POST OFFICE BOX DALLAS, TEXAS 75265
3 recommended operating conditions for V CCB at 5 V (see Note 4) SN74ALVC MIN MAX UNIT VCCB Supply voltage V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VIA Input voltage CCB V VOB voltage CCB V IOH High-level output current 24 ma IOL Low-level output current 24 ma t/ v Input transition rise or fall rate 10 ns/v TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at the associated VCC or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. recommended operating conditions for V CCA at 3.3 V (see Note 4) MIN MAX UNIT VCCA Supply voltage V VIH High-level input voltage VCCA = 2.7 V to 3.6 V 2 V VIL Low-level input voltage VCCA = 2.7 V to 3.6 V 0.8 V VIB Input voltage CCA V VOA voltage CCA V IOH IOL High-level output current Low-level output current VCCA = 2.7 V 12 VCCA = 3 V 24 VCCA = 2.7 V 12 VCCA = 3 V 24 t/ v Input transition rise or fall rate 10 ns/v TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at the associated VCC or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. ma ma POST OFFICE BOX DALLAS, TEXAS
4 electrical characteristics over recommended operating free-air temperature range for V CCB = 5 V (unless otherwise noted) (see Note 5) PARAMETER TEST CONDITIONS VCCB MIN TYP MAX UNIT VOH (A to B) VOL (A to B) IOH = 100 µa IOH = 24 ma IOL = 100 µa IOL =24mA 4.5 V V V V V V V V 0.55 II Control inputs VI = VCCB or 5.5 V ±5 µa IOZ A or B ports VO = VCCB or 5.5 V ±10 µa ICC VI = VCCB or, IO = V 40 µa ICC One input at 3.4 V, Other inputs at VCCB or 4.5 V to 5.5 V 750 µa Ci Control inputs VI = VCCB or 5 V 6.5 pf Cio A or B ports VO = VCCB or 5 V 6.5 pf Typical values are measured at VCC = 3.3 V, TA = 25 C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than at 0 or the associated VCC. NOTE 5: VCCA = 2.7 V to 3.6 V electrical characteristics over recommended operating free-air temperature range for V CCA = 3.3 V (unless otherwise noted) (see Note 6) PARAMETER TEST CONDITIONS VCCA MIN TYP MAX UNIT VOH (B to A) IOH = 12 ma IOH = 100 µa 2.7 V to 3.6 V VCC V V 2.4 IOH = 24 ma 3 V 2 IOL = 100 µa 2.7 V to 3.6 V 0.2 VOL (B to A) IOL = 12 ma 2.7 V 0.4 V IOL = 24 ma 3 V 0.55 II Control inputs VI = VCCA or 3.6 V ±5 µa IOZ VO = VCCA or 3.6 V ±10 µa ICC VI = VCCA or, IO = V 40 µa ICC One input at VCCA 0.6 V, Other inputs at VCCA or 3 V to 3.6 V 750 µa Ci Control inputs VI = VCCA or 3.3 V 6.5 pf Cio A or B ports VO = VCCA or 3.3 V 8.5 pf Typical values are measured at VCC = 3.3 V, TA = 25 C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than at 0 or the associated VCC. NOTE 6: VCCB = 5 V ± 0.5 V V V V 4 POST OFFICE BOX DALLAS, TEXAS 75265
5 switching characteristics over recommended operating free-air temperature range, C L = 50 pf (unless otherwise noted) (see Figures 1 and 2) PARAMETER tpd FROM (INPUT) TO (OUTPUT) VCCB = 5 V ± 0.5 V VCCA = 2.7 V V CCA = 3.3 V ± 0.3 V MIN MAX MIN MAX A B B A ten OE B ns tdis OE B ns ten OE A ns tdis OE A ns This limit can vary among suppliers. UNIT ns operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS VCCA = 3.3 V VCCB = 5 V TYP UNIT Cpd Power dissipation capacitance s enabled (A or B) s disabled (A or B) CL =50pF pf, f=10mhz 56 6 pf power-up considerations TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems. 1. Connect ground before any supply voltage is applied. 2. Next, power up the control side of the device (V CCA for all four of these devices). 3. Tie OE to V CCA with a pullup resistor so that it ramps with V CCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with V CCA. Otherwise, keep DIR low. Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021. POST OFFICE BOX DALLAS, TEXAS
6 PARAMETER MEASUREMENT INFORMATION V CCA = 2.7 V AND 3.3 V ± 0.3 V From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S1 6 V Open TEST tpd tplz/tpzl tphz/tpzh S1 Open 6 V LOAD CIRCUIT Control (low-level enabling) 3 V tpzl tplz Input tplh tphl VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES 3 V VOH VOL Waveform 1 S1 at 6 V (see Note B) Waveform 2 S1 at (see Note B) tpzh VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES VOL V VOL tphz 3 V VOH VOH 0.3 V NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX DALLAS, TEXAS 75265
7 PARAMETER MEASUREMENT INFORMATION V CCB = 5 V ± 0.5 V From Under Test CL = 50 pf (see Note A) 500 Ω 500 Ω S1 2 VCCB Open TEST tpd tplz/tpzl tphz/tpzh S1 Open 2 VCCB LOAD CIRCUIT Control (low-level enabling) 2.7 V tpzl tplz Input 2.7 V Waveform 1 S1 at 2 VCCB (see Note B) 50% VCCB VCCB 20% VCCB VOL tplh tphl VOH 50% VCCB 50% VCCB VOL Waveform 2 S1 at (see Note B) tpzh 50% VCCB tphz VOH 80% VCCB VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 2. Load Circuit and Voltage Waveforms POST OFFICE BOX DALLAS, TEXAS
8 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, license, warranty or endorsement thereof. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Resale of TI s products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service, is an unfair and deceptive business practice, and TI is not responsible nor liable for any such use. Also see: Standard Terms and Conditions of Sale for Semiconductor Products. Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2001, Texas Instruments Incorporated
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Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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3-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance
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Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
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SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
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Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input
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Operates With Single 5-V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 30-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-232-F and ITU Recommendation
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SN676B, SN776B Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus
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3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
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SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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-A -Current Capability Per Driver Applications Include Half-H and Full-H Solenoid Drivers and Motor Drivers Designed for Positive-Supply Applications Wide Supply-Voltage Range of 4.5 V to 6 V TTL- and
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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EPIC (Enhanced-Performance Implanted CMOS) Submicron Process Useful for Jumperless Configuration of PC Motherboard Inputs Accept Voltages to 5.5 V Signals are 2.5-V Outputs Signal is a 3.3-V Output Minimum
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Inputs Are TTL-oltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Operation From ery Slow Input Traitio Temperature-Compeated Threshold Levels High Noise Immunity Same Pinouts as AHCT00
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2-V to 5.5-V V CC Operation Typical V OLP (Output Ground Bounce) 2.3 V at V CC = 3.3 V, T A = 25 C Support Mixed-Mode Voltage
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SN54HC26, SN74HC26 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCLS03E MARCH 94 REVISED JULY 2003 Wide Operating Voltage Range of 2 V to 6 V High-Current 3-State Outputs Interface Directly With System
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Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional
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3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
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Low Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation pplications Operates at 3.3-V LVTTL-Compatible Inputs and s Supports Mixed-Mode Signal Operation (-V Input and Voltages With 3.3-V )
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Bidirectional Transceivers Meet or Exceed the Requirements of ANSI Standards TIA/EIA--B and TIA/EIA-8-A and ITU Recommendations V. and X.7 Designed for Multipoint Transmission on Long Bus Lines in Noisy
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WITH SELECTBLE POLRITY ND -STTE OUTPUTS SCS4 DECEMBER 99 REVISED NOVEMBER 99 Low Skew for Clock-Distribution and Clock-Generation pplicatio TTL-Compatible Inputs and s Distributes One Clock Input to Six
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Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
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-State Buffer-Type s Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) 00-mil DIPs,
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SN54HC00, SN74HC00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES SCLS181E DECEMBER 1982 REVISED AUGUST 2003 Wide Operating Voltage Range of 2 V to 6 V Outputs Can Drive Up To 10 LSTTL Loads Low Power Consumption,
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SN, SN7 Choice of Open-Collector or Active Pullup (Totem-Pole) Outputs Single -V Supply Differential Line Operation Dual-Channel Operation TTL Compatible ± -V Common-Mode Input Voltage Range Optional-Use
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CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POSITIVE-AND GATES AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage Speed of Bipolar F, AS, and S, With Significantly
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and GND Configuratio Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm
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Complete PWM Power Control Circuitry Uncommitted Outputs for 200-mA Sink or Source Current Output Control Selects Single-Ended or Push-Pull Operation Internal Circuitry Prohibits Double Pulse at Either
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
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Operates With Single -V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 0-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-22-F and ITU Recommendation
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Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
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A Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power oumption Balanced Propagation Delays ±24-mA Output
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Support the ME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range High-Drive Outputs (I OH = 60 m, I OL = 90 m) Support 25-Ω Incident-Wave Switching CC IS Pin Minimizes Signal Distortion
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Members of the Texas Itruments Widebus Family State-of-the-rt EPIC-ΙΙ icmos Design Significantly Reduces Power Dissipation Support the ME64 ETL Specification Reduced, TTL-Compatible, Input Threshold Range
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
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18-IT LTTL-TO-GTL/GTL+ UNIERSL US TRNSCEIERS Members of Texas Itruments Widebus Family UT Traceivers Combine D-Type Latches and D-Type Flip-Flops for Operation in Traparent, Latched, Clocked, or Clock-Enabled
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5-V Digital or ±7.5-V Peak-to-Peak Switching 5-Ω Typical On-State Resistance for 5-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 5-V Signal-Input Range On-State Resistance Flat Over
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Meet or Exceed the Requirements of TIA/EIA-232-F and ITU Recommendation V.28 Very Low Power Consumption... 5 mw Typ Wide Driver Supply Voltage Range... ±4.5 V to ±15 V Driver Output Slew Rate Limited to
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HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
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The ULNA is obsolete -ma Rated Collector Current (Single ) High-oltage s... Clamp Diodes ULNA, ULNA, ULNA, ULNA, ULQA, ULQA, SLRSC DECEMBER REISED MAY Inputs Compatible With arious Types of Logic Relay
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SN74CBT16214 12-BIT 1-OF-3 FET MULTIPLEXER/DEMULTIPLEXER SCDS008L MAY 1993 REVISED NOVEMBER 2001 Member of the Texas Instruments Widebus Family 5-Ω Switch Connection Between Two Ports TTL-Compatible Input
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