CD4066B CMOS QUAD BILATERAL SWITCH

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1 5-V Digital or ±7.5-V Peak-to-Peak Switching 5-Ω Typical On-State Resistance for 5-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 5-V Signal-Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output-Voltage Ratio: 8 db Typical at f is = khz, R L = kω High Degree of Linearity: <.5% Distortion Typical at f is = khz, V is = 5 V p-p, V DD V SS V, R L = kω Extremely Low Off-State Switch Leakage, Resulting in Very Low Offset Current and High Effective Off-State Resistance: pa Typical at V DD V SS = V, T A = 5 C Extremely High Control Input Impedance (Control Circuit Isolated From Signal Circuit): Ω Typical Low Crosstalk Between : 5 db Typical at f is = 8 MHz, R L = kω Matched Control-Input to Signal-Output Capacitance: Reduces Output Signal Transients Frequency Response, Switch on = MHz (Typical) % Tested for Quiescent Current at V 5-V, -V, and 5-V Parametric Ratings Meets All Requirements of JEDEC Tentative Standard No. B, Standard Specifications for Description of B-Series CMOS Devices Applications: Analog Signal Switching/Multiplexing: Signal Gating, Modulator, Squelch Control, Demodulator, Chopper, Commutating Switch Digital Signal Switching/Multiplexing Transmission-Gate Logic Implementation Analog-to-Digital and Digital-to-Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog-Signal Gain E, F, M, NS, OR PW PACKAGE (TOP VIEW) SIG A IN/OUT SIG A OUT/IN SIG B OUT/IN SIG B IN/OUT CONTROL B CONTROL C V SS V DD CONTROL A CONTROL D SIG D IN/OUT SIG D OUT/IN SIG C OUT/IN SIG C IN/OUT description/ordering information TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP F Tube F F PDIP E Tube E E 55 C to5 C SOIC M Tube M Tape and reel M9 M SOP NS Tape and reel NSR TSSOP PW Tape and reel PWR CMB Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright, Texas Instruments Incorporated POST OFFICE BOX 55 DALLAS, TEXAS 755

2 description/ordering information (continued) is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin-for-pin compatible with the CDB, but exhibits a much lower on-state resistance. In addition, the on-state resistance is relatively constant over the full input-signal range. The consists of four bilateral switches, each with independent controls. Both the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Figure, the well of the n-channel device on each switch is tied to either the input when the switch is on or to V SS when the switch is off. This configuration eliminates the variation of the switch-transistor threshold voltage with input signal and, thus, keeps the on-state resistance low over the full operating-signal range. The advantages over single-channel switches include peak input-signal voltage swings equal to the full supply voltage and more constant on-state impedance over the input-signal range. However, for sample-and-hold applications, the CDB is recommended. Switch Control IN Vis p n CONTROL VC n p n OUT All control inputs are protected by CMOS protection network. NOTES: A. All p substrates are connected to. B. Normal operation control-line biasing: Switch on (logic ), VC = ; Switch off (logic ), VC = C. Signal-level range: Vis 9CS - 9 Figure. Schematic Diagram of One of Four Identical and Associated Control Circuitry POST OFFICE BOX 55 DALLAS, TEXAS 755

3 absolute maximum ratings over operating free-air temperature (unless otherwise noted) DC supply-voltage range, (V DD ) (Voltages referenced to V SS terminal) V to V Input voltage range, V is, all inputs V to V DD +.5 V DC input current, I IN, any one input ± ma Package thermal impedance, θ JA (see Note ): E package C/W M package C/W NS package C/W PW package C/W Lead temperature (during soldering): At distance / ± / inch (,59 ±,79 mm) from case for s max C Storage temperature range, T stg C to 5 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE : The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions MIN MAX UNIT Supply voltage 8 V TA Operating free-air temperature 55 5 C POST OFFICE BOX 55 DALLAS, TEXAS 755

4 electrical characteristics PARAMETER TEST CONDITIONS VIN (V) (V) LIMITS AT INDICATED TEMPERATURES 55 C C 85 C 5 C TYP 5 C UNIT MAX, Quiescent device, IDD current, 5 5. Signal Inputs (Vis) and Output () ron ron On-state resistance (max), VC = RL =kω returned to Ω Vis = to 5 5 On-state resistance 5 5 difference between RL = kω, VC = Ω any two switches 5 5 µa THD Iis tpd Cis Cos Cios Total harmonic distortion -db cutoff frequency (switch on) 5-dB feed-through frequency (switch off) Input/output leakage current (switch off) (max) 5-dB crosstalk frequency Propagation delay (signal input to signal output) Input capacitance Output Feedthrough VC = = 5 V, = 5 V, Vis(p-p) = 5 V (sine wave centered on V), RL = kω, fis = khz sine wave. % VC = = 5 V, = 5 V, Vis(p-p) = 5 V (sine wave centered on V), MHz RL = kω VC = = 5 V, Vis(p-p) = 5 V (sine wave centered on V), MHz RL = kω VC = V, Vis = 8 V, = V; and 8 ±. ±. ± ± ± 5 ±. µa VC = V, Vis = V, = 8 V VC(A) = = 5 V, VC(B) = = 5 V, 8 MHz Vis(A) = 5 Vp-p, 5-Ω source, RL = kω RL = kω, VC =, 5 = GND, CL =5pF F, Vis = V ns (square wave centered on 5 V), tr, tf = ns = 5 V VC = = 5 V pf POST OFFICE BOX 55 DALLAS, TEXAS 755

5 electrical characteristics (continued) Control (VC) VILC VIHC IIN CHARACTERISTIC TEST CONDITIONS (V) Control input, low voltage (max) Control input, high voltage Input current (MAX) Crosstalk (control input to signal output) LIMITS AT INDICATED TEMPERATURES 55 C C 85 C 5 C TYP 5 C UNIT Iis <µa, 5 Vis =, VOS =, and V Vis =, VOS = (MIN) See Figure 7 (MIN) V Vis, = 8 V, VCC VC = V (square wave), tr, tf = ns, RL = kω Turn-on and turn-off VIN =, tr, tf = ns, propagation delay CL =5pF F, RL =kω Maximum control input repetition rate 5 (MIN) MAX 8 ±. ±. ± ± ± 5 ±. µa 5 mv ns 5 5 Vis =, = GND, 5 RL =kω to GND, CL =5pF F, VC = V (square wave 9 MHz centered on 5 V), tr, tf = ns, = / at khz CI Input capacitance pf switching characteristics (V) SWITCH INPUT Iis (ma) SWITCH OUTPUT, VOS (V) Vis (V) 55 C C 5 C 85 C 5 C MIN MAX POST OFFICE BOX 55 DALLAS, TEXAS 755 5

6 TYPICAL CHARACTERISTICS TYPICAL ON-STATE RESISTANCE VS INPUT SIGNAL VOLTAGE (ALL TYPES) TYPICAL ON-STATE VS INPUT SIGNAL VOLTAGE (ALL TYPES) r on Channel On-State Resistance Ω 5 Supply Voltage ( ) = 5 V TA = 5 C +5 C 55 C r on Channel On-State Resistance Ω Supply Voltage ( ) = V TA = 5 C +5 C 55 C Vis Input Signal Voltage V Vis Input Signal Voltage V 9CS-7RI 9CS-77RI Figure Figure TYPICAL ON-STATE RESISTANCE VS INPUT SIGNAL VOLTAGE (ALL TYPES) Supply Voltage ( ) = 5 V ON-STATE RESISTANCE VS INPUT SIGNAL VOLTAGE (ALL TYPES) TA = 5 C r on Channel On-State Resistance Ω TA = 5 C +5 C 55 C r on Channel On-State Resistance Ω 5 Supply Voltage ( ) = 5 V V 5 V Vis Input Signal Voltage V Figure 9CS-79RI Vis Input Signal Voltage V Figure 5 9CS-7RI POST OFFICE BOX 55 DALLAS, TEXAS 755

7 TYPICAL CHARACTERISTICS Vis Iis of ron = Vis Iis 9CS - 9 Figure. Determination of r on as a Test Condition for Control-Input High-Voltage (V IHC ) Specification Keithley Digital Multimeter kω TG on -kω Range Y X Y Plotter H. P. Moseley 7A X 9CS - 7 Figure 7. Channel On-State Resistance Measurement Circuit Output Voltage V V O TYPICAL ON CHARACTERISTICS FOR OF CHANNELS VC = Vis of All unused terminals are connected to RL Power Dissipation Per Package W D µ P POWER DISSIPATION PER PACKAGE VS SWITCHING FREQUENCY TA = 5 C Supply Voltage () = 5 V V 5 V 5 7 VI Input Voltage V Figure 8 9CS - 99 f Switching Frequency khz Figure 9 9CS -9 POST OFFICE BOX 55 DALLAS, TEXAS 755 7

8 TYPICAL CHARACTERISTICS Cios VC = 5 V = 5 V Cis of = 5 V Cos VC = Vis = of I 9CS -9 Measured on Boonton capacitance bridge, model 75a ( MHz) test-fixture capacitance nulled out Figure. Typical on Characteristics for One of Four Channels 9CS-9 All unused terminals are connected to. Figure. Off-Switch Input or Output Leakage VC = Vis tr = tf = ns of 5 pf All unused terminals are connected to. kω 9CS-9 + V tr = tf = ns kω VC Vis All unused terminals are connected to. of kω 9CS-9 Figure. Propagation Delay Time Signal Input (V is ) to Signal Output (V os ) Figure. Crosstalk-Control Input to Signal Output 8 POST OFFICE BOX 55 DALLAS, TEXAS 755

9 TYPICAL CHARACTERISTICS VC Rep Rate tr = tf = ns tr = tf = ns VC = of 5 pf kω + V tr = tf = ns 9% VC Vis = V ns ns of % = V 5 pf = / at khz kω NOTES: A. All unused terminals are connected to. B. Delay is measured at VOS level of +% from ground (turn-on) or on-state output level (turn-off). Figure. Propagation Delay t PLH, t PHL Control-Signal Output 9CS-95 All unused terminals are connected to Figure 5. Maximum Allowable Control-Input Repetition Rate 9CS-95 Inputs I 9CS-7555 Measure inputs sequentially, to both and. Connect all unused inputs to either or. Measure control inputs only. Figure. Input Leakage-Current Test Circuit POST OFFICE BOX 55 DALLAS, TEXAS 755 9

10 TYPICAL CHARACTERISTICS 7 9 Clock PE J J J J J5 Reset 5 CD8B Q Q 5 / External Reset Clock PE J J J J J5 CD8B Q Q 5 5 Signal Inputs / CD9B Package Count - CDB - CD9B - - CD8B Channel Channel Channel Channel CDB Maximum Allowable Signal Level 8 Clock 5 9 kω Chan Chan Chan Chan 7 9 / CD9B / CD9B 5 / 8 % ( ) CDB 5 9 Signal Outputs Channel LPF kω LPF kω LPF kω LPF kω Channel Channel Channel 9CM - 98 Figure 7. Four-Channel PAM Multiplex System Diagram POST OFFICE BOX 55 DALLAS, TEXAS 755

11 TYPICAL CHARACTERISTICS 5 V 5 V = 5 V Analog Inputs (±5 V) = 5 V 5 V SWA O IN CD5B SWB SWC Digital Control Inputs = V VEE = 5 V Analog Outputs (±5 V) SWD = 5 V 9CS - 97 Figure 8. Bidirectional Signal Transmission Via Digital Control Logic POST OFFICE BOX 55 DALLAS, TEXAS 755

12 APPLICATION INFORMATION In applications that employ separate power sources to drive V DD and the signal inputs, the V DD current capability should exceed V DD /R L (R L = effective external load of the four bilateral switches). This provision avoids any permanent current flow or clamp action on the V DD supply when power is applied or removed from the. In certain applications, the external load-resistor current can include both V DD and signal-line components. To avoid drawing V DD current when switch current flows into terminals,, 8, or, the voltage drop across the bidirectional switch must not exceed.8 V (calculated from r on values shown). No V DD current will flow through R L if the switch current flows into terminals,, 9, or. POST OFFICE BOX 55 DALLAS, TEXAS 755

13 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box 55 Dallas, Texas 755 Copyright, Texas Instruments Incorporated

CD4066B CMOS QUAD BILATERAL SWITCH

CD4066B CMOS QUAD BILATERAL SWITCH 15-V Digital or ±7.5-V Peak-to-Peak Switching 125-Ω Typical On-State Resistance for 15-V Operation Switch On-State Resistance Matched to Within 5 Ω Over 15-V Signal-Input Range On-State Resistance Flat