CD74HC4067, CD74HCT4067

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Data sheet acquired from Harris Semiconductor SCHS209 February 1998 CD74HC4067, CD74HCT4067 High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer [ /Title (CD74 HC406 7, CD74 HCT40 67)

1 Data sheet acquired from Harris Semiconductor SCHS209 February 1998 CD74HC4067, CD74HCT4067 High-Speed CMOS Logic 16-Channel Analog Multiplexer/Demultiplexer [ /Title (CD74 HC406 7, CD74 HCT40 67) /Subject (High- Speed CMOS Features Wide Analog Input Voltage Range Low ON Resistance - = 4.5V Ω (Typ) - = 6V Ω (Typ) Fast Switching and Propagation Speeds Break-Before-Make Switching ns (Typ) at 4.5V Available in Both Narrow and Wide-Body Plastic Packages Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of Pinout at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Description The Harris CD74HC4067 and CD74HCT4067 are digitally controlled analog switches which utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integrated circuits. These analog multiplexers/demultiplexers control analog voltages that may vary across the voltage supply range. They are bidirectional switches thus allowing any analog input to be used as an output and visa-versa. The switches have low on resistance and low off leakages. In addition, these devices have an enable control which when high will disable all switches to their off state. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE PKG. NO. CD74HC4067, CD74HCT4067 (PDIP, SOIC) TOP VIEW COMMON INPUT/OUTPUT I I 8 I I 9 I I 10 I I 11 I I 12 I I 13 I I 14 I I 15 S E S S S 3 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright Harris Corporation File Number

2 Functional Diagram I S 0 11 S 1 14 S 2 13 S 3 P N BINARY 1 OF 16 DECODER S N = 5 STAGES E = 4 STAGES 14 - OUTPUT CIRCUITS SAME AS ABOVE (WITH ANALOG INPUTS) I 1 TO I 14 1 COMMON INPUT/ OUTPUT P N E 15 I TRUTH TABLE S0 S1 S2 S3 E SELECTED CHANNEL X X X X 1 None NOTE: H = High Level L = Low Level X = Don t Care 2

3 Absolute Maximum Ratings DC Supply Voltage, (Voltages Referenced to Ground) V to 7V DC Input Diode, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Drain, I O For -0.5V < V O < + 0.5V ±25mA DC Output Diode, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Output Source or Sink per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 3) θ JA ( o C/W) PDIP Package SOIC Package Maximum Junction Temperature (Hermetic Package or Die) o C Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Voltage Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output Voltage, V I, V O V to Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 3. θ JA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER HC TYPES SYMBOL V I (V) V IS (V) (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage V IH V V V Low Level Input Voltage V IL V V V Maximum ON Resistance I O = 1mA R ON or to or to Ω Ω Ω Ω Maximum ON Resistance Between Any Two Switches R ON Ω Ω Switch Off Leakage 16 Channels I IZ E= or ±0.8 - ±8 - ±8 µa Logic Input Leakage I I or ±0.1 - ±1 - ±1 µa Quiescent Device I O = 0mA I CC or µa 3

4 DC Electrical Specifications (Continued) PARAMETER HCT TYPES High Level Input Voltage Low Level Input Voltage Maximum ON Resistance I O = 1mA Maximum ON Resistance Between Any Two Switches Switch Off Leakage 16 Channels Logic Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: 1 Unit Load SYMBOL V IH V V IL V R ON or to or to Ω Ω R ON Ω I IZ E= or I I I CC I CC (Note 4) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) V IS (V) (V) MIN TYP MAX MIN MAX MIN MAX or (Note 5) or ±0.8 - ±8 - ±8 µa ±0.1 - ±1 - ±1 µa µa µa NOTES: 4. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. 5. Any voltage between and. HCT Input Loading Table INPUT UNIT LOADS S 0 - S E 0.3 NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 360µA max at 25 o C. UNITS Switching Specifications Input t r, t f = 6ns PARAMETER HC TYPES Propagation Delay Time Switch In to Out Switch Turn On E to Out SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o CTO125 o C MIN TYP MAX MIN MAX MIN MAX UNITS t PLH, t PHL C L = 50pF ns ns ns C L = 15pF ns t PZH, t PZL C L = 50pF ns ns ns C L = 15pF ns 4

5 Switching Specifications Input t r, t f = 6ns (Continued) Switch Turn On Sn to Out Switch Turn Off E to Out t PZH, t PZL C L = 50pF ns ns ns C L = 15pF ns t PHZ, t PLZ C L = 50pF ns ns ns C L = 15pF ns Switch Turn Off t PHZ, t PLZ C L = 50pF ns Sn to Out ns ns C L = 50pF ns Input (Control) Capacitance C I pf Power Dissipation Capacitance (Notes 6, 7) C PD pf HCT TYPES Propagation Delay Time Switch In to Out Switch Turn On E to Out Switch Turn On Sn to Out Switch Turn Off E to Out PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o CTO125 o C MIN TYP MAX MIN MAX MIN MAX t PLH, t PHL C L = 50pF ns C L = 15pF ns t PZH, t PZL C L = 50pF ns C L = 15pF ns t PZH, t PZL C L = 50pF ns C L = 15pF ns t PHZ, t PLZ C L = 50pF ns C L = 15pF ns Switch Turn Off t PHZ, t PLZ C L = 50pF ns Sn to Out C L = 15pF ns Input (Control) Capacitance C I pf Power Dissipation Capacitance (Notes 6, 7) C PD pf NOTES: 6. C PD is used to determine the dynamic power consumption, per package. 7. P D =C PD V 2 CC fi + Σ (C L +C S )V 2 CC fo where f i = input frequency, f o = output frequency, C L = output load capacitance, C S = switch capacitance, = supply voltage. UNITS 5

6 6

7 Analog Channel Specifications T A = 25 o C PARAMETER TEST CONDITIONS (V) HC/HCT UNITS Switch Frequency Response Bandwidth at -3dB (Figure 2) Figure 4, Notes 8, MHz Sine Wave Distortion Figure % Feedthrough Noise E to Switch Figure 6, Notes 9, TBE mv Feedthrough Noise S to Switch TBE mv Switch OFF Signal Feedthrough (Figure 3) Figure db Switch Input Capacitance, C S - 5 pf Common Capacitance, C COM - 50 pf NOTES: 8. Adjust input level for 0dBm at output, f = 1MHz. 9. V IS is centered at / Adjust input for 0dBm at V IS. Typical Performance Curves ON RESISTANCE, R ON (Ω) T A = 25 o C, = 0V = 4.5V INPUT SIGNAL VOLTAGE, V IS (V) FIGURE 1. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE UNITS (db) = 4.5V -9 R L = 50Ω T A = 25 o C FREQUENCY, f (Hz) FIGURE 2. TYPICAL SWITCH FREQUENCY RESPONSE SWITCH-OFF SIGNAL FEEDTHROUGH (db) = 4.5V R L = 50Ω T A = 25 o C FREQUENCY, f (Hz) FIGURE 3. TYPICAL SWITCH-OFF SIGNAL FEEDTHROUGH vs FREQUENCY 7

8 Analog Test Circuits V IS 0.1µF SWITCH ON V OS SINE WAVE 10µF V IS SWITCH ON V OS /2 50Ω 10pF db METER /2 10kΩ 50pF DISTORTION METER f IS = 1kHz TO 10kHz FIGURE 4. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 5. SINE WAVE DISTORTION TEST CIRCUIT 600Ω SWITCH ALTERNATING ON AND OFF t r, t f 6ns f CONT = 1MHz 50% DUTY CYCLE /2 600Ω V OS 10pF SCOPE V IS 0.1µF R /2 VCC SWITCH OFF V C = V IL R /2 f IS 1MHz SINEWAVE R = 50Ω C = 10pF C V OS db METER FIGURE 6. CONTROL-TO-SWITCH FEEDTHROUGH NOISE TEST CIRCUIT FIGURE 7. SWITCH OFF SIGNAL FEEDTHROUGH TEST CIRCUIT Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 10% INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% 10% INVERTING OUTPUT t PHL t PLH 90% 1.3V 10% FIGURE 8. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 9. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8

9 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ( CRITICAL APPLICATIONS ). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER S RISK. In order to minimize risks associated with the customer s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI s publication of information regarding any third party s products or services does not constitute TI s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated

CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053

Data sheet acquired from Harris Semiconductor SCHS122B November 1997 - Revised May 2000 CD54/74HC4051, CD54/74HCT4051, CD54/74HC4052, CD74HCT4052, CD54/74HC4053, CD74HCT4053 High Speed CMOS Logic Analog