CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description

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Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features

1 Data sheet acquired from Harris Semiconductor SCHS166F November Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description [ /Title (CD74 HC221, CD74 HCT22 1) /Subject (High Speed CMOS Logic Dual Monos table Multi- Overriding RESET Terminates Output Pulse Triggering from the Leading or Trailing Edge Q and Q Buffered Outputs Separate Resets Wide Range of Output-Pulse Widths Schmitt Trigger on B Inputs Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of at = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH Pinout CD54HC221 (CERDIP) CD74HC221 (PDIP, SOIC, SOP, TSSOP) CD74HCT221 (PDIP, SOIC) TOP VIEW 1A 1B 1R 1Q 2Q 2C X 2C X R X C X R X 14 1C X 13 1Q 12 2Q 11 2R 10 2B 9 2A The HC221 and CD74HCT221 are dual monostable multivibrators with reset. An external resistor (R X ) and an external capacitor (C X ) control the timing and the accuracy for the circuit. Adjustment of R X and C X provides a wide range of output pulse widths from the Q and Q terminals. Pulse triggering on the B input occurs at a particular voltage level and is not related to the rise and fall time of the trigger pulse. Once triggered, the outputs are independent of further trigger inputs on A and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing Edge triggering (A) and leading-edge-triggering (B) inputs are provided for triggering from either edge of the input pulse. On power up, the IC is reset. If either Mono is not used each input (on the unused device) must be terminated either high or low. The minimum value of external resistance, R X, is typically 500Ω. The minimum value of external capacitance, C X, is 0pF. The calculation for the pulse width is t W = 0.7 R X C X at = 4.5V. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC221F3A -55 to Ld CERDIP CD74HC221E -55 to Ld PDIP CD74HC221M -55 to Ld SOIC CD74HC221MT -55 to Ld SOIC CD74HC221M96-55 to Ld SOIC CD74HC221NSR -55 to Ld SOP CD74HC221PW -55 to Ld TSSOP CD74HC221PWR -55 to Ld TSSOP CD74HC221PWT -55 to Ld TSSOP CD74HCT221E -55 to Ld PDIP CD74HCT221M -55 to Ld SOIC CD74HCT221MT -55 to Ld SOIC CD74HCT221M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2003, Texas Instruments Incorporated 1

2 Functional Diagram 1C X 1R X A 1B 1 2 1C X 1C X R X MONO Q 1Q 1R 3 2R 11 2A 9 5 2Q 2B 10 MONO Q 2C X 2C X R X 6 7 2C X 2R X TRUTH TABLE INPUTS OUTPUTS A B R Q Q H X H L H X L H L H L H H H X X L L H L H (Note 3) (Note 3) H = High Level, L = Low Level, X = Irrelevant, = Transition from Low to High Level, = Transition from High to Low Level, = One High Level Pulse, = One Low Level Pulse NOTE: 1. For this combination the reset input must be low and the following sequence must be used: pin 1 (or 9) must be set high or pin 2 (or 10) set low; then pin 1 (or 9) must be low and pin 2 (or 10) set high. Now the reset input goes from lowto-high and the device will be triggered. 2

3 Logic Diagram C P 16 N R X A 1 (9) B 2 (10) R 3 (11) P RESET FF R D C P OP AMP + - R2 15 (7) S R Q C R X C X QM QM PP MIRROR VOLTAGE R3 C X MASK FF S Q R Q MAIN FF R1 R4 N PULLDOWN FF D C Q N 14 (6) C X 8 4 (12) (13) 5 C R Q Q Q + - OP AMP 3

4 Absolute Maximum Ratings DC Supply, V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < + 0.5V ±25mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < + 0.5V ±25mA DC or Ground Current, I CC ±50mA Thermal Information Package Thermal Impedance, θ JA (see Note 2): E (PDIP) Package o C/W M (SOIC) Package o C/W NS (SOP) Package o C/W PW (TSSOP) Package o C/W Maximum Junction Temperature (Plastic Package) o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to Input Rise and Fall Time, t r, t f on Inputs A and R 2V ns (Max) 4.5V ns (Max) 6V ns (Max) Input Rise and Fall Time, t r, t f on Input B 2V Unlimited ns (Max) 4.5V Unlimited ns (Max) 6V Unlimited ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 2. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads SYMBOL TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V UNITS V V V V OL V IH or V IL V V V V V V 4

5 DC Electrical Specifications (Continued) PARAMETER Input Leakage Current Quiescent Device Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL I I I CC or or V IH to 5.5 V IL to ±0.1 - ±1 - ±1 µa µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC I CC (Note 3) TEST CONDITIONS 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX and or V ±0.1 - ±1 - ±1 µa µa to 5.5 NOTE: 3. For dual-supply systems theoretical worst case (V I = 2.4V, = 5.5V) specification is 1.8mA. HCT Input Loading Table UNITS µa INPUT UNIT LOADS All Inputs 0.3 NOTE: Unit Load is I CC limit specified in DC Electrical Table, e.g., 360µA max at 25 o C. Prerequisite For Switching Function 25 o C -40 o C TO 85 o C -55 o C TO 125 o C PARAMETER SYMBOL (V) MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Input Pulse Width t WL ns A ns ns Input Pulse Width t WH ns B ns ns 5

6 Prerequisite For Switching Function (Continued) Input Pulse Width Reset Recovery Time R to A or B Output Pulse Width Q or Q C X = 0.1µF R X = 10kΩ Output Pulse Width Q or Q C X = 28pF, R X = 2kΩ t WL ns ns ns t SU ns ns ns t W µs t W ns C X = 1000pF, R X = 2kΩ t W µs C X = 1000pF, R X = 10kΩ t W µs HCT TYPES Input Pulse Width A t WL ns Input Pulse Width B Input Pulse Width Reset Recovery Time R to A or B PARAMETER SYMBOL (V) Output Pulse Width Q or Q C X = 0.1µF R X = 10kΩ Output Pulse Width Q or Q C X = 28pF, R X = 2kΩ t WH ns t WL ns t SU ns t W µs t W ns C X = 1000pF, R X = 2kΩ t W µs C X = 1000pF, R X = 10kΩ t W µs Switching Specifications Input t r, t f = 6ns 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay, Trigger A, B, R to Q t PLH C L = 50pF ns C L = 50pF ns C L = 50pF ns C L = 15pF ns Propagation Delay, Trigger A, B, R to Q t PHL C L = 50pF ns C L = 50pF ns C L = 50pF ns C L = 15pF ns 6

7 Switching Specifications Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS Propagation Delay, R to Q t PLH C L = 50pF ns ns ns Propagation Delay, R to Q t PHL C L = 50pF ns ns ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns Input Capacitance C IN pf Pulse Width Match Between Circuits in the Same Package C X = 1000pF, R X = 10kΩ to ± % Power Dissipation Capacitance (Notes 4, 5) HCT TYPES Propagation Delay, Trigger A, B, R to Q Propagation Delay, Trigger A, B, R to Q Propagation Delay, R to Q Propagation Delay, R to Q CPD pf t PLH C L = 50pF ns C L = 15pF ns t PHL C L = 50pF ns C L = 15pF ns t PLH C L = 50pF ns t PHL C L = 50pF ns Output Transition Time t TLH, t THL C L = 50pF ns ns ns Input Capacitance C IN pf Pulse Width Match Between Circuits in the Same Package C X = 1000pF, R X = 10kΩ to ± % Power Dissipation Capacitance (Notes 4, 5) CPD pf NOTES: 4. C PD is used to determine the dynamic power consumption, per multivibrator. 5. P D = (C PD + C L ) V 2 CC f i + Σ where f i = input frequency, f o = output frequency, C L = output load capacitance, = supply voltage. 7

8 Test Circuits and Waveforms t r C L CLOCK t f C L I t WL + t WH = fcl 90% 50% 50% 50% 10% 10% t r C L = 6ns CLOCK t f C L = 6ns I t WL + t WH = fcl 3V 2.7V 1.3V 1.3V 1.3V 0.3V 0.3V t WL t WH t WL t WH NOTE: Outputs should be switching from 10% to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH NOTE: Outputs should be switching from 10% to 90% in accordance with device truth table. For f MAX, input duty cycle = 50%. FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 10% INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% 10% INVERTING OUTPUT t PHL t PLH 90% 1.3V 10% FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 8

9 Typical Performance Curves 685 R X = 10K R X = 10K = 5V T A = 25 o C t W, PULSE WIDTH (µs) C X = 1µF K FACTOR HCT T A, AMBIENT TEMPERATURE ( o C) , SUPPLY VOLTAGE (V) FIGURE 5. HC/HCT221 OUTPUT PULSE WIDTH vs TEMPERATURE FIGURE 6. HC/HCT221 K FACTOR vs SUPPLY VOLTAGE = 2V = 4.5V t W, PULSE WIDTH (µs) R X = 100K R X = 50K R X = 10K R X = 2K t W, PULSE WIDTH (µs) R X = 100K R X = 50K R X = 10K R X = 2K C X, TIMING CAPACITANCE (pf) C X, TIMING CAPACITANCE (pf) FIGURE 7. HC221 OUTPUT PULSE WIDTH vs C X FIGURE 8. HC/HCT221 OUTPUT PULSE WIDTH vs C X 9

10 10

15 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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