description/ordering information

Size: px

Start display at page:

Download "description/ordering information"

Blanche Cain
5 years ago
Views:

1 Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 ±24-mA Drive at 3.3 Latch-Up Performance Exceeds 250 ma Per JESD 17 description/ordering information This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has CCB, which is set to operate at 3.3 and 5. A port has CCA, which is set to operate at 2.5 and 3.3. This allows for translation from a 2.5- to a 3.3- environment, and vice versa, or from a 3.3- to a 5- environment, and vice versa. The SN74ALC is designed for asynchronous communication between data buses. To ensure the high-impedance state during power up or power down, the output-enable (OE) input should be tied to CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. 1DIR 1B1 1B2 1B3 1B4 (3.3, 5 ) CCB 1B5 1B6 1B7 1B8 2B1 2B2 2B3 2B4 (3.3, 5 ) CCB 2B5 2B6 2B7 2B8 2DIR DGG OR DL PACKAGE (TOP IEW) OE 1A1 1A2 1A3 1A4 CCA (2.5, 3.3 ) 1A5 1A6 1A7 1A8 2A1 2A2 2A3 2A4 CCA (2.5, 3.3 ) 2A5 2A6 2A7 2A8 2OE TA SSOP DL ORDERING INFORMATION PACKAGE Tube Tape and reel ORDERABLE PART NUMBER SN74ALC164245DL SN74ALC164245DLR TOP-SIDE MARKING ALC C to 85 C TSSOP DGG Tape and reel SN74ALC164245DGGR ALC FBGA GQL FBGA ZQL (Pb-free) Tape and reel SN74ALC164245KR 74ALC164245ZQLR C4245 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at FUNCTION TABLE (each 8-bit section) INPUTS OE DIR OPERATION L L B data to A bus L H A data to B bus H X Isolation Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Widebus is a trademark of Texas Instruments. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 A B C D E F G H J K GQL OR ZQL PACKAGE (TOP IEW) terminal assignments A 1DIR NC NC NC NC 1OE B 1B2 1B1 1A1 1A2 C 1B4 1B3 CCB CCA 1A3 1A4 D 1B6 1B5 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 2A4 2A3 H 2B5 2B6 CCB CCA 2A6 2A5 J 2B7 2B8 2A8 2A7 K 2DIR NC NC NC NC 2OE NC No internal connection logic diagram (positive logic) 1DIR 1 2DIR OE 25 2OE 1A1 47 2A B1 13 2B1 To Seven Other Channels To Seven Other Channels Pin numbers shown are for the DGG and DL packages. 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 absolute maximum ratings over operating free-air temperature range for CCB at 5 and CCA at 3.3 (unless otherwise noted) Supply voltage range: CCA to 4.6 CCB to 6 Input voltage range, I : Except I/O ports (see Note 1) to 6 I/O port A (see Note 2) to CCA I/O port B (see Note 1) to CCB Input clamp current, I IK ( I < 0) ma clamp current, I OK ( O < 0) ma Continuous output current, I O ±50 ma Continuous current through each CC or ±100 ma Package thermal impedance, θ JA (see Note 3): DGG package C/W DL package C/W GQL/ZQL package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. This value is limited to 6 maximum. 2. This value is limited to 4.6 maximum. 3. The package thermal impedance is calculated in accordance with JESD recommended operating conditions for CCB at 3.3 and 5 (see Note 4) MIN MAX UNIT CCB Supply voltage IH High-level input voltage 2 IL Low-level input voltage CCB = 3 to CCB = 4.5 to IA Input voltage CCB OB voltage CCB IOH High-level output current 24 ma IOL Low-level output current 24 ma t/ v Input transition rise or fall rate 10 ns/ TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at the associated CC or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. POST OFFICE BOX DALLAS, TEXAS

4 recommended operating conditions for CCA at 2.5 and 3.3 (see Note 4) MIN MAX UNIT CCA Supply voltage IH IL High-level input voltage Low-level input voltage CCA = 2.3 to CCA = 3 to CCA = 2.3 to CCA = 3 to IB Input voltage CCA OA voltage CCA IOH IOL High-level output current Low-level output current CCA = 2.3 CCA = CCA = CCA = 3 24 t/ v Input transition rise or fall rate 10 ns/ TA Operating free-air temperature C NOTE 4: All unused inputs of the device must be held at the associated CC or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range for CCA = 2.7 to 3.6 and CCB = 4.5 to 5.5 (unless otherwise noted) PARAMETER TEST CONDITIONS CCA CCB MIN TYP MAX UNIT IOH = 100 µa 2.7 to 3.6 CC 0.2 ma ma OH (B to A) IOH = 12 ma IOH = 24 ma IOH = 100 µaa OH (A to B) IOH = 24 ma IOL = 100 µa 2.7 to OL (B to A) IOL = 12 ma OL (A to B) IOL = 24 ma IOL = 100 µa 4.5 to IOL = 24 ma 4.5 to II Control inputs I = CCA/CCB or ±5 µa IOZ A or B ports O = CCA/CCB or ±10 µa ICC I = CCA/CCB or, IO = µa ICC One input at CCA/CCB 0.6, Other inputs at CCA/CCB or 3 to to µa Ci Control inputs I = CCA/CCB or pf Cio A or B ports O = CCA/CCB or pf Typical values are measured at CCA = 3.3 and CCB = 5, TA = 25 C. For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated CC. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 electrical characteristics over recommended operating free-air temperature range for CCA = 2.3 to 2.7 and CCB = 3 to 3.6 (unless otherwise noted) PARAMETER TEST CONDITIONS CCA CCB MIN MAX UNIT IOH = 100 µa 2.3 to to 3.6 CCA 0.2 OH (B to A) IOH = 8 ma to OH (A to B) OL (B to A) OL (A to B) IOH = 12 ma to IOH = 100 µa 2.3 to to 3.6 CCB 0.2 IOH = 18 ma 2.3 to IOL = 100 µa 2.3 to to IOL = 12 ma to IOL = 100 µa 2.3 to to IOL = 18 ma II Control inputs I = CCA/CCB or 2.3 to to 3.6 ±5 µa IOZ A or B ports O = CCA/CCB or 2.3 to to 3.6 ±10 µa ICC I = CCA/CCB or, IO = to to µa ICC One input at CCA/CCB 0.6, Other inputs at CCA/CCB or 2.3 to to µa For I/O ports, the parameter IOZ includes the input leakage current. This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at 0 or the associated CC. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1-4) PARAMETER tpd FROM (INPUT) TO (OUTPUT) CCB = 3.3 ± 0.3 CCA = 2.5 ± 0.2 CCB = 5 ± 0.5 CCA = 2.7 CCA = 3.3 ± 0.3 MIN MAX MIN MAX MIN MAX A B B A ten OE B ns tdis OE B ns ten OE A ns tdis OE A ns UNIT ns operating characteristics, T A = 25 C Cpd CCB = 3.3 CCB = 5 PARAMETER TEST CONDITIONS CCA = 2.5 CCA = 3.3 UNIT TYP TYP s enabled (B) CL = 50 pf, f = 10 MHz Power dissipation s disabled (B) 27 6 capacitance s enabled (A) CL = 50 pf, f = 10 MHz s disabled (A) 58 6 pf POST OFFICE BOX DALLAS, TEXAS

6 power-up considerations TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. Take these precautions to guard against such power-up problems. 1. Connect ground before any supply voltage is applied. 2. Next, power up the control side of the device ( CCA for all four of these devices). 3. Tie OE to CCA with a pullup resistor so that it ramps with CCA. 4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus), ramp it with CCA. Otherwise, keep DIR low. Refer to the TI application report, Texas Instruments oltage-level-translation Devices, literature number SCEA POST OFFICE BOX DALLAS, TEXAS 75265

7 PARAMETER MEASUREMENT INFORMATION CCA = 2.5 ± 0.2 TO CCB = 3.3 ± 0.3 From Under Test CL = 30 pf (see Note A) CCB = 6 TEST tpd tplz/tpzl tphz/tpzh CCB = 6 LOAD CIRCUIT Control (low-level enabling) CCA/2 CCA/2 CCA tpzl tplz Input tplh CCA/2 CCA/2 tphl OLTAGE WAEFORMS PROPAGATION DELAY TIMES CCA OHB OLB Waveform 1 at 6 Waveform 2 at tpzh OLTAGE WAEFORMS ENABLE AND DISABLE TIMES OL OLB tphz CCB OHB OH 0.3 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 1. Load Circuit and oltage Waveforms POST OFFICE BOX DALLAS, TEXAS

8 PARAMETER MEASUREMENT INFORMATION CCB = 3.3 ± 0.3 TO CCA = 2.5 ± 0.2 From Under Test CL = 30 pf (see Note A) 2 CCA TEST tpd tplz/tpzl tphz/tpzh 2 CCA LOAD CIRCUIT Control (low-level enabling) 2.7 tpzl tplz Input 2.7 Waveform 1 at 2 CCA CCA/2 CCA OL OLA tplh CCA/2 tphl OHA CCA/2 OLA Waveform 2 at tpzh CCA/2 tphz OHA OH 0.15 OLTAGE WAEFORMS PROPAGATION DELAY TIMES OLTAGE WAEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2 ns, tf 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 2. Load Circuit and oltage Waveforms 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 PARAMETER MEASUREMENT INFORMATION CCA = 3.3 ± 0.3 TO CCB = 5 ± 0.5 From Under Test CL = 50 pf (see Note A) 2 CCB TEST tpd tplz/tpzl tphz/tpzh 2 CCB LOAD CIRCUIT Control (low-level enabling) 2.7 tpzl tplz Input 2.7 Waveform 1 at 2 CCB 50% CCB CCB 20% CCB OL tplh tphl OH 50% CCB 50% CCB OL Waveform 2 at tpzh 50% CCB tphz OH 80% CCB OLTAGE WAEFORMS PROPAGATION DELAY TIMES OLTAGE WAEFORMS ENABLE AND DISABLE TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 3. Load Circuit and oltage Waveforms POST OFFICE BOX DALLAS, TEXAS

10 PARAMETER MEASUREMENT INFORMATION CCB = 5 ± 0.5 TO CCA = 2.7 AND 3.3 ± 0.3 From Under Test CL = 50 pf (see Note A) CCA = 6 TEST tpd tplz/tpzl tphz/tpzh CCA = 6 LOAD CIRCUIT Control (low-level enabling) 3 tpzl tplz Input tplh tphl OLTAGE WAEFORMS PROPAGATION DELAY TIMES 3 OHA OLA Waveform 1 at 6 Waveform 2 at tpzh OLTAGE WAEFORMS ENABLE AND DISABLE TIMES OL OLA tphz 3 OHA OH 0.3 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tplz and tphz are the same as tdis. F. tpzl and tpzh are the same as ten. G. tplh and tphl are the same as tpd. Figure 4. Load Circuit and oltage Waveforms 10 POST OFFICE BOX DALLAS, TEXAS 75265

13 MECHANICAL DATA MSSO001C JANUARY 1995 REISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN (0,635) (0,343) (0,203) (0,13) M (0,25) (0,13) (7,59) (7,39) (10,67) (10,03) Gage Plane (0,25) 1 A (1,02) (0,51) (2,79) MAX (0,20) MIN Seating Plane (0,10) DIM PINS ** A MAX (9,65) (16,00) (18,54) A MIN (9,40) (15,75) (18,29) / E 12/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed (0,15). D. Falls within JEDEC MO-118 POST OFFICE BOX DALLAS, TEXAS 75265

14 MECHANICAL DATA MTSS003D JANUARY 1995 REISED JANUARY 1998 DGG (R-PDSO-G**) 48 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,50 0,27 0,17 0,08 M ,20 8,30 6,00 7,90 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16, / F 12/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

15 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony ideo & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2003, Texas Instruments Incorporated

ORDERING INFORMATION PACKAGE

ORDERING INFORMATION PACKAGE Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 description This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has