SN54LV4052A, SN74LV4052A DUAL 4-CHANNEL ANALOG MULTIPLEXERS/DEMULTIPLEXERS

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1 2-V to 5.5-V V CC Operation Support Mixed-Mode Voltage Operation on All Ports Fast Switching High On-Off Output-Voltage Ratio Low Crosstalk Between Switches Extremely Low Input Current Latch-Up Performance Exceeds 100 ma Per JESD 78, Class II ESD Protection Exceeds JESD V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) SN54LV4052A...J OR W PACKAGE SN74LV4052A... D, DB, DGV, N, NS, OR PW PACKAGE (TOP VIEW) 2Y0 2Y2 2-COM 2Y3 2Y V CC 1Y2 1Y1 1-COM 1Y0 1Y3 A B SN74LV4052A... RGY PACKAGE (TOP VIEW) description/ordering information These dual 4-channel CMOS analog multiplexers/demultiplexers are designed for 2-V to 5.5-V V CC operation. The LV4052A devices handle both analog and digital signals. Each channel permits signals with amplitudes up to 5.5 V (peak) to be transmitted in either direction. Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-toanalog conversion systems. 2Y2 2-COM 2Y3 2Y Y CC B V Y2 1Y1 1-COM 1Y0 1Y3 A TA ORDERING INFORMATION PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP N Tube of 25 SN74LV4052AN SN74LV4052AN QFN RGY Reel of 1000 SN74LV4052ARGYR LW052A SOIC D Tube of 40 SN74LV4052AD Reel of 2500 SN74LV4052ADR LV4052A 40 C to 85 C SOP NS Reel of 2000 SN74LV4052ANSR 74LV4052A SSOP DB Reel of 2000 SN74LV4052ADBR LW052A Tube of 90 SN74LV4052APW TSSOP PW Reel of 2000 SN74LV4052APWR LW052A Reel of 250 SN74LV4052APWT TVSOP DGV Reel of 2000 SN74LV4052ADGVR LW052A 55 C to 125 C CDIP J Tube of 25 SNJ54LV4052AJ SNJ54LV4052AJ CFP W Tube of 150 SNJ54LV4052AW SNJ54LV4052AW Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright 2003, Texas Instruments Incorporated POST OFFICE BOX DALLAS, TEXAS

2 FUNCTION TABLE INPUTS ON B A CHANNEL L L L 1Y0, 2Y0 L L H 1Y1, 2Y1 L H L 1Y2, 2Y2 L H H 1Y3, 2Y3 H X X None logic diagram (positive logic) 13 1-COM A Y0 1Y1 15 1Y2 B Y3 1 2Y0 5 2Y1 2 2Y Y3 3 2-COM 2 POST OFFICE BOX DALLAS, TEXAS 75265

3 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V CC V to 7.0 V Input voltage range, V I (see Note 1) V to 7.0 V Switch I/O voltage range, V IO (see Notes 1 and 2) V to V CC V Input clamp current, I IK (V I < 0) ma I/O diode current, I IOK (V IO < 0 or V IO > V CC ) ±50 ma Switch through current, I T (V IO = 0 to V CC ) ±25 ma Continuous current through V CC or ±50 ma Package thermal impedance, θ JA (see Note 3): D package C/W (see Note 3): DB package C/W (see Note 3): DGV package C/W (see Note 3): N package C/W (see Note 3): NS package C/W (see Note 3): PW package C/W (see Note 4): RGY package C/W Storage temperature range, T stg C to 150 C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The package thermal impedance is calculated in accordance with JESD The package thermal impedance is calculated in accordance with JESD recommended operating conditions (see Note 5) SN54LV4052A SN74LV4052A UNIT MIN MAX MIN MAX Supply voltage V VIH VIL = 2 V High-level input voltage, = 2.3 V to 2.7 V control inputs = 3 V to 3.6 V = 4.5 V to 5.5 V = 2 V Low-level input voltage, = 2.3 V to 2.7 V control inputs = 3 V to 3.6 V = 4.5 V to 5.5 V VI Control input voltage V VIO Input/output voltage 0 0 V = 2.3 V to 2.7 V t/ v Input transition rise or fall rate = 3 V to 3.6 V ns/v = 4.5 V to 5.5 V TA Operating free-air temperature C With supply voltages at or near 2 V, the analog switch on-state resistance becomes very nonlinear. It is recommended that only digital signals be transmitted at these low supply voltages. NOTE 5: All unused inputs of the device must be held at or to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. V V PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DALLAS, TEXAS

4 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS TA = 25 C SN54LV4052A SN74LV4052A MIN TYP MAX MIN MAX MIN MAX IT = 2 ma, 2.3 V On-state VI = or, ron 3 V Ω switch resistance V = VIL (see Figure 1) 4.5 V V Peak IT = 2 ma, ron(p) VI = to, 3 V Ω on-state resistance V = VIL 4.5 V UNIT ron Difference in on-state resistance between switches 2.3 V IT = 2 ma, VI I = to, 3 V Ω V = VIL 4.5 V II Control input current VI = 5.5 V or IS(off) IS(on) Off-state switch leakage current On-state switch leakage current VI = and =, or VI = and =, V = VIH (see Figure 2) VI = or, V = VIL (see Figure 3) 0 to 5.5 V ±0.1 ±1 ±1 µa 5.5 V ±0.1 ±1 ±1 µa 5.5 V ±0.1 ±1 ±1 µa ICC Supply current VI = or 5.5 V µa CIC CIS COS CF Control input capacitance Common terminal capacitance Switch terminal capacitance Feedthrough capacitance f = 10 MHz 3.3 V 2.1 pf 3.3 V 13.1 pf 3.3 V 5.6 pf 3.3 V 0.5 pf PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX DALLAS, TEXAS 75265

5 switching characteristics over recommended operating free-air temperature range, V CC = 2.5 V ± 0.2 V (unless otherwise noted) tplh tphl tpzh tpzl tphz tplz tplh tphl tpzh tpzl tphz tplz PARAMETER Propagation Enable Disable Propagation Enable Disable FROM TO TEST TA = 25 C SN54LV4052A SN74LV4052A (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX Y or COM C L = 15 pf, (see Figure 4) CL = 15 pf, CL = 15 pf, Y or COM C L = 50 pf, (see Figure 4) CL = 50 pf, CL = 50 pf, UNIT ns ns ns ns ns ns switching characteristics over recommended operating free-air temperature range, V CC = 3.3 V ± 0.3 V (unless otherwise noted) tplh tphl tpzh tpzl tphz tplz tplh tphl tpzh tpzl tphz tplz PARAMETER Propagation Enable Disable Propagation Enable Disable FROM TO TEST TA = 25 C SN54LV4052A SN74LV4052A (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX Y or COM C L = 15 pf, (see Figure 4) CL = 15 pf, CL = 15 pf, Y or COM C L = 50 pf, (see Figure 4) CL = 50 pf, CL = 50 pf, UNIT ns ns ns ns ns ns PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX DALLAS, TEXAS

6 switching characteristics over recommended operating free-air temperature range, V CC = 5 V ± 0.5 V (unless otherwise noted) tplh tphl tpzh tpzl tphz tplz tplh tphl tpzh tpzl tphz tplz PARAMETER Propagation Enable Disable Propagation Enable Disable FROM TO TEST TA = 25 C SN54LV4052A SN74LV4052A (INPUT) (OUTPUT) CONDITIONS MIN TYP MAX MIN MAX MIN MAX Y or COM C L = 15 pf, (see Figure 4) CL = 15 pf, CL = 15 pf, Y or COM C L = 50 pf, (see Figure 4) CL = 50 pf, CL = 50 pf, UNIT ns ns ns ns ns ns analog switch characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER Frequency response (switch on) Crosstalk (between any switches) Crosstalk (control input to signal output) Feedthrough attenuation (switch off) FROM TO TEST (INPUT) (OUTPUT) CONDITIONS Y or COM Y or COM Y or COM Sine-wave distortion Y or COM NOTES: TA = 25 C MIN TYP MAX UNIT CL = 50 pf, 2.3 V 30 RL = 600 Ω, 3 V 35 MHz fin = 1 MHz (sine wave) (see Note 6 and Figure 6) 4.5 V 50 CL = 50 pf, 2.3 V 45 RL = 600 Ω, 3 V 45 db fin = 1 MHz (sine wave) (see Note 7 and Figure 7) 4.5 V 45 CL = 50 pf, 2.3 V 20 RL = 600 Ω, 3 V 35 mv fin = 1 MHz (square wave) (see Figure 8) 4.5 V 65 CL L = 50 pf, 2.3 V 45 RL = 600 Ω, 3 V 45 db fin = 1 MHz (sine wave) (see Note 7 and Figure 9) 4.5 V 45 CL = 50 pf, VI = 2 Vp-p 2.3 V 0.1 RL = 10 kω, fin = 1 khz VI = 2.5 Vp-p 3 V 0.1 % (sine wave) (see Figure 10) VI = 4 Vp-p 4.5 V Adjust fin voltage to obtain 0 dbm at output. Increase fin frequency until db meter reads 3 db. 7. Adjust fin voltage to obtain 0 dbm at input. operating characteristics, T A = 25 C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance CL = 50 pf, f = 10 MHz 11.8 pf PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX DALLAS, TEXAS 75265

7 PARAMETER MEASUREMENT INFORMATION V = VIL VI = or (ON) r on V I V O ma V VI Figure 1. On-State Resistance Test Circuit V = VIH VI A (OFF) Condition 1: VI = 0, = Condition 2: VI =, = 0 Figure 2. Off-State Switch Leakage-Current Test Circuit V = VIL VI A (ON) Open VI = or Figure 3. On-State Switch Leakage-Current Test Circuit POST OFFICE BOX DALLAS, TEXAS

8 PARAMETER MEASUREMENT INFORMATION V = VIL Input (ON) Output 50 Ω CL Figure 4. Propagation Delay Time, Signal Input to Signal Output 50 Ω V TEST S1 S2 S1 VI RL = 1 kω S2 tplz/tpzl tphz/tpzh CL TEST CIRCUIT V 0 V 50% V 0 V 50% tpzl tpzh 50% L (tpzl, tpzh) H 0 V 50% V 0 V 50% V 0 V 50% tplz tphz L L V (tplz, tphz) H 0 V H 0.3 V LTAGE WAVEFORMS Figure 5. Switching Time (t PZL, t PLZ, t PZH, t PHZ ), Control to Signal Output 8 POST OFFICE BOX DALLAS, TEXAS 75265

9 PARAMETER MEASUREMENT INFORMATION V = fin 50 Ω 0.1 µf V I (ON) RL = 600 Ω CL = 50 pf /2 NOTE A: fin is a sine wave. Figure 6. Frequency Response (Switch On) V = fin 50 Ω 0.1 µf 600 Ω VI (ON) RL = 600 Ω 1 CL = 50 pf /2 V = 600 Ω (OFF) RL = 600 Ω 2 CL = 50 pf /2 Figure 7. Crosstalk Between Any Two Switches 50 Ω V fin 600 Ω RL = 600 Ω CL = 50 pf /2 /2 Figure 8. Crosstalk Between Control Input and Switch Output POST OFFICE BOX DALLAS, TEXAS

10 PARAMETER MEASUREMENT INFORMATION V = fin 50 Ω 0.1 µf 600 Ω VI (OFF) RL = 600 Ω CL = 50 pf /2 /2 Figure 9. Feedthrough Attenuation (Switch Off) V = fin 600 Ω 10 µf VI (ON) RL = 10 kω CL = 50 pf /2 Figure 10. Sine-Wave Distortion 10 POST OFFICE BOX DALLAS, TEXAS 75265

12 MECHANICAL DATA MPDS006C FEBRUARY 1996 REVISED AUGUST 2000 DGV (R-PDSO-G**) 24 PINS SHOWN PLASTIC SMALL-OUTLINE 0,40 0,23 0,13 0,07 M ,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 1 12 A 0 8 0,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,08 DIM PINS ** A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11, /E 08/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins MO /16/20/56 Pins MO-194 POST OFFICE BOX DALLAS, TEXAS 75265

16 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

17 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

18 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio Data Converters dataconverter.ti.com Automotive DSP dsp.ti.com Broadband Interface interface.ti.com Digital Control Logic logic.ti.com Military Power Mgmt power.ti.com Optical Networking Microcontrollers microcontroller.ti.com Security Telephony Video & Imaging Wireless Mailing Address: Texas Instruments Post Office Box Dallas, Texas Copyright 2004, Texas Instruments Incorporated

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE

1OE 3B V GND ORDERING INFORMATION. TOP-SIDE MARKING QFN RGY Tape and reel SN74CBTLV3126RGYR CL126 PACKAGE SN74CBTLV326 LOW-VOLTAGE QUADRUPLE FET BUS SWITCH SCDS03H DECEMBER 997 REVISED APRIL 2003 Standard 26-Type Pinout 5-Ω Switch Connection Between Two Ports Isolation Under Power-Off Conditions Latch-up Performance