CD54ACT74, CD74ACT74 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET
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1 s Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Drive urrent Fanout to 5 F Devices SR-Latchup-Resistant MOS Process and ircuit Design Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 305 D54AT74...F PAKAGE D74AT74...E OR M PAKAGE (TOP VIEW) LR D LK PRE Q Q GND V 2LR 2D 2LK 2PRE 2Q 2Q description/ordering information The AT74 dual positive-edge-triggered devices are D-type flip-flops. A low level at the preset (PRE) or clear (LR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and LR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. lock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. TA ORDERING INFORMATION PAKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP E Tube D74AT74E D74AT74E Tube D74AT74M 55 to25 SOI M AT74M Tape and reel D74AT74M96 DIP F Tube D54AT74F3A D54AT74F3A Package drawings, standard packing quantities, thermal data, symbolization, and PB design guidelines are available at FUNTION TABLE (each flip-flop) INPUTS OUTPUTS PRE LR LK D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q0 Q0 This configuration is nonstable; that is, it does not persist when PRE or LR returns to its inactive (high) level. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. opyright 2002, Texas Instruments Incorporated On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
2 logic diagram, each flip-flop (positive logic) PRE LK TG Q D TG TG TG Q LR absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V V to 6 V clamp current, I IK (V I < 0 or V I > V ) (see Note ) ±20 ma clamp current, I OK (V O < 0 or V O > V ) (see Note ) ±50 ma ontinuous output current, I O (V O = 0 to V ) ±50 ma ontinuous current through V or GND ±00 ma Package thermal impedance, θ JA (see Note 2): E package /W M package /W Storage temperature range, T stg to 50 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES:. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 5-7. recommended operating conditions (see Note 3) TA = to to 85 UNIT MIN MAX MIN MAX MIN MAX V Supply voltage V VIH High-level input voltage V VIL Low-level input voltage V VI voltage V VO voltage V IOH High-level output current ma IOL Low-level output current ma t/ v transition rise or fall rate ns/v NOTE 3: All unused inputs of the device must be held at V or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating MOS s, literature number SBA004. 2
3 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST ONDITIONS V VOH VOL VI =VIH or VIL VI =VIH or VIL TA = to to 85 UNIT MIN MAX MIN MAX MIN MAX IOH = 50 µa 4.5 V IOH = 24 ma 4.5 V IOH = 50 ma 5.5 V 3.85 IOH = 75 ma 5.5 V 3.85 IOL = 50 µa 4.5 V IOL = 24 ma 4.5 V IOL = 50 ma 5.5 V.65 IOL = 75 ma 5.5 V.65 II VI = V or GND 5.5 V ±0. ± ± µa I VI = V or GND, IO = V µa I V I = V 2. V 4.5 V to 5.5 V ma i pf Test one output at a time, not exceeding -second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85 and 75-Ω transmission-line drive capability at 25. Additional quiescent supply current per input pin, TTL inputs high, unit load V V AT INPUT LOAD TABLE INPUT UNIT LOAD Data 0.53 PRE or LR 0.58 LK Unit load is I limit specified in electrical characteristics table (e.g., 2.4 ma at 25 ). timing requirements over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) 55 to to 85 UNIT MIN MAX MIN MAX fclock lock frequency MHz tw Pulse duration PRE or LR low LK ns tsu Setup time Data ns PRE or LR inactive ns th Hold time Data after LK 0 0 ns trec Recovery time, before LK LR or PRE ns 3
4 switching characteristics over recommended operating free-air temperature range, V = 5 V ± 0.5 V (unless otherwise noted) (see Figure ) PARAMETER FROM (INPUT) TO (OUTPUT) 55 to to 85 UNIT MIN MAX MIN MAX fmax MHz tplh tphl tplh tphl LK Q or Q PRE or LR QorQ Q ns ns operating characteristics, V = 5 V, T A = 25 PARAMETER TYP UNIT pd Power dissipation capacitance 55 pf 4
5 PARAMETER MEASUREMENT INFORMATION From Under Test L = 50 pf (see Note A) R = 500 Ω R2 = 500 Ω S 2 V GND Open TEST tplh/tphl tplz/tpzl tphz/tpzh S Open 2 V GND tw LOAD IRUIT.5 V.5 V PULSE DURATION LR.5 V Reference tsu.5 V th LK.5 V trec Data.5 V 0% 90% 90% tr.5 V 0% tf In-Phase Out-of-Phase REOVERY TIME.5 V.5 V tplh 50% 0% tphl 90% 90% 90% VOH 50% V 0% VOL tf PROPAGATION DELAY AND OUTPUT TRANSITION TIMES tr tphl 50% V 50% 0% 0% tf tplh VOH 90% VOL tr SETUP AND HOLD AND INPUT RISE AND FALL TIMES ontrol Waveform S at 2 V (see Note B) Waveform 2 S at GND (see Note B) tpzl tpzh.5 V.5 V tplz V 20% V 20% V VOL 80% V tphz OUTPUT ENABLE AND DISABLE TIMES VOH 80% V NOTES: A. L includes probe and test-fixture capacitance. B. Waveform is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.. All input pulses are supplied by generators having the following characteristics: PRR MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tplh and tphl are the same as tpd. G. tpzl and tpzh are the same as ten. H. tplz and tphz are the same as tdis. Figure. Load ircuit and Voltage Waveforms 5
6
7 MPDI002 JANUARY 995 REVISED DEEMBER N (R-PDIP-T**) 6 PINS SHOWN PLASTI DUAL-IN-LINE PAKAGE DIM PINS ** A A MAX (9,69) (9,69) (23,37).060 (26,92) 6 9 A MIN (8,92) (8,92) (2,59) (23,88) (6,60) (6,0) MS-00 VARIATION AA BB A AD (,78) (,4) D (,4) (0,76) D (0,5) MIN (8,26) (7,62) 0.05 (0,38) (5,08) MAX Gauge Plane Seating Plane 0.25 (3,8) MIN 0.00 (0,25) NOM 0.02 (0,53) 0.05 (0,38) 0.00 (0,25) 0.00 (2,54) M (0,92) MAX 4/8 PIN ONLY 20 pin vendor option D /E 2/2002 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Falls within JEDE MS-00, except 8 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.
8 MEHANIAL DATA MSOI002B JANUARY 995 REVISED SEPTEMBER 200 D (R-PDSO-G**) PLASTI SMALL-OUTLINE PAKAGE 8 PINS SHOWN (,27) (0,5) 0.04 (0,35) 0.00 (0,25) (6,20) (5,80) (0,20) NOM 0.57 (4,00) 0.50 (3,8) Gage Plane 4 A (0,25) (,2) 0.06 (0,40) Seating Plane (,75) MAX 0.00 (0,25) (0,0) (0,0) DIM PINS ** A MAX 0.97 (5,00) (8,75) (0,00) A MIN (4,80) (8,55) (9,80) /E 09/0 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice.. Body dimensions do not include mold flash or protrusion, not to exceed (0,5). D. Falls within JEDE MS-02
9 IMPORTANT NOTIE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. ustomers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. ustomers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Mailing Address: Texas Instruments Post Office Box Dallas, Texas opyright 2003, Texas Instruments Incorporated
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74A7 Eight Latches in a Single Package -State Bus-Driving True s Full Parallel Access for Loading Buffered Control Inputs Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio
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Inputs Are TTL Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Optio Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and DIP (N)
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Operation From Very Slow Input Transitions Temperature-Compensated Threshold Levels High Noise Immunity Same Pinouts as HC00 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB),
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Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
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Operating Range of 2 V to 5.5 V Max t pd of 10 at 5 V Low Power Coumption, 10-µ Max I CC ±8-m Drive at 5 V Latch-Up Performance Exceeds 250 m Per JESD 17 description/ordering information DBV OR DCK PCKGE
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HIH-SPEED DIFFERENTIAL LINE DRIVER Designed for Signaling Rates Up to 5 Mbps Low-Voltage Differential Signaling With Typical Output Voltage of 7 mv and a -Ω Load Propagation Delay Time of. ns, Typical
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Operates With Single 5-V Power Supply LinBiCMOS Process Technology Two Drivers and Two Receivers ± 30-V Input Levels Low Supply Current...8 ma Typical Meets or Exceeds TIA/EIA-232-F and ITU Recommendation
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Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
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74ACT62 Independent Registers and Enables for A and B Buses Multiplexed Real-Time and Stored Data Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed Switching
More informationPRODUCT PREVIEW SN54AHCT257, SN74AHCT257 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS. description
Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), Thin Shrink
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Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
More informationdescription V CC 2CLR 2D 2CLK 2PRE 2Q 2Q 1CLR 1D 1CLK 1PRE 1Q 1Q GND 2CLR 1CLR 1CLK NC 1PRE NC 1Q 2CLK 2PRE GND
Package Optio Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs TYPE TYPICAL MAXIMUM CLOCK FREUEY (CL = 0 pf) (MHz) TYPICAL POWER
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Dependable Texas Instruments Quality and Reliability description/ordering information These devices contain six independent inverters. SN5404... J PACKAGE SN54LS04, SN54S04... J OR W PACKAGE SN7404, SN74S04...
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SNALS0, SNAS0, SN7ALS0, SN7AS0 Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain
More information54AC16245, 74AC BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
4AC64, 74AC64 6-BIT BUS TRANSCEIVERS SCAS3A MARCH 990 REVISED APRIL 996 Members of the Texas Itruments Widebus Family 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture
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Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
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SN78 Meets or Exceeds the Requirements of ANSI EIA/TIA--B and ITU Recommendation V. Single -V Supply Balanced-Line Operation TTL Compatible High Output Impedance in Power-Off Condition High-Current Active-Pullup
More informationdescription/ordering information
Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 ±24-mA Drive at 3.3 Latch-Up Performance Exceeds 250 ma Per JESD 17 description/ordering information This 16-bit (dual-octal) noninverting
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Compatible With IEEE Std 1194.1-1991 (TL) TTL A Port, ackplane Traceiver Logic (TL) Port Open-Collector -Port Outputs Sink 100 ma IAS V CC Pin Minimizes Signal Distortion During Live Iertion or Withdrawal
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Compare Two -Bit Words Totem-Pole Outputs () ALS Are Identical to ALS2 Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J)
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Inputs Are TTL-Voltage ompatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power onsumption Balanced Propagation Delays ±24-mA Output Drive urrent Fanout to 15 F Devices SR-Latchup-Resistant
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SCLS07B DECEMBER 92 REVISED MAY 997 Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK),
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Members of the Texas Itruments Widebus Family Inputs Are TTL-Voltage Compatible 3-State Bus Driving True s Full Parallel Access for Loading Flow-Through Architecture Optimizes PCB Layout Distributed and
More informationSN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
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Featuring Unitrode L and LD Products Now From Texas Instruments Wide Supply-Voltage Range:.5 V to V Separate Input-Logic Supply Internal ESD Protection Thermal Shutdown High-Noise-Immunity Inputs Functional
More informationSN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
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Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current Fanout to 15 F Devices SCR-Latchup-Resistant
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Member of the Texas Itruments idebus Family Load Clock and Unload Clock Can Be Asynchronous or Coincident 256 ords by 18 Bits Low-Power Advanced CMOS Technology Full, Empty, and Half-Full Flags Programmable
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Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
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Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 00-mil DIPs description These devices contain four independent 2-input positive-nand
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SCES JULY Control Inputs V IH /V IL Levels are Referenced to V CCA Voltage V CC Isolation Feature If Either V CC Input Is at, Both Ports Are in the High-Impedance State Overvoltage-Tolerant Inputs/Outputs
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WITH CLEA SDAS2A APIL 92 EVISED DECEMBE 99 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
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Members of the Texas Instruments Widebus Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input
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SCAS032A JUL 187 REVISED APRIL 13 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and Configuratio Minimize High-Speed
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3-State Buffer-Type Outputs Drive Bus Lines Directly Bus-Structured Pinout Package Optio Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs
More informationDistributed by: www.jameco.com -800-83-4242 The content and copyrights of the attached material are the property of its owner. SN54HC393, SN74HC393 DUAL 4-BIT BINARY COUNTERS Wide Operating Voltage Range
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The ULN2A is obsolete 5-mA-Rated Collector Current (Single ) High-Voltage s... 5 V Clamp Diodes ULN2A, ULN22A, ULN23A, ULN24A, ULQ23A, ULQ24A SLRS2F DECEMBER 96 REVISED FEBRUARY 23 Inputs Compatible With
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Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
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Operation From Very Slow Edges Improved Line-Receiving Characteristics High Noise Immunity SN5414, SN54LS14, SN5414, SN54LS14...J OR W PACKAGE SN7414... D, N, OR NS PACKAGE SN74LS14... D, DB, OR N PACKAGE
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Dual Versions of Highly Stable SN542 and SN742 One Shots SN5422 and SN7422 Demonstrate Electrical and Switching Characteristics That Are Virtually Identical to the SN542 and SN742 One Shots Pinout Is Identical
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AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA
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3-TERMINAL ABLE REGULATOR Output Voltage Range Adjustable From 1.25 V to 37 V Output Current Greater Than 1.5 A Internal Short-Circuit Current Limiting Thermal Overload Protection Output Safe-Area Compensation
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