CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

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CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January 1998 - Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers,

1 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Data sheet acquired from Harris Semiconductor SCHS189C January Revised July 2004 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State Features Description [ /Title (CD74 HC540, CD74 HCT54 0, CD74 HC541, CD74 HCT54 HC540, CD74HCT Inverting HC541, HCT Non-Inverting Buffered Inputs Three-State Outputs Bus Line Driving Capability Typical Propagation Delay = 9ns at V CC = 5V, C L = 15pF, T A = 25 o C Fanout (Over Temperature Range) - Standard Outputs LSTTL Loads - Bus Driver Outputs LSTTL Loads Wide Operating Temperature Range o C to 125 o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: N IL = 30%, N IH = 30% of V CC at V CC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.8V (Max), V IH = 2V (Min) - CMOS Input Compatibility, I l 1µA at V OL, V OH The HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The HC541 and HCT541 are Non- Inverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CD54HC540F3A -55 to Ld CERDIP CD54HC541F3A -55 to Ld CERDIP CD54HCT541F3A -55 to Ld CERDIP CD74HC540E -55 to Ld PDIP CD74HC540M -55 to Ld SOIC CD74HC540M96-55 to Ld SOIC CD74HC541E -55 to Ld PDIP CD74HC541M -55 to Ld SOIC CD74HC541M96-55 to Ld SOIC CD74HC541PW -55 to Ld TSSOP CD74HC541PWR -55 to Ld TSSOP CD74HCT540E -55 to Ld PDIP CD74HCT540M -55 to Ld SOIC CD74HCT540M96-55 to Ld SOIC CD74HCT541E -55 to Ld PDIP CD74HCT541M -55 to Ld SOIC CD74HCT541M96-55 to Ld SOIC NOTE: When ordering, use the entire part number. The suffix 96 denotes tape and reel. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 2004, Texas Instruments Incorporated 1

2 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Pinouts CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW OE A0 A1 A2 A3 A4 A5 A6 A V CC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 CD54HC541, CD54HCT541 (CERDIP) CD74HC541 (PDIP, SOIC, TSSOP) CD74HCT541 (PDIP, SOIC) TOP VIEW OE1 A0 A1 A2 A3 A4 A5 A6 A V CC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7 Functional Diagram OE A OE B D 0 Y0 Y 0 D 1 Y 1 Y 1 D 2 Y 2 Y 2 D 3 Y 3 Y 3 D 4 Y 4 Y 4 D 5 Y 5 Y 5 D 6 Y 6 Y 6 D 7 Y 7 Y 7 2

3 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 TRUTH TABLE INPUTS OUTPUTS OE1 OE2 An L L H L H H X X Z Z X H X Z Z L L L H L H = HIGH Level L = LOW Level X= Don t Care Z = High Impedance 3

4 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Absolute Maximum Ratings DC Supply, V CC V to 7V DC Input Diode Current, I IK For V I < -0.5V or V I > V CC + 0.5V ±20mA DC Output Diode Current, I OK For V O < -0.5V or V O > V CC + 0.5V ±20mA DC Drain Current, per Output, I O For -0.5V < V O < V CC + 0.5V ±35mA DC Output Source or Sink Current per Output Pin, I O For V O > -0.5V or V O < V CC + 0.5V ±25mA DC V CC or Ground Current, I CC ±50mA Thermal Information Thermal Resistance (Typical, Note 1) θ JA ( o C/W) E (PDIP) Package M (SOIC) Package PW (TSSOP) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 150 o C Maximum Lead Temperature (Soldering 10s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to 125 o C Supply Range, V CC HC Types V to 6V HCT Types V to 5.5V DC Input or Output, V I, V O V to V CC Input Rise and Fall Time 2V ns (Max) 4.5V ns (Max) 6V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD DC Electrical Specifications PARAMETER HC TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current SYMBOL TEST CONDITIONS V CC 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V IH or V IL V V V UNITS V V V V OL V IH or V IL V V V I I V CC or V V V ±0.1 - ±1 - ±1 µa 4

5 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 DC Electrical Specifications (Continued) PARAMETER Quiescent Device Current Three- State Leakage Current HCT TYPES High Level Input Low Level Input High Level Output CMOS Loads High Level Output TTL Loads Low Level Output CMOS Loads Low Level Output TTL Loads Input Leakage Current Quiescent Device Current Three- State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load SYMBOL I CC V CC or I OZ V IL or V IH V O = V CC or V IH to 5.5 V IL to µa ±0.5 - ±5.0 - ±10 µa V V V OH V IH or V IL V V V OL V IH or V IL V I I I CC V CC and V CC or I OZ V IL or V IH V O = V CC or I CC (Note 2) TEST CONDITIONS V CC 25 o C -40 o C TO 85 o C -55 o C TO 125 o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V CC V ±0.1 - ±1 - ±1 µa µa to ±0.5 - ±5.0 - ±10 µa NOTE: 2. For dual-supply systems theoretical worst case (V I = 2.4V, V CC = 5.5V) specification is 1.8mA. HCT Input Loading Table UNIT LOADS UNITS µa INPUT HCT540 HCT541 A0 - A OE OE NOTE: Unit Load is I CC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25 o C. 5

6 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Switching Specifications C L = 50pF, Input t r, t f = 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS HC TYPES Propagation Delay t PLH, t PHL C L = 50pF Data to Outputs (540) ns ns C L = 15pF ns C L = 50pF ns Data to Outputs (541) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Enable and Disable to Outputs (540) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Enable and Disable to Outputs (541) t PLZ,t PHZ C L = 50pF ns ns C L = 15pF ns C L = 50pF ns Output Transition Time t THL, t TLH C L = 50pF ns ns ns Input Capacitance C I C L = 50pF pf Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) (540) Power Dissipation Capacitance (Notes 3, 4) (541) C O pf C PD C L = 15pF pf C PD C L = 15pF pf HCT TYPES Propagation Delay t PHL, t PLH Data to Outputs (540) C L = 50pF ns C L = 15pF ns Data to Outputs (541) t PHL, t PLH C L = 50pF ns C L = 15pF ns Output Enable and Disable to Outputs (540, 541) t PLZ,t PHZ C L = 50pF ns C L = 15pF ns Output Transition Time t TLH, t THL C L = 50pF ns Input Capacitance C I C L = 50pF pf 6

7 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Switching Specifications C L = 50pF, Input t r, t f = 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25 o C -40 o C TO 85 o C -55 o C TO 125 o C MIN TYP MAX MIN MAX MIN MAX UNITS Three-State Output Capacitance Power Dissipation Capacitance (Notes 3, 4) (540, 541) C O pf C PD C L = 15pF pf NOTES: 3. C PD is used to determine the dynamic power consumption, per channel. 4. P D = V 2 CC f i (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, V CC = Supply. Test Circuits and Waveforms t r = 6ns t f = 6ns t r = 6ns t f = 6ns INPUT 90% 50% 10% V CC INPUT 2.7V 1.3V 0.3V 3V t THL t TLH t THL t TLH INVERTING OUTPUT t PHL t PLH 90% 50% 10% INVERTING OUTPUT t PHL t PLH 90% 1.3V 10% FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC 6ns OUTPUT DISABLE 50% 90% 10% 6ns V CC t r OUTPUT DISABLE 6ns t f ns 3V tplz t PZL t PLZ t PZL OUTPUT LOW TO OFF 10% 50% OUTPUT LOW TO OFF 10% 1.3V OUTPUT HIGH TO OFF t PHZ 90% t PZH 50% OUTPUT HIGH TO OFF t PHZ 90% t PZH 1.3V OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED OUTPUTS ENABLED OUTPUTS DISABLED OUTPUTS ENABLED FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM 7

8 Test Circuits and Waveforms (Continued) OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREE- STATE OUTPUT OUTPUT R L = 1kΩ C L 50pF V CC FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =1kΩ to V CC, C L = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT 8

12 MECHANICAL DATA MSSO002E JANUARY 1995 REVISED DECEMBER 2001 DB (R-PDSO-G**) 28 PINS SHOWN PLASTIC SMALL-OUTLINE 0,65 0,38 0,22 0,15 M ,60 5,00 8,20 7,40 0,25 0,09 Gage Plane ,25 A 0 8 0,95 0,55 2,00 MAX 0,05 MIN Seating Plane 0,10 DIM PINS ** A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12, /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX DALLAS, TEXAS 75265

13 MECHANICAL DATA MTSS001C JANUARY 1995 REVISED FEBRUARY 1999 PW (R-PDSO-G**) 14 PINS SHOWN PLASTIC SMALL-OUTLINE PACKAGE 0,30 0,65 0,10 M 0, ,50 4,30 6,60 6,20 0,15 NOM Gage Plane 1 A ,25 0,75 0,50 1,20 MAX 0,15 0,05 Seating Plane 0,10 DIM PINS ** A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9, /F 01/97 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153 POST OFFICE BOX DALLAS, TEXAS 75265

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CD54HC221, CD74HC221, CD74HCT221. High-Speed CMOS Logic Dual Monostable Multivibrator with Reset. Features. Description

Data sheet acquired from Harris Semiconductor SCHS166F November 1997 - Revised October 2003 CD54HC221, CD74HC221, CD74HCT221 High-Speed CMOS Logic Dual Monostable Multivibrator with Reset Features Description