DATASHEET CD4066BMS. Description. Features. Pinout. Applications. CMOS Quad Bilateral Switch. Rev X.00 Page 1 of 9. Jan 13, Rev X.

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1 DATASHEET CMOS Quad Bilateral Switch Rev X. Features For Transmission or Multiplexing of Analog or Digital Signals High Voltage Types (V Rating) V Digital or.v Peak-to-Peak Switching Typical On-State Resistance for V Operation Switch On-State Resistance Matched to Within Over V Signal Input Range On-State Resistance Flat Over Full Peak-to-Peak Signal Range High On/Off Output Voltage Ratio - db Typ. at FIS = khz, RL = k High Degree of Linearity: <.% Distortion Typ. at FIS = khz, VIS = Vp-p, - V, RL = k Extremely Low Off-State Switch Leakage Resulting in Very Low Offset Current and High Effective Off-State Resistance: pa Typ. at - = V, T A = + o C Extremely High Control Input Impedance (Control Circuit Isolated from Signal Circuit): Typ. Low Crosstalk Between Switches: -db Typ. at FIS = MHz, RL = k Matched Control Input to Signal Output Capacitance: Reduces Output Signal Transients Description is a quad bilateral switch intended for the transmission or multiplexing of analog or digital signals. It is pin for pin compatible with CDB, but exhibits a much lower on state resistance. In addition, the on-state resistance is relatively constant over the full input signal range. The consists of four independent bilateral switches. A single control signal is required per switch. Both the p and the n device in a given switch are biased on or off simultaneously by the control signal. As shown in Figure, the well of the n channel device on each switch is either tied to the input when the switch is on or to when the switch is off. This configuration eliminates the variation of the switch transistor threshold voltage with input signal, and thus keeps the on-state resistance low over the full operating signal range. The advantages over single channel switches include peak input signal voltage swings equal to the full supply voltage, and more constant on-state impedance over the input signal range. For sample and hold applications, however, the CDB is recommended. The is supplied in these -lead outline packages: Braze Seal DIP Frit Seal DIP Ceramic Flatpack HQ HB HW Frequency Response, Switch on = MHz (Typ.) % Tested for Quiescent Current at V V, V and V Parametric Ratings Pinout TOP VIEW Meets All Requirements of JEDEC Tentative Standard No. B, Standard Specifications for Description of B Series CMOS Devices IN/OUT A Applications OUT/IN A OUT/IN B CONT A CONT D Analog Signal Switching/Multiplexing - Signal Gating - Modulator - Squelch Control - Demodulator - Chopper - Commutating Switch Digital Signal Switching/Multiplexing IN/OUT B CONT B CONT C IN/OUT D OUT/IN D OUT/IN C IN/OUT C Transmission Gate Logic Implementation Analog to Digital & Digital to Analog Conversion Digital Control of Frequency, Impedance, Phase, and Analog Signal Gain Rev X. Page of

2 Absolute Maximum Ratings DC Supply Voltage Range, () V to +V (Voltage Referenced to Terminals) Input Voltage Range, All Inputs V to +.V DC Input Current, Any One Input ma Operating Temperature Range o C to + o C Package Types D, F, K, H Storage Temperature Range (TSTG) o C to + o C Lead Temperature (During Soldering) o C At Distance / / Inch (.mm.mm) from case for s Maximum Reliability Information Thermal Resistance ja jc Ceramic DIP and FRIT Package..... o C/W o C/W Flatpack Package o C/W o C/W Maximum Package Power Dissipation (PD) at + o C For TA = - o C to + o C (Package Type D, F, K) mw For TA = + o C to + o C (Package Type D, F, K)..... Derate Linearity at mw/ o C to mw Device Dissipation per Output Transistor mw For TA = Full Package Temperature Range (All Package Types) Junction Temperature o C TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS GROUP A PARAMETER SYMBOL CONDITIONS (NOTE ) SUBGROUPS TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND + o C -. A + o C - A = V, VIN = or GND - o C -. A Input Leakage Current IIL VC = or GND + o C - - na + o C - - na - o C - - na Input Leakage Current IIH VC = or GND + o C - na + o C - na - o C - na Input/Output Leakage IOZL VC = V, VIS = V, = + o C - - na Current (Switch OFF) = V, VIS = V, = V + o C - - na = V - o C - - na IOZH = + o C - na + o C - na = V - o C - na On Resistance RON VC =, RL = kw = V + o C - RON returned to - / = V + o C - RON = V + o C - VIS = to On Resistance RON = V, + o C - - o C - On Resistance RON = V, + o C - - o C - On Resistance RON = V, + o C - - o C - Functional (Note ) F =.V, VIN = or GND = V, VIN = or GND + o C + o C VOH > / = V, VIN = or GND A + o C = V, VIN = or GND B - o C VOL < / Switch Threshold SWTHRH = V, VC =.V, VIS = GND,, + o C, + o C, - o C. - V RL = k to SWTHRH = V, VC = V, VIS = GND,, + o C, + o C, - o C. - V N Threshold Voltage VNTH = V, ISS = - A + o C V P Threshold Voltage VPTH = V, IDD = A + o C.. V V Rev X. Page of

3 Control Input Low Voltage (Note ) IIS < a, VIS =, = and VIS =, = Control Input High Voltage (Note, Figure ) VIS = and VIS = NOTES: TABLE. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS (NOTE ) VILC = V,, + o C, + o C, - o C - V VILC = V,, + o C, + o C, - o C - V VIHC = V, IIS =.ma,.v < <.V = V, IIS =.ma,.v < <.V = V, IIS =.ma,.v < <.V VIHC = V, IIS =.ma,.v < <.V = V, IIS =.ma,.v < <.V = V, IIS =.ma,.v < <.V. All voltages referenced to device GND, % testing being implemented.. Go/No Go test with limits applied to inputs. GROUP A SUBGROUPS TEMPERATURE + o C. - V + o C. - V - o C. - V + o C - V + o C - V - o C - V. =.V/.V, RL = K to = V/V, RL = K to MIN MAX UNITS TABLE. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off TPLH TPHL VC = = V, = GND (Notes, ) GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS + o C - ns, + o C, - o C - ns TPHZ/ZH VIS = = V (Notes, ) + o C - ns TPLZ/ZL, + o C, - o C - ns NOTES:. CL = pf, RL = K, Input TR, TF < ns.. - o C and + o C limits guaranteed, % testing being implemented.. CL = pf, RL = K, Input TR, TF < ns. TABLE. ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND, - o C, + o C -. A + o C -. A = V, VIN = or GND, - o C, + o C -. A + o C - A = V, VIN = or GND, - o C, + o C -. A + o C - A Control Input Low Voltage IIS < a, VIS =, = and VIS =, = Control Input High Voltage (See Figure ) VILC = V, + o C, + o C, - o C VIHC = V, VIS = or GND + o C, + o C, - o C - V - V Rev X. Page of

4 Propagation Delay Signal Input to Signal Output Propagation Delay Turn-On, Turn-Off TABLE. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE TPLH TPHL = V,, + o C - ns = V,, + o C - ns TPHZ/ZH = V,, + o C - ns TPLZ/ZL = V,, + o C - ns Input Capacitance CIN Any Input, + o C -. pf NOTES:. All voltages referenced to device GND.. The parameters listed on Table are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics.. CL = pf, RL = K, Input TR, TF < ns. MIN MAX UNITS TABLE. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS Supply Current IDD = V, VIN = or GND, + o C - A N Threshold Voltage VNTH = V, ISS = - A, + o C V N Threshold Voltage VTN = V, ISS = - A, + o C - V Delta P Threshold Voltage VTP = V, IDD = A, + o C.. V P Threshold Voltage VTP = V, IDD = A, + o C - V Delta Functional F = V, VIN = or GND = V, VIN = or GND + o C VOH > / Propagation Delay Time TPHL TPLH NOTES:. All voltages referenced to device GND.. CL = pf, RL = K, Input TR, TF < ns. VOL < / = V,,, + o C -. x + o C Limit. See Table for + o C limit.. Read and Record V ns TABLE. BURN-IN AND LIFE TEST DELTA PARAMETERS + O C PARAMETER SYMBOL DELTA LIMIT Supply Current - SSI IDD. A ON Resistance RONDEL % x Pre-Test Reading TABLE. APPLICABLE SUBGROUPS CONFORMANCE GROUP MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Initial Test (Pre Burn-In) %,, IDD, IOL, IOHA, RONDEL Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL PDA (Note ) %,,, Deltas Interim Test (Post Burn-In) %,, IDD, IOL, IOHA, RONDEL PDA (Note ) %,,, Deltas Final Test %,, A, B,, Group A Sample,,,, A, B,,, Group B Subgroup B- Sample,,,, A, B,,,, Deltas Subgroups,,,,, Subgroup B- Sample,, Rev X. Page of

5 CONFORMANCE GROUP TABLE. APPLICABLE SUBGROUPS (Continued) MIL-STD- METHOD GROUP A SUBGROUPS READ AND RECORD Group D Sample,,, A, B, Subgroups, NOTE:. % Parameteric, % Functional; Cumulative for Static and. TABLE. TOTAL DOSE IRRADIATION MIL-STD- TEST READ AND RECORD CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD Group E Subgroup,, Table, Table TABLE. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND V -.V khz khz Static Burn-In (Note ),,,, -, - Static Burn-In (Note ),,,, -,, - Dynamic Burn-In (Note ) -,,,,,,,,, Irradiation (Note ),,,, -,, - NOTE:. Each pin except and GND will have a series resistor of K %, = V.V. Each pin except and GND will have a series resistor of K %; Group E, Subgroup, sample size is dice/wafer, failures, = V.V Functional Diagram TRUTH TABLE EACH SWITCH IN/OUT SIG A SW A INPUT OUTPUT VC VIS OUT/IN CONTROL A OUT/IN SIG B IN/OUT SW D CONTROL D IN/OUT Open Open CONTROL B SW B SIG D OUT/IN Positive Logic: Switch ON VC = Switch OFF VC = CONTROL C SW C OUT/IN SIG C IN/OUT Copyright Intersil Americas LLC. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see Rev X. Page of

6 Schematic CONTROL IN VIS SWITCH NORMAL OPERATION CONTROL LINE BIASING: SWITCH ON, VC I = SWITCH OFF, VC O = CONTROL VC * P N N P N OUT SIGNAL LEVEL RANGE: VIS * ALL CONTROL INPUTS ARE PROTECTED BY THE CMOS PROTECTION NETWORK NOTE: All P Substrates Connected to FIGURE. SCHEMATIC DIAGRAM OF OF IDENTICAL SWITCH- ES AND ITS ASSOCIATED CONTROL CIRCUITRY KEITHLY DIGITAL MULTIMETER VIS IIS OF SWITCHES VIS - RON = IIS k TG ON k RANGE Y X X-Y PLOT TER H P MOSELEY A FIGURE. DETERMINATION OF RON AS A TEST CONDITION FOR CONTROL INPUT HIGH VOLTAGE (VIHC) SPECIFICATION FIGURE. CHANNEL ON-STATE RESISTANCE MEASURE- MENT CIRCUIT VC = -V CIOS = +V OF SWITCHES MEASURED ON BOONTON CAPACITANCE BRIDGE MODEL A (MHz) TEST FIXTURE CAPACITANCE NULLED OUT VC = VIS = OF SWITCHES ALL UNUSED TERMINALS ARE CONNECTED TO CIS = -V COS FIGURE. CAPACITANCE TEST CIRCUIT FIGURE. OFF SWITCH INPUT OR OUTPUT LEAKAGE VC = ALL UNUSED INPUTS ARE CONNECTED TO +V tr = tf = ns VC ALL UNUSED TERMINALS ARE CONNECTED TO ViS tr = tf = ns OF SWITCHES pf k k VIS OF SWITCHES k FIGURE. PROPAGATION DELAY TIME SIGNAL INPUT (VIS) TO SIGNAL OUTPUT () FIGURE. CROSSTALK CONTROL INPUT TO SIGNAL OUTPUT Rev X. Page of

7 VC tr = tf = ns REP RATE % ns % ns VC = tr = tf = ns OF SWITCHES ALL UNUSED TERMINALS ARE CONNECTED TO pf k +V tr = tf = ns VIS = +V VC = +V OF SWITCHES ALL UNUSED INPUTS ARE CONNECTED TO = / AT khz pf k FIGURE. PROPAGATION DELAY TPLH, TPHL CONTROL SIGNAL OUTPUT. DELAY IS MEASURED AT LEVEL OF +% FROM GROUND (TURN ON) OR ON-STATE OUTPUT LEVEL (TURN OFF). FIGURE. MAXIMUM ALLOWABLE CONTROL INPUT REPETI- TION RATE CLOCK RESET PE J J J J J CDB Q Q / CDB EXT RESET CLOCK PE J J J J J Q Q CDB / CDB CDB / CDB CDB SIGNALS INPUTS PACKAGE COUNT - CDB - CDB - - CDB CHANNEL CHANNEL CHANNEL CHANNEL CLOCK MAX. ALLOWABLE SIGNAL LEVEL CDB K / CDB / CDB % ( - ) CHAN. CHAN. CHAN. CHAN. CDB K K K K LPF LPF LPF LPF SIGNALS OUTPUTS CHANNEL CHANNEL CHANNEL CHANNEL FIGURE. CHANNEL PAM MULTIPLEX SYSTEM DIAGRAM Rev X. Page of

8 + ANALOG INPUTS ( V) = V - = +V V SWA IN CDB SWB SWC SWD DIGITAL CONTROL INPUTS = V VEE = -V ANALOG OUTPUTS ( V) = -V FIGURE. BIDIRECTIONAL SIGNAL TRANSMISSION VIA DIGITAL CONTROL LOGIC Typical Performance Characteristics CHANNEL ON-STATE RESISTANCE (RON) ( ) SUPPLY VOLTAGE ( - VEE) = V AMBIENT TEMPERATURE (T A ) = + o C + o C - o C CHANNEL ON-STATE RESISTANCE (RON) ( ) SUPPLY VOLTAGE ( - VEE) = V AMBIENT TEMPERATURE (T A ) = + o C + o C - o C INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE. TYPICAL ON-STATE vs INPUT SIGNAL VOLTAGE (ALL TYPES). CHANNEL ON-STATE RESISTANCE (RON) ( ) SUPPLY VOLTAGE ( - ) = V AMBIENT TEMPERATURE (T A ) = + o C + o C - o C CHANNEL ON-STATE RESISTANCE (RON) ( ) AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE ( - ) = V V V INPUT SIGNAL VOLTAGE (VIS) (V) INPUT SIGNAL VOLTAGE (VIS) (V) FIGURE. TYPICAL ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) FIGURE. ON-STATE RESISTANCE vs INPUT SIGNAL VOLTAGE (ALL TYPES) Rev X. Page of

9 Typical Performance Characteristics (Continued) OUTPUT VOLTAGE (VO) (V) - - AMBIENT TEMPERATURE (T A ) = + o C =.V, = -.V INPUT = TERM, OUTPUT = TERM K K RL = K VC = VIS ALL UNUSED TERMINALS ARE CONNECTED TO OF SWITCHES K K - K INPUT VOLTAGE (VI) (V) RL POWER DISSIPATION PER PACKAGE (PD) ( W) AMBIENT TEMPERATURE (T A ) = + o C SUPPLY VOLTAGE () = V V V f CD/ BMS SWITCHING FREQUENCY (f) (khz) FIGURE. TYPICAL ON CHARACTERISTICS FOR OF CHANNELS FIGURE. POWER DISSIPATION PER PACKAGE vs SWITCHING FREQUENCY Chip Dimensions and Pad Layout Special Considerations In applications that employ separate power sources to drive and the signal inputs, the current capability should exceed /RL (RL = effective external load of the four CDB bilateral switches). This provision avoids any permanent current flow or clamp action on the supply when power is applied or removed from the CDB. In certain applications, the external load-resistor current may include both and signal line components. To avoid drawing current when switch current flows into terminals,, or the voltage drop across the bidirectional switch must not exceed. volts (calculated from RON values shown). Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils ( - inch). No current will flow through RL if the switch current flows into terminals,,, or. METALLIZATION: Thickness: kå kå, AL. PASSIVATION:.kÅ -.kå, Silane BOND PADS:. inches X. inches MIN DIE THICKNESS:. inches -. inches Rev X. Page of