DATASHEET HA-5102, HA Pinouts. Ordering Information. Features. Applications. Dual and Quad, 8MHz, Low Noise Operational Amplifiers

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1 DATASHEET HA-512, HA-514 Dual and Quad, 8Hz, Low Noise Operational Amplifiers FN2925 Rev 9. October 26, 24 Low noise and high performance are key words describing HA-512 and HA-514. These general purpose amplifiers offer an array of dynamic specifications including a 3V/ s slew rate and 8Hz bandwidth. Complementing these outstanding parameters is a very low noise specification of 4.3nV/ Hz at 1kHz. Fabricated using the Intersil high frequency DI process, these operational amplifiers also offer excellent input specifications such as a.5mv offset voltage and 3nA offset current. Complementing these specifications are 18dB open loop gain and 6dB channel separation. Consuming a very modest amount of power (9mW/ package for duals and 15mW/package for quads), HA-512/4 also provide 15mA of output current. This impressive combination of features make this series of amplifiers ideally suited for designs ranging from audio amplifiers and active filters to the most demanding signal conditioning and instrumentation circuits. These operational amplifiers are available in dual or quad form with industry standard pinouts allowing for immediate interchangeability with most other dual and quad operational amplifiers. Pinouts OUT1 1 -IN1 2 +IN1 3 V- 4 OUT1 1 -IN1 2 +IN1 3 V+ 4 +IN2 5 -IN2 6 OUT2 7 HA-512 (CERDIP) TOP VIEW + - HA-514 (CERDIP) TOP VIEW + - HA514 (SOIC) TOP VIEW 8 V+ 7 OUT2 6 -IN2 5 +IN2 14 OUT IN4 12 +IN4 11 V IN IN3 8 OUT3 HA-512 Dual, Comp. HA-514 Quad, Comp. Refer to the /883 data sheet for military product. Ordering Information PART NUBER TEP. RANGE ( o C) PACKAGE PKG. DWG. # HA to Ld CERDIP F8.3A HA to Ld CERDIP F14.3 HA9P to Ld SOIC 16.3 OUT1 -IN1 +IN1 V+ +IN2 -IN2 OUT2 NC OUT IN IN4 13 V- 12 +IN IN OUT3 8 9 NC Features Low Noise nV/ Hz Bandwidth Hz (Compensated) Slew Rate V/ s (Compensated) Low Offset Voltage mV Available in Duals or Quads Applications High Q, Active Filters Audio Amplifiers Instrumentation Amplifiers Integrators Signal Generators For Further Design Ideas, See Application Note AN554 FN2925 Rev 9. Page 1 of 13 October 26, 24

2 HA-512, HA-514 Absolute aximum Ratings Supply Voltage Between V+ and V- Terminals V Differential Input Voltage V Input Voltage V SUPPLY Output Short Circuit Duration (Note 3) Indefinite Operating Conditions Temperature Range HA-51X o C to 125 o C HA o C to 85 o C Thermal Information Thermal Resistance (Typical, Note 2) JA ( o C/W) JC ( o C/W) 8 Lead CERDIP Package Lead CERDIP Package SOIC Package N/A aximum Junction Temperature (Note 1, Hermetic Package)..175 o C aximum Junction Temperature (Plastic Package) o C aximum Storage Temperature Range o C to 15 o C aximum Lead Temperature (Soldering 1s) o C (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in Absolute aximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. aximum power dissipation, including output load, must be designed to maintain the maximum junction temperature below 175 o C for hermetic packages, and below 15 o C for plastic packages. 2. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. Any one amplifier may be shorted to ground indefinitely. Electrical Specifications V SUPPLY = 15V, Unless Otherwise Specified PARAETER TEP. ( o C) HA HA HA IN TYP AX IN TYP AX IN TYP AX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Offset Voltage Average Drift Full V/ o C Bias Current na Full na Offset Current na Full na Input Resistance k Common ode Range Full V TRANSFER CHARACTERISTICS Large Signal Voltage Gain, (V OUT = 5V, R L = 2k kv/v Full kv/v Common ode Rejection Ratio (V C = 5.V) Full db Small Signal Bandwidth, (A V = 1) Hz Channel Separation (Note 4) db OUTPUT CHARACTERISTICS Output Voltage Swing (R L = 1k ) Full V (R L = 2k ) Full V Output Current, (V OUT = 5V) Full ma Full Power Bandwidth (Note 5) khz Output Resistance STABILITY inimum Stable Closed Loop Gain Full V/V TRANSIENT RESPONSE (Note 6) FN2925 Rev 9. Page 2 of 13 October 26, 24

3 HA-512, HA-514 Electrical Specifications V SUPPLY = 15V, Unless Otherwise Specified (Continued) PARAETER TEP. ( o C) HA HA HA IN TYP AX IN TYP AX IN TYP AX UNITS Rise Time ns Overshoot % Slew Rate V/ s Settling Time (Note 7) s NOISE CHARACTERISTICS (Note 8) Input Noise Voltage f = 1Hz nv/ Hz f = 1kHz nv/ Hz Input Noise Current f = 1Hz pa/ Hz f = 1kHz pa/ Hz Broadband Noise Voltage f = DC to 3kHz nv RS POWER SUPPLY CHARACTERISTICS Supply Current (All Amps) ma Power Supply Rejection Ratio, ( V S = 5V) Full db NOTES: 4. Channel separation value is referred to the input of the amplifier. Input test conditions are: f = 1kHz; V IN = 1mV PEAK ; R S = 1k. Slew Rate 5. Full power bandwidth is guaranteed by equation: Full power bandwidth = V 6. Refer to Test Circuits section of the data sheet. PEAK 7. Settling time is measured to.1% of final value for a 1V input step, A V = The limits for these parameters are guaranteed based on lab characterization, and reflect lot-to-lot variation. FN2925 Rev 9. Page 3 of 13 October 26, 24

4 HA-512, HA-514 Test Circuits and Waveforms 2k IN 2k - + OUT IN + - 1k 5pF 2k 5pF INPUT +5V V -5V 2mV INPUT OUTPUT +5V OUTPUT V -5V V Vertical = 5V/Div., Horizontal = 5 s/div. (A V = -1) FIGURE 1. LARGE SIGNAL RESPONSE CIRCUIT Vertical = 4mV/Div., Horizontal = 5ns/Div. (A V = +1) FIGURE 2. SALL SIGNAL RESPONSE CIRCUIT +15V 5k 5 (NOTE 9) 2N4416 5k +15V TO OSCILLOSCOPE 2k + V IN - V OUT 2 (NOTE 9) 2k -15V 5pF 2k NOTES: 9. A V = Feedback and summing resistors should be.1% matched. 11. Clipping diodes are optional, HP recommended. FIGURE 3. SETTLING TIE CIRCUIT FN2925 Rev 9. Page 4 of 13 October 26, 24

5 HA-512, HA-514 Simplified Schematic V+ OUTPUT V- +INPUT -INPUT Typical Performance Curves 15 V S = 15V, T A = 25 o C 1 V S = 15V, T A = 25 o C NOISE VOLTAGE (nv/ Hz) 1 5 HIGH TYPICAL LOW NOISE CURRENT (pa/ Hz) K FREQUENCY (Hz) FIGURE 4. INPUT NOISE VOLTAGE DENSITY K FREQUENCY (Hz) FIGURE 5. INPUT NOISE CURRENT DENSITY FN2925 Rev 9. Page 5 of 13 October 26, 24

6 HA-512, HA-514 Typical Performance Curves (Continued) V S = 15V, T A = 25 o C, 5 V/Div., 1s/Div., A V = 1V/V Input Noise =.232 V P-P FIGURE 6..1Hz TO 1Hz NOISE V S = 15V, T A = 25 o C, 5 V/Div., 1s/Div., A V = 1V/V Total Output Noise = 2.75 V P-P FIGURE 7..1Hz TO 1Hz NOISE 2. V S = 15V 2. T A = 25 o C INPUT OFFSET VOLTAGE (mv) OFFSET VOLTAGE (mv) TEPERATURE ( o C) SUPPLY VOLTAGE ( V) FIGURE 8. V IO vs TEPERATURE FIGURE 9. V IO vs V S INPUT OFFSET CURRENT (na) 4 2 V S = 15V TEPERATURE ( o C) INPUT BIAS CURRENT (na) 1 9 V S = 15V TEPERATURE ( o C) FIGURE 1. I IO vs TEPERATURE FIGURE 11. I BIAS vs TEPERATURE FN2925 Rev 9. Page 6 of 13 October 26, 24

7 HA-512, HA-514 Typical Performance Curves (Continued) 5 V S = 15V, I OUT = 5 T A = 25 o C, I OUT = TOTAL SUPPLY CURRENT (ma) TOTAL SUPPLY CURRENT (ma) TEPERATURE ( o C) SUPPLY VOLTAGE ( V) FIGURE 12. I CC vs TEPERATURE (HA-514) FIGURE 13. I CC vs V S (HA-512) OPEN LOOP VOLTAGE GAIN (1 5 V/V) 5 V S = 15V, V O = 1V, R L = 2k OPEN LOOP VOLTAGE GAIN (1 5 V/V) K V O = 1V, V S = 15V 2K 125 o C 25 o C -55 o C 4K 6K 8K 1K TEPERATURE ( o C) LOAD RESISTANCE ( ) FIGURE 14. A VOL vs TEPERATURE FIGURE 15. A VOL vs LOAD RESISTANCE OPEN LOOP GAIN (kv/v) T A = 25 o C, R L = 2k SUPPLY VOLTAGE ( V) AX OUTPUT SWING ( V) T A = 25 o C, R L = 2k SUPPLY VOLTAGE ( V) FIGURE 16. A VOL vs V S FIGURE 17. V OUT vs V S FN2925 Rev 9. Page 7 of 13 October 26, 24

8 HA-512, HA-514 Typical Performance Curves (Continued) 45 V S = 15V, T A = 25 o C OUTPUT CURRENT (ma) V OUT = +15V V OUT = -15V CRR (db) TIE (SECONDS) -1 1K 1K FREQUENCY (Hz) 1K 1 FIGURE 18. OUTPUT SHORT CIRCUIT CURRENT vs TIE FIGURE 19. CRR vs FREQUENCY POWER SUPPLY REJECTION (db) PSRR -PSRR VOLTAGE GAIN (db) V S = 15V, R L = 2k, C L = 5pF 125 o C GAIN 125 o C PHASE -55 o C PHASE -55 o C GAIN PHASE SHIFT (DEGREES) -1 1K 1K 1K K 1K FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 2. PSRR vs FREQUENCY FIGURE 21. UNITY GAIN FREQUENCY RESPONSE VOLTAGE GAIN (db) GAIN PHASE V S = 15V, T A = 25 o C, R L = 2k, C L = 5pF 18 1K 1K 1K FREQUENCY (Hz) PHASE SHIFT (DEGREES) OVERSHOOT (%) V S = 15V, T A = 25 o C, R L = 2k 1 1 1K 1K LOAD CAPACITANCE (pf) FIGURE 22. OPEN LOOP GAIN vs FREQUENCY FIGURE 23. SALL SIGNAL OVERSHOOT vs C LOAD FN2925 Rev 9. Page 8 of 13 October 26, 24

9 HA-512, HA-514 Typical Performance Curves (Continued) 1.1 R L = 2k, C L = 5pF, V S = 15V 1.1 R L = 2k, C L = 5pF, V S = 15V SLEW RATE (NORALIZED) RISE TIE (NORALIZED) TEPERATURE ( o C) TEPERATURE ( o C) FIGURE 24. SLEW RATE vs TEPERATURE FIGURE 25. RISE TIE vs TEPERATURE Die Characteristics DIE DIENSIONS: 98.4 mils x 67.3 mils x 19 mils 25 m x 171 m x 483 m ETALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ 2kÅ PASSIVATION: Type: Nitride (Si 3 N 4 ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 12kÅ 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 93 PROCESS: Bipolar Dielectric Isolation etallization ask Layout HA-512 V- +IN1 -IN1 OUT1 +IN2 -IN2 OUT2 V+ FN2925 Rev 9. Page 9 of 13 October 26, 24

10 HA-512, HA-514 Die Characteristics DIE DIENSIONS: 95 mils x 99 mils x 19 mils 242 m x 253 m x 483 m ETALLIZATION: Type: Al, 1% Cu Thickness: 16kÅ 2kÅ SUBSTRATE POTENTIAL (POWERED UP): Unbiased TRANSISTOR COUNT: 175 PROCESS: Bipolar Dielectric Isolation PASSIVATION: Type: Nitride (Si 3 N 4 ) over Silox (SiO 2, 5% Phos.) Silox Thickness: 12kÅ 2kÅ Nitride Thickness: 3.5kÅ 1.5kÅ etallization ask Layout HA-514 +IN2 V+ +IN1 -IN2 -IN1 OUT2 OUT3 OUT1 OUT4 -IN3 -IN4 +IN3 V- +IN4 FN2925 Rev 9. Page 1 of 13 October 26, 24

11 HA-512, HA-514 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. easure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y Controlling dimension: INCH E L c1 ea/2 S D S aaa C A - B LEAD FINISH BASE ETAL b1 (b) SECTION A-A S ea c D S (c) F8.3A IL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES ILLIETERS SYBOL IN AX IN AX NOTES A b b b b c c D E e.1 BSC 2.54 BSC - ea.3 BSC 7.62 BSC - ea/2.15 BSC 3.81 BSC - L Q S o 15 o 9 o 15 o - aaa bbb ccc , 3 N Rev. 4/94 FN2925 Rev 9. Page 11 of 13 October 26, 24

12 HA-512, HA-514 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. easure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y Controlling dimension: INCH. E L c1 ea/2 S D S aaa C A - B LEAD FINISH BASE ETAL b1 (b) SECTION A-A S ea c D S (c) F14.3 IL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES ILLIETERS SYBOL IN AX IN AX NOTES A b b b b c c D E e.1 BSC 2.54 BSC - ea.3 BSC 7.62 BSC - ea/2.15 BSC 3.81 BSC - L Q S o 15 o 9 o 15 o - aaa bbb ccc , 3 N Rev. 4/94 FN2925 Rev 9. Page 12 of 13 October 26, 24

13 HA-512, HA-514 Small Outline Plastic Packages (SOIC) N INDEX AREA e D B.25(.1) C A E -B- -A- -C- SEATING PLANE A B S H A1.1(.4) NOTES: 1. Symbols are defined in the O Series Symbol List in Section 2.2 of Publication Number Dimensioning and tolerancing per ANSI Y Dimension D does not include mold flash, protrusions or gate burrs. old flash, protrusion and gate burrs shall not exceed.15mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm (.1 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.14 inch) or greater above the seating plane, shall not exceed a maximum value of.61mm (.24 inch) 1. Controlling dimension: ILLIETER. Converted inch dimensions are not necessarily exact. µ.25(.1) B L h x 45 o C 16.3 (JEDEC S-13-AA ISSUE C) 16 LEAD WIDE BODY SALL OUTLINE PLASTIC PACKAGE INCHES ILLIETERS SYBOL IN AX IN AX NOTES A A B C D E e.5 BSC 1.27 BSC - H h L N o 8 o o 8 o - Rev. 12/93 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN2925 Rev 9. Page 13 of 13 October 26, 24