DATASHEET HS-1135RH. Features. Applications. Pinouts

Transcription

1 DATASHEET Radiation Hardened, High Speed, Low Power Current Feedback Amplifier with Programmable Output Limiting FN099 Rev.00 The is a radiation hardened, high speed, low power current feedback amplifier built with Intersil s proprietary complementary bipolar UHF- (DI bonded wafer) process. They are QL approved and processed in full compliance with IL-PRF-. This amplifier features user programmable output limiting, via the and V L pins. The is the ideal choice for high speed, low power applications requiring output limiting (e.g., flash A/D drivers), especially those requiring fast overdrive recovery times. The limiting function allows the designer to set the maximum and minimum output levels to protect downstream stages from damage or input saturation. The sub-nanosecond overdrive recovery time ensures a quick return to linear operation following an overdrive condition. Component and composite video systems also benefit from this op amp s performance, as indicated by the gain flatness, and differential gain and phase specifications. Specifications for Rad Hard QL devices are controlled by the Defense Supply Center in Columbus (DSCC). The SD numbers listed here must be used when ordering. Detailed Electrical Specifications for these devices are contained in SD A hot-link is provided on our website for downloading. Pinouts -IN GDIP-T (CERDIP) OR CDIP2-TI (SBDIP) TOP VIEW OUT V L Features Electrically Screened to SD # 92-9 QL Qualified per IL-PRF- Requirements User Programmable Output Voltage Limiting Fast Overdrive Recovery <ns (Typ) Low Supply Current mA (Typ) Wide -db Bandwidth Hz (Typ) High Slew Rate V/µs (Typ) High Input Impedance (Typ) Excellent Gain Flatness (to 0Hz) dB (Typ) Total Gamma Dose kRAD(Si) Latch Up None (DI Technology) Applications Flash A/D Driver Video Switching and Routing Pulse and Video Amplifiers Wideband Amplifiers RF/IF Signal Processing Imaging Systems -IN CDFP-F (FLATPACK) TOP VIEW OUT V L FN099 Rev.00 Page of 9

2 Ordering Information ORDERING NUBER (Note) INTERNAL KT. NUBER PART ARKING TEP. RANGE ( C) PACKAGE PKG DWG # 92F90VPC HSB-RH-Q Q92F9 0VPC - to +2 Ld SBDIP D. 92F90VXC HS9-RH-Q Q92F9 0VXC - to +2 Ld Flatpack K.A HSB-RH/PROTO HSB-RH/PROTO HSB- RH /PROTO - to +2 Ld SBDIP D. HS9-RH/PROTO HS9-RH/PROTO HS9- RH /PROTO - to +2 Ld Flatpack K.A NOTE: These Intersil Pb-free Hermetic packaged products employ 00% Au plate - e termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. FN099 Rev.00 Page 2 of 9

3 Clamp Operation General The features user programmable output clamps to limit output voltage excursions. Clamping action is obtained by applying voltages to the and V L terminals (pins and ) of the amplifier. sets the upper output limit, while V L sets the lower clamp level. If the amplifier tries to drive the output above, or below V L, the clamp circuitry limits the output voltage at or V L (± the clamp accuracy), respectively. The low input bias currents of the clamp pins allow them to be driven by simple resistive divider circuits, or active elements such as amplifiers or DACs. Clamp Circuitry Figure shows a simplified schematic of the input stage, and the high clamp ( ) circuitry. As with all current feedback amplifiers, there is a unity gain buffer (Q X - Q X2 ) between the positive and negative inputs. This buffer forces -IN to track, and sets up a slewing current of (V -IN -V OUT )/R F. This current is mirrored onto the high impedance node (Z) by Q X -Q X, where it is converted to a voltage and fed to the output via another unity gain buffer. If no clamping is utilized, the high impedance node may swing within the limits defined by Q P and Q N. Note that when the output reaches it s quiescent value, the current flowing through -IN is reduced to only that small current (-I BIAS ) required to keep the output at the final voltage. Q P Q N Q P Q N Q N2 Q P2 I CLAP -IN Q P Tracing the path from to Z illustrates the effect of the clamp voltage on the high impedance node. decreases by 2V BE (QN and QP) to set up the base voltage on QP. QP begins to conduct whenever the high impedance node reaches a voltage equal to QP s base + 2V BE (QP and QN). Thus, QP clamps node Z whenever Z reaches. R provides a pull-up network to ensure functionality with Z Q N Q N Q P + Q N Q P R F (EXTERNAL) 0k (0k FOR V L ) 200 V OUT FIGURE. SIPLIFIED CLAP CIRCUITRY R the clamp inputs floating. A similar description applies to the symmetrical low clamp circuitry controlled by V L. When the output is clamped, the negative input continues to source a slewing current (I CLAP ) in an attempt to force the output to the quiescent voltage defined by the input. Q P must sink this current while clamping, because the -IN current is always mirrored onto the high impedance node. The clamping current is calculated as (V -IN - V OUT )/R F. As an example, a unity gain circuit with V IN = 2V, = V, and R F = 0 would have I CLAP = (2-)/0 =.9mA. Note that I CC will increase by I CLAP when the output is clamp limited. Clamp Accuracy The clamped output voltage will not be exactly equal to the voltage applied to or V L. Offset errors, mostly due to V BE mismatches, necessitate a clamp accuracy parameter which is found in the device specifications. Clamp accuracy is a function of the clamping conditions. Referring again to Figure, it can be seen that one component of clamp accuracy is the V BE mismatch between the Q X transistors, and the Q X transistors. If the transistors always ran at the same current level, there would be no V BE mismatch, and no contribution to the inaccuracy. The Q X transistors are biased at a constant current, but as described earlier, the current through Q X is equivalent to I CLAP. V BE increases as I CLAP increases, causing the clamped output voltage to increase as well. I CLAP is a function of the overdrive level (V -IN -V OUTCLAPED ) and R F, so clamp accuracy degrades as the overdrive increases, or as R F decreases. As an example, the specified accuracy of 0mV for a 2X overdrive with R F =0 degrades to 220mV for R F =20 at the same overdrive, or to 20mV for a X overdrive with R F =0. Consideration must also be given to the fact that the clamp voltages have an effect on amplifier linearity. Clamp Range Unlike some competitor devices, both and V L have usable ranges that cross 0V. While must be more positive than V L, both may be positive or negative, within the range restrictions indicated in the specifications. For example, the could be limited to ECL output levels by setting = -0.V and V L = -.V. and V L may be connected to the same voltage (GND for instance) but the result won t be in a DC output voltage from an AC input signal. A 0-200mV AC signal will still be present at the output. Recovery from Overdrive The output voltage remains at the clamp level as long as the overdrive condition remains. When the input voltage drops below the overdrive level (V CLAP /A VCL ) the amplifier will return to linear operation. A time delay, known as the Overdrive Recovery Time, is required for this resumption of linear operation. The plots of Unclamped Performance and Clamped Performance highlight the s sub nanosecond recovery time. The difference between the unclamped and clamped propagation delays is the overdrive FN099 Rev.00 Page of 9

4 recovery time. The appropriate propagation delays are.0ns for the unclamped pulse, and.ns for the clamped (2X overdrive) pulse yielding an overdrive recovery time of 00ps. The measurement uses the 90% point of the output transition to ensure that linear operation has resumed. Note: The propagation delay illustrated is dominated by the fixturing. The delta shown is accurate, but the true propagation delay is 00ps. Use of Die in Hybrid Applications This amplifier is designed with compensation to negate the package parasitics that typically lead to instabilities. As a result, the use of die in hybrid applications results in overcompensated performance due to lower parasitic capacitances. Reducing R F below the recommended values for packaged units will solve the problem. For A V = +2 the recommended starting point is 00, while unity gain applications should try 00. The layout and schematic of the board are shown in the following: OUT V L GND FIGURE 2A. TOP LAYOUT PC Board Layout The frequency performance of this amplifier depends a great deal on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! Attention should be given to decoupling the power supplies. A large value (0µF) tantalum in parallel with a small value chip (0.µF) capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Output capacitance, such as that resulting from an improperly terminated transmission line will degrade the frequency response of the amplifier and may cause oscillations. In most cases, the oscillation can be avoided by placing a resistor in series with the output. Care must also be taken to minimize the capacitance to ground seen by the amplifier s inverting input. The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to pin 2, and connections to pin 2 should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. FIGURE 2B. BOTTO LAYOUT µF 0µF 0 2 +V 0 IN OUT V L 0µF 0.µF GND -V GND FIGURE 2C. SCHEATIC FIGURE 2. EVALUATION BOARCHEATIC AND LAYOUT Evaluation Board An evaluation board is available for the, (HFAXXEVAL). Please contact your local sales office for information. FN099 Rev.00 Page of 9

5 Burn-In Circuit CERDIP R 2 R R D D 2 C D D C. R = k, % (Per Socket) 2. R 2 = 0k, % (Per Socket). C = 0.0µF (Per Socket) or 0.µF (Per Row) inimum. D = N002 or Equivalent (Per Board). D 2 = N002 or Equivalent (Per Socket). = +.V 0.V. = -.V 0.V Irradiation Circuit CERDIP R 2 R R C C 2. R = k, % 9. R 2 = 0k, % 0. C = C 2 = 0.0µF. = +.0V 0.V 2. = -.0V 0.V FN099 Rev.00 Page of 9

6 Die Characteristics DIE DIENSIONS: 9 mils x.2 mils x 9 mils mil 00µm x 0µm x µm 2.µm INTERFACE ATERIALS: Glassivation: Type: Nitride Thickness: kå 0.kÅ Top etallization: Type: etal : AICu(2%)/TiW Thickness: etal : kå 0.kÅ Type: etal 2: AICu(2%) Thickness: etal 2: kå 0.kÅ etallization ask Layout Substrate: UHF-, Bonded Wafer, DI ASSEBLY RELATED INFORATION: Substrate Potential: Floating ADDITIONAL INFORATION: Worst Case Current Density: < 2 x 0 A/cm 2 Transistor Count: 9 -IN OUT V L FN099 Rev.00 Page of 9

7 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) PLANE SEATING PLANE S b2 ccc bbb S b C A - B Q -C- A -B- C A - B S D A A e -D- -A-. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness.. Corner leads (, N, N/2, and N/2+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b2.. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimension Q shall be measured from the seating plane to the base plane.. easure dimension S at all four corners.. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y Controlling dimension: IH E L c ea/2 S aaa C A - B LEAD FINISH ETAL b (b) SECTION A-A S ea c (c) F.A IL-STD- GDIP-T (D-, CONFIGURATION A) LEAD CERAIC DUAL-IN-LINE FRIT SEAL PACKAGE IHES ILLIETERS SYBOL IN AX IN AX NOTES A b b b b c c D E e 0.00 BSC 2. BSC - ea 0.00 BSC.2 BSC - ea/2 0.0 BSC. BSC - L Q S o 0 o 90 o 0 o - aaa bbb ccc , N Rev. 0 /9 FN099 Rev.00 Page of 9

8 Ceramic Dual-In-Line etal Seal Packages (SBDIP) PLANE SEATING PLANE S b2 ccc bbb S b C A - B S C A - B D A A e S. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness.. Corner leads (, N, N/2, and N/2+) may be configured with a partial lead paddle. For this configuration dimension b replaces dimension b2.. Dimension Q shall be measured from the seating plane to the base plane.. easure dimension S at all four corners.. easure dimension S2 from the top of the ceramic body to the nearest metallization or lead.. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 0. Dimensioning and tolerancing per ANSI Y Controlling dimension: IH. E c L ea/2 LEAD FINISH ETAL b (b) SECTION A-A -D- -A- S2 Q -C- A ea -Baaa C A - B S c (c) D. IL-STD- CDIP2-T (D-, CONFIGURATION C) LEAD CERAIC DUAL-IN-LINE ETAL SEAL PACKAGE IHES ILLIETERS SYBOL IN AX IN AX NOTES A b b b b c c D E e 0.00 BSC 2. BSC - ea 0.00 BSC.2 BSC - ea/2 0.0 BSC. BSC - L Q S S o 0 o 90 o 0 o - aaa bbb ccc N Rev. 0 /9 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO900 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN099 Rev.00 Page of 9

9 Ceramic etal Seal Flatpack Packages (Flatpack) -Hb A e -A H A - B Q SEATING AND PLANE L c S E PIN NO. ID AREA E E E2 LEAD FINISH ETAL b (b) 0.0 H A - B SECTION A-A. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. Alternately, a tab (dimension k) may be used to identify pin one. 2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.. This dimension allows for off-center lid, meniscus, and glass overrun.. Dimensions b and c apply to lead base metal only. Dimension applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.. N is the maximum number of terminal positions.. easure dimension S at all four corners.. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the leads.. Dimension Q shall be measured at the point of exit (beyond the meniscus) of the lead from the body. Dimension Q minimum shall be reduced by 0.00 inch (0.0mm) maximum when solder dip lead finish is applied. 9. Dimensioning and tolerancing per ANSI Y Controlling dimension: IH. E (c) L S C S A A -D- -C- -B- D K.A IL-STD- CDFP-F (F-2A, CONFIGURATION B) LEAD CERAIC ETAL SEAL FLATPACK PACKAGE IHES ILLIETERS SYBOL IN AX IN AX NOTES A b b c c D E E E E e 0.00 BSC.2 BSC - k L Q S N - Rev. 0 //9 FN099 Rev.00 Page 9 of 9