DATASHEET HA-5101/883. Features. Applications. Ordering Information. Pinouts. Low Noise, High Performance Operational Amplifier

Transcription

1 DATASHEET HA-511/883 Low Noise, High Performance Operational Amplifier The HA-511/883 is a dielectrically isolated operational amplifier featuring low noise and high performance. This amplifier has an excellent noise voltage density of 4.5nV/ Hz (max) at 1kHz. The unity gain stable HA-511/883 yields a 1MHz unity gain bandwidth and a 6V/µs slew rate. DC characteristics of the HA-511/883 assure accurate performance. The 3mV (max) offset voltage is externally adjustable and offset voltage drift is just 3 V/ C. Low bias currents (2nA max) reduce input current errors and the high open loop voltage gain of 1kV/V, over temperature, increases the loop gain for low distortion amplification. The HA-511/883 is ideal for audio applications, especially low-level signal amplifiers such as microphone, tape head and preamplifiers. Additionally, it is well suited for low distortion oscillators, low noise function generators and high Q filters. Features FN3931 Rev.1. This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph Low Noise 1kHz nV/ Hz Max Low Noise 1kHz pA/ Hz Max Wide Unity Gain Bandwidth MHz Min High Gain (Full Temp) kV/V Min (Room Temp) MV/V Typ Slew Rate V/ s Min High CMRR/PSRR (Full Temp) dB Min High Output Drive Capability (Full Temp) mA Applications High Quality Audio Preamplifiers High Q Active Filters Low Noise Function Generators Low Distortion Oscillators Low Noise Comparators Ordering Information PART NUMBER TEMP. RANGE ( C) PACKAGE PKG. DWG. # HA7-511/ to Ld CerDIP F8.3A A -55 to Ld Ceramic LCC J2.A Pinouts HA7-511/883 (CERDIP) TOP VIEW (CLCC) TOP VIEW BAL BAL IN +IN V V+ OUT BAL -IN +IN V+ OUT V- BAL FN3931 Rev.1. Page 1 of 16

2 HA-511/883 Absolute Maximum Ratings Voltage Between V+ and V- Terminals V Differential Input Voltage V Voltage at Either Input Terminal V+ to V- Input Current mA Output Short Circuit Duration Indefinite Junction Temperature (T J ) C Storage Temperature Range C to +15 C ESD Rating <2V Lead Temperature (Soldering 1s) C Thermal Information Thermal Resistance JA ( C/W) JC ( C/W) Ceramic DIP Package Ceramic LCC Package Package Power Dissipation Limit at +75 C for T J +175 C Ceramic DIP Package W Ceramic LCC Package W Package Power Dissipation Derating Factor Above +75 C Ceramic DIP Package mW/ C Ceramic LCC Package mW/ C Operating Conditions Operating Temperature Range C to +125 C Operating Supply Voltage ±5V to ±15V V INcm 1/2 (V+ - V-) R L 5 CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. TABLE 1. D.C. ELECTRICAL PERFORMAE CHARACTERISTICS Device Tested at: V S = 15V, R S = 1 R L = 5k V OUT = V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP ( C) MIN LIMITS MAX UNITS Input Offset Voltage V IO V CM = V mv 2, , mv Input Bias Current +I B V CM = V +R S = 1k -RS = 1 -I B V CM = V +R S = 1 -RS = 1k Input Offset Current I IO V CM = V +R S = 1k -RS = 1k Common Mode Range +CMR V+ = 3V V- = -27V na 2, , na na 2, , na na 2, , na V 2, , V -CMR V+ = 27V V- = -3V V 2, , V Large Signal Voltage Gain +A VOL V OUT = V and 1V R L = 2k -A VOL V OUT = V and 1V R L = 2k Common Mode Rejection Ratio +CMRR V CM = +1V V+ =+5V V- = -25V V OUT = -1V -CMRR V CM = -1V V+ = +25V V- = -5V V OUT = +1V kv/v 5, , kv/v kv/v 5, , kv/v db 2, , db db 2, , db FN3931 Rev.1. Page 2 of 16

3 HA-511/883 TABLE 1. D.C. ELECTRICAL PERFORMAE CHARACTERISTICS (Continued) Device Tested at: V S = 15V, R S = 1 R L = 5k V OUT = V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP ( C) LIMITS Output Voltage Swing +V OUT1 R L = 2k V 2, , V -V OUT1 R L = 2k V 2, , V +V OUT2 V S = 18V V R L = 6 2, , V -V OUT2 V S = 18V V R L = 6 2, , V Output Current +I OUT V OUT = -15V ma V S = ±18V 2, , ma -I OUT V OUT = +15V ma V S = ±18V 2, , ma Quiescent Power Supply Current +I CC V OUT = V ma I OUT = ma 2, , ma -I CC V OUT = V ma I OUT = ma 2, , ma Power Supply Rejection Ratio +PSRR V S = 1V db V+ = +1V, V- = -15V V+ = +2V, V- = -15V 2, , db -PSRR V S = 1V db V+ = +15V, V- = -1V V+ = +15V, V- = -2V 2, , db Offset Voltage Adjustment +V IO Adj Note V IO -1 - mv R L = 2k, C L = 5pF A V = +1V/V 2, , -55 V IO -1 - mv -V IO Adj V IO +1 - mv 2, , -55 V IO +1 - mv MIN MAX UNITS TABLE 2. A.C. ELECTRICAL PERFORMAE CHARACTERISTICS Device Tested at: V S = 15V, R S = 5 R L = 2k C L = 5pF, A VCL = +1V/V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS GROUP A SUBGROUP TEMP ( C) MIN LIMITS MAX UNITS Slew Rate +SR V OUT = -3V to +3V V/ s -SR V OUT = +3V to -3V V/ s Rise and Fall Time t R V OUT = V to +2mV 1% t R 9% ns 5, , ns t F V OUT = V to -2mV 1% t F 9% ns 5, , ns Overshoot +OS V OUT = V to +2mV % 5, , % -OS V OUT = V to -2mV % 5, , % FN3931 Rev.1. Page 3 of 16

4 HA-511/883 TABLE 3. ELECTRICAL PERFORMAE CHARACTERISTICS Device Characterized at: V S = 15V, R L = 2k C L = 5pF, A V = +1, Unless Otherwise Specified LIMITS PARAMETER SYMBOL TEST CONDITIONS NOTES TEMP ( C) MIN MAX UNITS Differential Input Resistance R IN V CM = V k Low Frequency Peak-to-Peak Noise E np-p.1hz to 1Hz µv P-P Input Noise Voltage Density E n R S = 2, f o = 1Hz nv/ Hz Input Noise Current Density I n R S = 2M, f o = 1Hz pa/ Hz Unity Gain Bandwidth UGBW V O = 1mV MHz Full Power Bandwidth FPBW V PEAK = 1V 1, khz Minimum Closed Loop Stable Gain CLSG 1-55 to V/V Output Resistance R OUT Open Loop Quiescent Power Consumption PC V OUT = V, I OUT = ma 1, 3-55 to mw NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot to lot and within lot variation. 2. Full Power Bandwidth guarantee based on Slew Rate measurement using FPBW = Slew Rate/(2 V PEAK ). 3. Quiescent Power Consumption based upon Quiescent Supply Current test maximum. (No load on outputs.) 4. Offset adjustment range is [V IO (Measured) ±1mV] minimum referred to output. This test is for functionality only to assure adjustment through V. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLES 1 & 2) Interim Electrical Parameters (Pre Burn-in) 1 Final Electrical Test Parameters 1*, 2, 3, 4, 5, 6 Group A Test Requirements 1, 2, 3, 4, 5, 6 Groups C & D Endpoints 1 *PDA applies to Subgroup 1 only. FN3931 Rev.1. Page 4 of 16

5 HA-511/883 t R t F t R t F FN3931 Rev.1. Page 5 of 16

6 HA-511/883 Burn-in Circuits CERAMIC MINI-DIP 1 8 V C 1 C 3 D 1 V- 4 5 D 2 C 2 R 1 CERAMIC LCC NOTES: R 1 = 1M, ±5%, 1/4W (Min) C 1 = C 2 =.1µF/Socket (Min) or.1µf/row, (Min) C 3 =.1µF/Socket, 1% D 1 = D 2 = 1N42 or Equivalent/Board (V+) - (V-) = 3V FN3931 Rev.1. Page 6 of 16

7 HA-511/883 Schematic -IN D 1 D 2 +IN V+ R 24 R 25 R 23 Q 23 R 26 Q 26 Q 47 R 6 R 28 Q 24 Q 28 R 35 Q 25 QL41 Q 45 Q L2 R 34 Q L1 Q 14 Q15 Q 16 R 37 Q 37 Q 35 R 36 Q 36 R 22 Q 41 Q 44 Q 2A Q 2B Q 3 Q 46 Q 33 Q 32 Q 31 Q 43 Q 38 Q 29 Q 1B Q 1A Q 42 Q R 15 OUTPUT R 17A Q 21 Q 22 Q 17 R 2 Q 19B C 1 Q 2 Q 19A Q 11 Q 1 Q 27 Q 5 Q 3 Q 9 Q 4 Q 6 Q 7 C 2 Q 12 Q 34 R 58 Q 8 Q 18 R 3A 3.65K Q 39 R 4A 3.65K Q 49 Q 5 Q 48 R 19A R 11 R 1 R 12 R 27 R 38 R 4B Q 51 R 18 V- R 19B BAL BAL FN3931 Rev.1. Page 7 of 16

8 HA-511/883 Die Characteristics DIE DIMENSIONS 7 X 7 X 19 mils ±1mil 179 x 178 x 483µm ±25.4µm METALLIZATION Type: AI, 1% Cu Thickness: 16kÅ ±2kÅ GLASSIVATION Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kÅ ±2kÅ Nitride Thickness: 3.5kÅ ±1.5kÅ WORST CASE CURRENT DENSITY: 1.38 x 1 5 A/cm 2 SUBSTRATE POTENTIAL (Powered Up): V- TRANSISTOR COUNT: 54 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout BAL HA-511/883 -IN V+ +IN OUT V- BAL FN3931 Rev.1. Page 8 of 16

9 HA-511/883 Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S1 b2 ccc M bbb S b C A - B Q -C- A -B- C A - B S D A A e D S -D- -A- NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: IH E L M c1 ea/2 S D S aaa M C A - B LEAD FINISH BASE METAL b1 M (b) SECTION A-A S ea c D S (c) F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e.1 BSC 2.54 BSC - ea.3 BSC 7.62 BSC - ea/2.15 BSC 3.81 BSC - L Q S o 15 o 9 o 15 o - aaa bbb ccc M , 3 N Rev. 4/94 FN3931 Rev.1. Page 9 of 16

10 HA-511/883 Ceramic Leadless Chip Carrier Packages (CLCC) j x 45 o.1 S E H S D D3 J2.A MIL-STD-1835 CQCC1-N2 (C-2) 2 PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE IHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A , 7 A B B , 4 B E3 E B2.72 REF 1.83 REF - B D D1.2 BSC 5.8 BSC - D2.1 BSC 2.54 BSC - h x 45 o D S E F S E A A1 PLANE 2 E1.2 BSC 5.8 BSC - E2.1 BSC 2.54 BSC - E E- PLANE 1 e.5 BSC 1.27 BSC - e h.4 REF 1.2 REF 5 j.2 REF.51 REF 5.7 M E F S HS L L B1 -H- e L3 L L L ND NE N F- E1 E2 e1 L2 D1 B2 D2 B3 L1 Rev. 5/18/94 NOTES: 1. Metallized castellations shall be connected to plane 1 terminals and extend toward plane 2 across at least two layers of ceramic or completely across all of the ceramic layers to make electrical connection with the optional plane 2 terminals. 2. Unless otherwise specified, a minimum clearance of.15 inch (.38mm) shall be maintained between all metallized features (e.g., lid, castellations, terminals, thermal pads, etc.) 3. Symbol N is the maximum number of terminals. Symbols ND and NE are the number of terminals along the sides of length D and E, respectively. 4. The required plane 1 terminals and optional plane 2 terminals (if used) shall be electrically connected. 5. The corner shape (square, notch, radius, etc.) may vary at the manufacturer s option, from that shown on the drawing. 6. Chip carriers shall be constructed of a minimum of two ceramic layers. 7. Dimension A controls the overall package thickness. The maximum A dimension is package height before being solder dipped. 8. Dimensioning and tolerancing per ANSI Y14.5M Controlling dimension: IH. FN3931 Rev.1. Page 1 of 16

11 DATASHEET HA-511/883 Low Noise, High Performance Operational Amplifier FN3931 Rev.1. DESIGN INFORMATION The information contained on the following pages has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves Unless Otherwise Specified: V S = ±15V, T A = +25 C 8 15 INPUT NOISE VOLTAGE (nv/ Hz) VOLTAGE CURRENT INPUT NOISE CURRENT (pa/ Hz) OFFSET VOLTAGE ( V) K 1K 1K FREQUEY (Hz) TEMPERATURE ( C) FIGURE 1. NOISE SPECTRUM FIGURE 2. OFFSET VOLTAGE vs TEMPERATURE A V = 25,, V S = 15V (.9nV P-P RTI) PEAK-TO-PEAK NOISE.1Hz TO 1Hz A V = 25,, V S = 15V (12.89mV P-P RTO or.52µv P-P RTI) PEAK-TO-PEAK TOTAL NOISE.1Hz TO 1MHz FN3931 Rev.1. Page 11 of 16

12 HA-511/883 Typical Performance Curves Unless Otherwise Specified: V S = ±15V, T A = +25 C (Continued) 2 25 INPUT OFFSET CURRENT (na) -2-4 BIAS CURRENT (na) TEMPERATURE ( C) FIGURE 3. INPUT OFFSET CURRENT vs TEMPERATURE TEMPERATURE ( C) FIGURE 4. INPUT BIAS CURRENT vs TEMPERATURE 3 5 MAXIMUM 2 4 OFFSET CHANGE ( V) SUPPLY CURRENT (ma) TYPICAL MINIMUM TIME (s) SUPPLY VOLTAGE ( V) FIGURE 5. INPUT OFFSET WARMUP DRIFT vs TIME (NORMALIZED TO ZERO FINAL VALUE) (SIX REPRESENTATIVE UNITS) FIGURE 6. SUPPLY CURRENT vs SUPPLY VOLTAGE SLEW RATE (NORMALIZED) RISE TIME 1. SLEW RATE R L = 2K, C L = 5pF TEMPERATURE ( C) RISE TIME (NORMALIZED) OUTPUT CURRENT (ma) D B C A V IN V OUT A +15mV 15V B -15mV 15V C +15mV V D -15mV V TIME (s) FIGURE 7. SLEW RATE/RISE TIME vs TEMPERATURE FIGURE 8. SHORT CIRCUIT CURRENT vs TIME FN3931 Rev.1. Page 12 of 16

13 HA-511/883 Typical Performance Curves Unless Otherwise Specified: V S = ±15V, T A = +25 C (Continued) 1M (14) OPEN LOOP VOLTAGE GAIN V/V(dB) 1M (12) 1K (1) V ERROR 1mV 2.65 s 1K (8) SUPPLY VOLTAGE ( V) TIME (1.5µs/DIV) FIGURE 9. DC OPEN-LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE FIGURE 1. SETTLING WAVEFORM 6 CLOSED LOOP VOLTAGE GAIN (db) K A V = 1V/V R L = 2K, C L = 5pF 1K 125 C PHASE 1M FREQUEY (Hz) 125 C GAIN 1M -55 C GAIN -55 C PHASE M PHASE SHIFT (DEGREES) GAIN (db) 4 A V = 1 3 A V = A V = R L = 2K, C L = 5pF 1K 1K 1M FREQUEY (Hz) 1M 1M FIGURE 11. CLOSED LOOP GAIN AND PHASE AT HIGH AND LOW TEMPERATURES FIGURE 12. CLOSED-LOOP VOLTAGE GAIN vs FREQUEY AT DIFFERENT CLOSED LOOP GAINS FN3931 Rev.1. Page 13 of 16

14 HA-511/883 Typical Performance Curves Unless Otherwise Specified: V S = ±15V, T A = +25 C (Continued) VOLTAGE GAIN (db) PHASE GAIN PHASE SHIFT (DEGREES) REJECTION RATIO (db) PSRR/CMRR +PSRR K 1K 1K FREQUEY (Hz) 1M 1M 1M K 1K 1K 1M FREQUEY (Hz) FIGURE 13. OPEN-LOOP GAIN/PHASE vs FREQUEY FIGURE 14. REJECTION RATIOS vs FREQUEY V IN = V OUT = ±3V, A V = +1, R L = 2k, C L = 5pF Timescale = 5ns/Div., Scale: Input = 5V/Div, Output = 2V/Div FIGURE 15. SLEW RATE WAVEFORM Rise Time and Overshoot V IN = V OUT = V to +2mV, A V = +1, R L = 2K, C L = 5pF Timescale = 2ns/Div. FIGURE 16. SMALL SIGNAL WAVEFORM FN3931 Rev.1. Page 14 of 16

15 HA-511/883 Applications Information Operation At 5V Supply The HA-511 performs well at V S = 5V exhibiting typical characteristics as listed below: I CC mA V IO mV I BIAS nA A VOL (V O = 3V) kV/V V OUT V I OUT mA CMRR ( V CM = 2.5V) dB PSRR ( V CC =.5V) dB Unity Gain Bandwidth MHz Slew Rate V/ s Input Protection The HA-511 has built-in back-to-back protection diodes which will limit the differential input voltage to approximately 7V. If the HA-511 will be used in conditions where that voltage may be exceeded, then current limiting resistors must be used. No more than 25mA should be allowed to flow in the HA-511 s input. Output Saturation When an op amp is overdriven, output devices can saturate and sometimes take a long time to recover. Saturation can be avoided (sometimes) by using circuits such as: V+ Offset Adjustment The following is the recommended V IO adjust configuration: NOTE: Proper decoupling is always recommended,.1 F high quality capacitor should be at or very near the device s supply pins. Comparator Circuit V IN (NOTE) R LIM R LIM Choose R LIM Such That: V V RP 5 (NOTE) 6 R P = 1k - + V+ V- 7 4 V IN MAX 7V R 25mA LIM 6 R 1 V SOURCE R 2 R 3 R IN V- If saturation cannot be avoided the HA-511 recovers from a 25% overdrive in about 6.5 s (see photo). OUT Top: Input Bottom: Output, 5V/Div., 2 s/div. Output is overdriven negative and recovers in 6 s. FN3931 Rev.1. Page 15 of 16

16 HA-511/883 TABLE 1. TYPICAL PERFORMAE CHARACTERISTICS Device Characterized At: V S = 15V, R L = 2k C L = 5pF, A VCL = +1V/V, Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP ( C) TYP DESIGN LIMITS UNITS Offset Voltage V CM = V Table 1 mv Offset Voltage Average Drift Versus Temperature -55 to µv/ C Offset Current Average Drift Versus Temperature -55 to pa/ C Input Bias Current V CM = V Table 1 na Input Offset Current V CM = V Table 1 na Differential Input Resistance V CM = V Table 3 k Input Noise Voltage Density f o = 1Hz nv/ Hz f o = 1Hz nv/ Hz f o = 1kHz Table 3 nv/ Hz Input Noise Current Density f o = 1Hz pa/ Hz f o = 1Hz pa/ Hz f o = 1kHz Table 3 pa/ Hz Large Signal Voltage Gain V OUT = ±1V -55 4K Table 1 V/V +25 1M Table 1 V/V M Table 1 V/V Slew Rate V OUT = ±3V -55 to V/ s Full Power Bandwidth V PEAK = 1V, (Note 2) -55 to khz Rise and Fall Times V OUT = ±2mV -55 to Table 2 ns Overshoot V OUT = ±2mV -55 to % Settling Time To.1% for 1V Step µs To.1% for 1V Step µs Output Short Circuit Current t < 1s, V OUT = ±15V +25 ±35 ±5 ma Output Resistance Open Loop Table 3 Supply Current No Load Table 1 ma Minimum Supply Voltage Functional Operation Only, Other Parameters Will Vary +25 ±4 ±5 V Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO91 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN3931 Rev.1. Page 16 of 16