HA-2520, HA-2522, HA-2525

Transcription

1 HA-, HA-, HA- Data Sheet November, 6 FN894.8 MHz, High Slew Rate, Uncompensated, High Input Impedance, Operational Amplifiers HA-, HA-, HA- comprise a series of operational amplifiers delivering an unsurpassed combination of specifications for slew rate, bandwidth and settling time. These dielectrically isolated amplifiers are controlled at close loop gains greater than 3 without external compensation. In addition, these high performance components also provide low offset current and high input impedance. V/ms slew rate and ns (.%) settling time of these amplifiers make them ideal components for pulse amplification and data acquisition designs. These devices are valuable components for RF and video circuitry requiring up to MHz gain bandwidth and MHz power bandwidth. For accurate signal conditioning designs the HA-, HA-, HA- s superior dynamic specifications are complemented by na offset current, MΩ input impedance and offset trim capability. Ordering Information PART NUMBER PART MARKING TEMP. RANGE ( C) PACKAGE PKG. DWG. # HA-- HA-- - to + 8 Ld Metal Can T8.C HA7-- HA7-- - to + 8 Ld CerDIP F8.3A HA-- HA-- - to + 8 Ld Metal Can T8.C HA-- HA-- to +7 8 Ld Metal Can T8.C HA3-- HA3-- to +7 8 Ld PDIP E8.3 Features High Slew Rate V/μs Fast Settling ns Full Power Bandwidth MHz Gain Bandwidth (A V 3) MHz High Input Impedance MΩ Low Offset Current nA Compensation Pin for Unity Gain Capability Pb-Free Plus Anneal Available (RoHS Compliant) Applications Data Acquisition Systems RF Amplifiers Video Amplifiers Signal Generators Pinouts HA-, HA- (8 LD CERDIP, 8 LD PDIP, CERDIP, SOIC) TOP VIEW BAL -IN +IN V COMP V+ OUT BAL HA3--Z (Note) HA3--Z to +7 8 Ld PDIP* (Pb-free) E8.3 HA7-- HA7-- to +7 8 Ld CerDIP F8.3A HA9P- to +7 8 Ld SOIC M8. HA9P-Z (Note) -Z to +7 8 Ld SOIC (Pb-free) M8. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. HA-, HA-, HA- (8 LD METAL CAN) TOP VIEW COMP IN- BAL IN V- 7 6 V+ BAL OUT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures INTERSIL or Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 999, 4,, 6. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 HA-, HA-, HA- Absolute Maximum Ratings Supply Voltage (Between V+ and V- Terminals) V Differential Input Voltage V Output Current ma Operating Conditions Temperature Range HA-/ C to + C HA C to +7 C Thermal Information Thermal Resistance (Typical, Note ) θ JA ( C/W) θ JC ( C/W) Metal Can Package PDIP Package* N/A CERDIP Package SOIC Package N/A Maximum Junction Temperature (Hermetic Packages) C Maximum Junction Temperature (Plastic Package) C Maximum Storage Temperature Range C to + C Maximum Lead Temperature (Soldering s) C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V SUPPLY = ±V PARAMETER TEMP ( C) HA-- HA-- HA-- MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS INPUT CHARACTERISTICS Offset Voltage mv Full mv Offset Voltage Drift Full mv/ C Bias Current na Full na Offset Current na Full na Input Resistance (Note ) MW Common Mode Range Full ±. - - ±. - - ±. - - V TRANSFER CHARACTERISTICS Large Signal Voltage Gain (Notes 3, 6) Common Mode Rejection Ratio (Note 4) kv/v Full kv/v Full db Gain Bandwidth (Notes, ) MHz Minimum Stable Gain V/V OUTPUT CHARACTERISTICS Output Voltage Swing (Note 3) Full ±. ±. - ±. ±. - ±. ±. - V Output Current (Note 6) ± ± - ± ± - ± ± - ma Full Power Bandwidth (Notes 6, ) MHz TRANSIENT RESPONSE (A V = +3) Rise Time (Notes 3, 7, 8, ) ns Overshoot (Notes 3, 7, 8, ) % Slew Rate (Notes 3, 7,, ) ± ± - ±8 ± - ±8 ± - V/μs Settling Time (Notes 3, 7,, ) μs FN894.8 November, 6

3 HA-, HA-, HA- Electrical Specifications V SUPPLY = ±V (Continued) PARAMETER TEMP ( C) HA-- HA-- HA-- MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS POWER SUPPLY CHARACTERISTICS Supply Current ma Power Supply Rejection Ratio (Note 9) Full db. This parameter value is based on design calculations. 3. R L = kω. 4. V CM = ±V.. A V >. 6. V O = ±.V. 7. C L = pf. 8. V O = ±mv. 9. DV = ±.V.. See Transient Response Test Circuits and Waveforms. Slew Rate. Full Power Bandwidth guaranteed based on slew rate measurement using: FPBW = πv. V OUT = ±V. PEAK Test Circuits and Waveforms +.67V INPUT -.67V +V 7% OUTPUT ΔV % ERROR BAND -V SLEW ±mv FROM Δt RATE FINAL VALUE = ΔV/Δt SETTLING TIME FIGURE. SLEW RATE AND SETTLING TIME INPUT V ±mv 9% OUTPUT % V ±67mV OVERSHOOT RISE TIME NOTE: Measured on both positive and negative transitions from V to +mv and V to -mv at the output. FIGURE. TRANSIENT RESPONSE V+ μf INPUT 667.Ω 3 7.μF μf OUTPUT pf IN + - pf 333Ω 667Ω pf OUT D G N446 S 667Ω V-.μF Ω Ω SETTLING TIME TEST POINT Ω CR CR FIGURE 3. SLEW RATE AND TRANSIENT RESPONSE 3. A V = Feedback and summing resistor ratios should be.% matched.. Clipping diodes CR and CR are optional. HP8-8 recommended. FIGURE 4. SETTLING TIME TEST CIRCUIT 3 FN894.8 November, 6

4 HA-, HA-, HA- Test Circuits and Waveforms (Continued) V+ kω IN BAL. COMP OUT V- C C NOTE: Tested offset adjustment range is V OS + mv minimum referred to output. Typical ranges are ±mv with R T = kω. FIGURE. SUGGESTED V OS ADJUSTMENT AND COMPENSATION HOOK-UP Schematic Diagram OFFSET- PIN BAL BAL OFFSET+ COMP V+ Q 3 R AA R BB R R Q 9 R 3 R 44.8K R A 44.8K R B R Q 8 Q 7 R 6 Q 6 Q 3A Q 4A Q 3B Q 4B C pf Q 3 Q 8 Q R 9 Q A +INPUT R Q A Q A Q B Q B Q B D 38 Q B R 7 OUTPUT Q 7 R A R B Q 7 R 8 3 Q 4 D 3A Q 8 Q 6 Q 3 Q 9 Q Q A Q 6 Q B Q A Q B Q Q R 6A Q R 6B R 3A R 3B R 9 Q 9 D 4 R Q A V- -INPUT 4 FN894.8 November, 6

5 HA-, HA-, HA- Typical Application Inverting Unity Gain Circuit Figure 6 shows a Compensation Circuit for an inverting unity gain amplifier. The circuit was tested for functionality with supply voltages from ±4V to ±V, and the performance as tested was: Slew Rate V/μs; Bandwidth MHz; and Settling Time (.%) ns. Figure 7 illustrates the amplifier s frequency response, and it is important to note that capacitance at pin 8 must be minimized for maximum bandwidth. IN k K pf K k + - HA- OUT FIGURE 6. INVERTING UNITY GAIN CIRCUIT GAIN (db) PHASE GAIN k k M M FIGURE 7. FREQUENCY RESPONSE FOR INVERTING UNITY GAIN CIRCUIT PHASE SHIFT (DEGREES) Typical Performance Curves V S = ±V, T A = C, Unless Otherwise Specified 6-4 OFFSET VOLTAGE (mv) BIAS CURRENT (na) TEMPERATURE ( C) TEMPERATURE ( C) FIGURE 8. OFFSET VOLTAGE vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) FIGURE 9. BIAS CURRENT vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) OFFSET BIAS CURRENT (na) TEMPERATURE ( C) A VOL (kv/ V) TEMPERATURE ( C) FIGURE. OFFSET CURRENT vs TEMPERATURE ( TYPICAL UNITS FROM 3 LOTS) FIGURE. OPEN LOOP GAIN vs TEMPERATURE (6 TYPICAL UNITS FROM 3 LOTS) FN894.8 November, 6

6 HA-, HA-, HA- Typical Performance Curves V S = ±V, T A = C, Unless Otherwise Specified (Continued) OUTPUT CURRENT (±ma) SUPPLY VOLTAGE (±V) OUTPUT VOLTAGE SWING (±V) 4 R L = kω SUPPLY VOLTAGE (±V) FIGURE. OUTPUT CURRENT vs SUPPLY VOLTAGE FIGURE 3. OUTPUT VOLTAGE SWING vs SUPPLY VOLTAGE SUPPLY CURRENT (ma) SUPPLY VOLTAGE (±V) C C - C GAIN (db) GAIN AT A V = PHASE AT A V = OPEN LOOP PHASE OPEN LOOP GAIN k k k M M M FREQUENCY (Hz) PHASE ANGLE (DEGREES) FIGURE 4. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE. FREQUENCY RESPONSE k pf 3pF k k M M M FREQUENCY (Hz) pf pf 3pF pf INPUT NOISE VOLTAGE (nv/ Hz) INPUT NOISE CURRENT INPUT NOISE VOLTAGE. k k k FREQUENCY (Hz). INPUT NOISE CURRENT (pa/ Hz) FIGURE 6. OPEN LOOP FREQUENCY RESPONSE FOR VARIOUS VALUES OF CAPACITORS FROM COMP PIN TO GROUND FIGURE 7. INPUT NOISE CHARACTERISTICS 6 FN894.8 November, 6

7 HA-, HA-, HA- Typical Performance Curves V S = ±V, T A = C, Unless Otherwise Specified (Continued) OUTPUT VOLTAGE SWING (V P-P ) 3 3 V SUPPLY = ±V V SUPPLY = ±V V SUPPLY = ±V NORMALIZED TO ±V DATA R L = kω C L = pf BANDWIDTH NEGATIVE SLEW RATE POSITIVE SLEW RATE k k M M FREQUENCY (Hz) FIGURE 8. OUTPUT VOLTAGE SWING vs FREQUENCY SUPPLY VOLTAGE (±V) FIGURE 9. NORMALIZED AC PARAMETERS vs SUPPLY VOLTAGE Die Characteristics SUBSTRATE POTENTIAL: Unbiased TRANSISTOR COUNT: 4 PROCESS: Bipolar Dielectric Isolation Metallization Mask Layout HA-, HA-, HA- COMP V+ OUT BAL BAL -IN +IN V- 7 FN894.8 November, 6

8 HA-, HA-, HA- Metal Can Packages (Can) ØD ØD F Q A REFERENCE PLANE Øb A A L L L Øb Øb ØD. (All leads) Øb applies between L and L. Øb applies between L and. from the reference plane. Diameter is uncontrolled in L and beyond. from the reference plane.. Measured from maximum diameter of the product. 3. a is the basic spacing from the centerline of the tab to terminal and b is the basic spacing of each lead or lead position (N - places) from a, looking at the bottom of the package. 4. N is the maximum number of terminal positions.. Dimensioning and tolerancing per ANSI Y4.M Controlling dimension: INCH. Øe BASE AND SEATING PLANE BASE METAL SECTION A-A Øb β e LEAD FINISH N α k k C L T8.C MIL-STD-83 MACY-X8 (A) 8 LEAD METAL CAN PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A Øb Øb Øb ØD ØD ØD e. BSC.8 BSC - e. BSC.4 BSC - F k k L L L Q a 4 BSC 4 BSC 3 b 4 BSC 4 BSC 3 N Rev. /8/94 8 FN894.8 November, 6

9 HA-, HA-, HA- Ceramic Dual-In-Line Frit Seal Packages (CERDIP) BASE PLANE SEATING PLANE S b ccc M bbb S b C A - B C A - B S D A A e D S. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer s identification shall not be used as a pin one identification mark.. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b and c apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (, N, N/, and N/+) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b.. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y4.M Controlling dimension: INCH E L M c ea/ S D S aaa M C A - B LEAD FINISH BASE METAL b M (b) SECTION A-A -D- -A- Q -C- A -Bα S ea c D S (c) F8.3A MIL-STD-83 GDIP-T8 (D-4, CONFIGURATION A) 8 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A b b b b c c D E e. BSC.4 BSC - ea.3 BSC 7.6 BSC - ea/. BSC 3.8 BSC - L Q S α aaa bbb ccc M , 3 N Rev. 4/94 9 FN894.8 November, 6

10 Dual-In-Line Plastic Packages (PDIP) HA-, HA-, HA- INDEX AREA BASE PLANE SEATING PLANE D B -C- -A- N 3 N/ B D e D E -B- A. (.) M C A A L B S. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.. Dimensioning and tolerancing per ANSI Y4.M Symbols are defined in the MO Series Symbol List in Section. of Publication No Dimensions A, A and L are measured with the package seated in JEDEC seating plane gauge GS-3.. D, D, and E dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed. inch (.mm). 6. E and e A are measured with the leads constrained to be perpendicular to datum -C-. 7. e B and e C are measured at the lead tips with the leads unconstrained. e C must be zero or greater. 8. B maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed. inch (.mm). 9. N is the maximum number of terminal positions.. Corner leads (, N, N/ and N/ + ) for E8.3, E6.3, E8.3, E8.3, E4.6 will have a B dimension of inch ( mm). A e C E C L e A C e B E8.3 (JEDEC MS--BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A B B , C D D E E e. BSC.4 BSC - e A.3 BSC 7.6 BSC 6 e B L N Rev. /93 FN894.8 November, 6

11 Small Outline Plastic Packages (SOIC) HA-, HA-, HA- N INDEX AREA 3 e D B.(.) M C A M E -B- -A- -C- SEATING PLANE A B S H.(.) M B A α.(.4) L M h x 4. Symbols are defined in the MO Series Symbol List in Section. of Publication Number 9.. Dimensioning and tolerancing per ANSI Y4.M Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed.mm (.6 inch) per side. 4. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.mm (. inch) per side.. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. L is the length of terminal for soldering to a substrate. 7. N is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width B, as measured.36mm (.4 inch) or greater above the seating plane, shall not exceed a maximum value of.6mm (.4 inch).. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. C M8. (JEDEC MS--AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A B C D E e. BSC.7 BSC - H h L N α Rev. 6/ All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN894.8 November, 6