ISL4089. Features. DC-Restored Video Amplifier. Applications. Related Documents. Ordering Information. Pinout FN Data Sheet June 28, 2006

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1 Data Sheet FN9. DCRestored Video Amplifier The is complete DCrestored monolithic video amplifier subsystem. It contains a high performance video amplifier and a nulling, sampleandhold amplifier designed to establish a programmable DC output level. When the HOLD logic input is applied the DC restore function is active. The sampleandhold amplifier loop is closed and used to null the DC offset of the video amplifier. This can occur during sync, or, at any time that a black level is expected. When the HOLD input is applied, the correcting voltage is stored on the video amplifier s input coupling capacitor. This condition must be true during active video. The restored DC voltage level can be adjusted using an external reference voltage applied to the V REF pin. The device operates from a single 5V supply and is ideal for 5V only systems when used with a sync separator, such as the EL3. The is intended to directly replace the EL9 only in certain applications. This direct replacement requires that the single positive supply is no higher than 5.5V and that no part of the clamped output goes below ground. The NC on pin is not internally connected, so it can be connected to the 5V pin in existing EL9 applications. The is specified for operation over C to 5 C temperature range. Pinout IN IN ( Ld SOIC) TOP VIEW V V OUT Features Complete video level DCrestoration system.3% differential gain and.5 differential phase accuracy 3MHz 3dB small signal bandwidth at A V = 5MHz 3dB small signal bandwidth at A V = 3V/µs Slew Rate.dB flatness to MHz 5V single supply operation TTL/CMOS compatible hold signal Pbfree plus anneal available (RoHS compliant) Applications Input amplifier in video equipment DCrestoration amplifier in video mixers Related Documents AN: EVAL User s Guide AN9: EL9 and EL39 DCRestored Video Amplifier Ordering Information PART NUMBER IBZ (See Note) IBZT7 (See Note) PART MARKING TAPE & REEL PACKAGE 9IBZ Ld SO (Pbfree) 9IBZ 7 Ld SO (Pbfree) PKG. DWG. # MDP7 MDP7 NOTE: Intersil Pbfree plus anneal products employ special Pbfree material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pbfree soldering operations. Intersil Pbfree products are MSL classified at Pbfree peak reflow temperatures that meet or exceed the Pbfree requirements of IPC/JEDEC J STD. V REF N/C HOLD CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. INTERSIL or 377 Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc.. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

2 Absolute Maximum Ratings (T A = 5 C) Voltage between V and V Voltage between IN, IN, HOLD, V REF and ;v.5v Supply Turnon Slew Rate V/µs Digital and Analog Input Current (Note ) mA put Current (Continuous) ma ESD Rating Human Body Model (Per MILSTD3 Method 35.7)....3V Machine Model V Storage Temperature Range C to 5 C Ambient Operating Temperature C to 5 C Operating Junction Temperature C to 5 C Power Dissipation See Curves CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A DC Electrical Specifications V = 5V, Load = kω; T A = 5 C PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNIT AMPLIFIER SECTION (HOLD = 5V) Ib IN Input Bias Current V IN =.5V 7 µa Ib IN Input Bias Current V IN =.3V 3 µa A VOL Open Loop Gain db V OUT High put Level R L = k 3.5 V V OUT Low put Level IL = ma 5 mv I SC Short Circuit Current ma RESTORE SECTION V OS, Comp Composite Input Offset Voltage V REF = V to.5v 5 mv I OUT Restoring Current Available 3 µa PSRR Power Supply Rejection Ratio V = 5V to V 7 9 db Ib V REF V REF Input Bias Current V REF =.5V..5. µa V H HOLD HOLD Logic Input Low. V V L HOLD HOLD Logic Input High. V I IH, Hold HOLD Input Logic High V HOLD = 5V 5 3 µa I IL, Hold HOLD Input Logic Low V HOLD = V 5 5 µa I S Supply Current V HOLD = V 7 3 ma AC Electrical Specifications V S = 5V, V REF = V DC, R L = 5Ω, R F and R G = ; A V =, T A = 5 C. PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNITS AMPLIFIER SECTION SR Slew Rate; V PP, % to % 3 V/µs tr, tf put Rise and Fall Times V OUT =.Vpp; % to 9% 3. ns tpd Propagation Delay, IN to put V OUT =.V; % to %.3 ns 3dB BW Small Signal; Unity Gain R F = ; R G = inf.; C L =.pf, V OUT =.V PP 3 MHz Large Signal; Unity Gain R F = ; R G = inf.; C L =.pf, 95 MHz V OUT = V PP Small Signal; A V = C L =.pf, V OUT =.V PP 5 MHz Large Signal; A V = C L =.pf, V OUT = V PP 5 MHz FN9.

3 AC Electrical Specifications V S = 5V, V REF = V DC, R L = 5Ω, R F and R G = ; A V =, T A = 5 C. (Continued) PARAMETER DESCRIPTION CONDITION MIN TYP MAX UNITS.dB BW.dB Gain Flatness; Unity Gain R F = ; R G = inf.; C L =.pf V OUT =.V PP 7 MHz R F = ; R G = inf.; C L =.pf MHz V OUT = V PP.dB Gain Flatness; A V = C L =.pf, V OUT =.V PP MHz C L =.pf, V OUT = V PP 5 MHz dg Differential Gain Error NTC7, Restore on sync tip.3 % dp Differential Phase Error NTC7, Restore on sync tip.5 RESTORE SECTION T HE Time to Enable Hold; 5% to 5% HOLD input V to 5V ns T HD Time to Disable Hold; 5% to 5% HOLD input 5V to V ns NOTE:. If an input signal is applied before the supplies are powered up, the input current must be limited to these maximum values Typical Performance Curves V S = 5V, R L = 5Ω to, C L =.pf, T A = 5 C, unless otherwise specified. V OUT =.V PP R L = 5Ω A V = R F = R G = 5Ω A V = R F = R G = A V = R F = Ω M M M 5M FIGURE. SMALL SIGNAL GAIN vs FREQUENCY for VARIOUS GAINS V OUT = V PP R L = 5Ω A V = R F = R G = A V = R F = R G = 5Ω A V = R F = Ω M M M 5M FIGURE. LARGE SIGNAL GAIN vs FREQUENCY for VARIOUS GAINS V OUT = V PP R L = 5Ω A V = C L =.pf to pf A V = C L =.pf A V = C L = pf V OUT =.V PP R L = 5Ω AV = R F = R G = R F = R G = 3Ω R F = R G = kω M M M 5M FIGURE 3. LARGE SIGNAL GAIN vs FREQUENCY vs C L M M M 5M FIGURE. SMALL SIGNAL GAIN vs R F, R G 3 FN9.

4 Typical Performance Curves V S = 5V, R L = 5Ω to, C L =.pf, T A = 5 C, unless otherwise specified. (Continued) A V = R F = R G = 75 R L = 5 V OUT = V PP. M M M G FIGURE 5..dB GAIN FLATNESS V OUT =.V PP NORMALIZED GAIN ERROR(%) NORMALIZED PHASE ( ) V OUT =.V PP R L = 5 A V = V OUT =.3V PP. f = 3.5MHz. R F = R G =.. V OUT =.V PP.... V OUT =.3V PP V OUT DC (V) FIGURE. DIFFERENTIAL GAIN PHASE.5. OUTPUT VOLTAGE (V) V OUT =.V PP R F = R G = C G =.5pF OUTPUT VOLTAGE (V) V OUT = V PP R F = R G = C G =.5pF TIME (ns/div) TIME (ns/div) FIGURE 7. SMALL SIGNAL TRANSIENT RESPONSE; A V = FIGURE. LARGE SIGNAL TRANSIENT RESPONSE; A V = VOLTAGE NOISE (nv/ Hz) 5 3 k k k FIGURE 9. INPUT NOISE vs FREQUENCY FN9.

5 Typical Performance Curves V S = 5V, R L = 5Ω to, C L =.pf, T A = 5 C, unless otherwise specified. (Continued) JEDEC JESD57 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD JEDEC JESD53 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.7 POWER DISSIPATION (W) mW SO θ JA = C/W POWER DISSIPATION (W) mW SO θ JA = C/W AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE AMBIENT TEMPERATURE ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE ( LD SOIC) PIN NAME EQUIVALENT CIRCUIT DESCRIPTION IN Circuit Video amplifier inverting input N Circuit Video amplifier noninverting input 3 V REF Circuit Restore amplifier V REF input HOLD Circuit Hold/restore logic input. Logic selects the restore state; logic selects the hold state 5 Circuit Ground NIC Circuit No internal connection 7 V OUT Circuit 3 Video amplifier output V Circuit Positive power supply V V IN LOGIC PIN k V CIRCUIT CIRCUIT V OUT CIRCUIT 3 CIRCUIT V CAPACITIVELY COUPLED ESD CLAMP 5 FN9.

6 AC Test Circuits R G R F TEST R S EQUIPMENT V IN 5Ω Ω C L.Ω 5Ω. HOLD INPUT = FIGURE A. VIDEO AMPLIFIER AC TEST CIRCUIT FOR 5Ω R G R F TEST R S EQUIPMENT V IN C L DCRestore Amplifier (Figure 3) The DCrestore circuit contains a voltage reference amplifier and an analog switch function that closes the DCrestore loop under control of the HOLD logic input. The reference amplifier uses an internal mv offset voltage (V) to enable the V REF input to sense down to the negative supply. The A amplifier output stage operates in a currentfeed mode with a source/sink capability of ±3µA (Typ). A logic at the HOLD input closes switch S which closes the DCrestore loop. The video input AC coupling capacitor, CX, acts as a DC hold capacitor (through the termination resistor RX) to average the currentsource output of amplifier A. When the DCrestore loop has reached equilibrium, the DC voltage stored on CX will the value required to force the output voltages at A (V OUT ) and A (V IN ) according to the following: FIGURE B. BACKTERMINATED TEST CIRCUIT FOR VIDEO CABLE APPLICATION. Figure A illustrates the AC test circuit used to operate the video amplifier into a 5Ω load while providing a 5Ω matched impedance. Figure B illustrates the test circuit for impedance matching to test equipment. Application Information General. HOLD INPUT = The implements the video DCrestore function using a high performance gain adjustable video amplifier and a nulling, samplehold amplifier to establish a user defined DC reference voltage at the video amplifier output. A detailed description of the DCrestore function implemented in the can be found in application note AN9, EL9 and EL39 DCRestored Video Amplifier. The performs the same function with the exception that it is designed for single supply operation. Video Amplifier Operation (Figure 3) The video amplifier (A) is voltagefeed, high performance video amplifier designed for 5V operation. The output stage is capable of swinging to within mv of the negative rail. The differential input stage contains an internal voltage reference that positions the noninverting input DC level (V) to ~.V higher than the negative supply rail. This offset ensures that the amplifier input DC level is maintained within the common mode input voltage range. The amplifier noninverting gain is given in Equation. R V OUT ( V IN.V) F = R (EQ. ) G V OUT (DC) = V REF mv (EQ. ) and; the DC voltage at the noninverting input of the video amplifier A is given in Equation 3: V IN = V OUT (DC).V (EQ. 3) Therefore, if V REF is set to V (); V OUT = mv, and the DC voltage stored on CX is ~.V. The CX capacitor value is chosen from the system requirements. A typical DCrestore application using the horizontal sync to drive the HOLD pin will result in a µs hold time. The typical input bias current to the video amplifier is.µa, so for a µs hold time, and a.µf capacitor, the output voltage drift is 7.5mV in one line. The restore amplifier can provide a typical current of 3µA to charge capacitor CX, so with a.µs sampling time, the output can be corrected by 3mV in each line. Using a smaller value of CX increases both the voltage that can be corrected, as well as the droop while being held. Likewise, using a larger value of CX, reduces the correction and droop voltages. A sample of charging and droop rates are shown on the following table. TABLE OF CHARGE STORAGE CAPACITOR VS DROOP CHARGING RATES (NOTE) CAP VALUE (if) DROOP IN µs (mv) CHARGE IN.µs (mv) CHARGE IN µs (mv) NOTE: Basic formulae are: V (droop) = Ib * (Line time Sample time)/capacitor and V (charge) = I OUT * Sample time/capacitor FN9.

7 R G R F VIDEO INPUT RX CX V IN V IN S.V V A k V OUT RXT VIDEO OUT V 5V A.µF.7µF V Ref V to.5v V REF mv V HOLD pf TTL INPUT FIGURE 3. BASIC 5V APPLICATION CIRCUIT Using the Reference Voltage Input (V REF ) Implementing DCrestore and amplifying composite video using a single 5V supply amplifier, requires attention to the performance of the amplifier over the minimum to maximum range of output voltage swing. The differential gain phase plot in Figure shows the amplifier accuracy operating from a single 5V supply, driving a 3mV PP and a mv PP signal into a 5Ω load. Over the output DC voltage range of.5v to 3.5V, differential gain and phase are less than.5% and.5 respectively and defines the optimum output voltage range of the. Figure also shows that as the signal level increases, a corresponding decrease in the output DC level (min/max voltage swing) can be expected. The V REF input enables the output DC voltage level to be optimally programmed within the min/max voltage range, according to Equation. The values in Figure take into account the additional amplifier overhead (3mV PP and mv PP ) needed by the video signal. Although the AC performance degrades below ~.5V, the maintains DC accuracy down to mv. Limiting the put Current No output short circuit current limit exists on these parts. All applications need to limit the output current to less than ma. Adequate thermal heat sinking of the parts is also required. Application Information A typical single supply application circuit using the EL3 sync separator to generate the DCrestore hold command, is shown in Figure 3. The is configured for a gain of, and input and output terminations are used for cable driving; providing an end to end gain of. DCrestore is performed during sync tip using the composite sync output of the EL3, which clamps the 3mV input sync tip level to VDC at the output (Figure 5 lower trace). Clamping sync tip to VDC forces the black level, color burst and active video to the 3mV level at the load in the terminal equipment, and to mv at the output pin. The mv DC offset is safely within the lower linear range of the output (Figure Differential Gain Phase) and the V maximum video amplitude at the output is safely within the upper limit. In applications where the sync tip level can t be guaranteed, positioning the active video within the linear range can be accomplished using the back porch clamp output of the EL3 and supplying V to the V REF input. This has the effect of clamping the back porch to the V V REF level at the output while enabling the negative sync tip level to pass through to the output. 7 FN9.

8 R 75 ohms R5 75 ohms VIDEO INPUT C.uF R3 75 ohms IN IN 3 Vref V Vout NC C, C3.uF R 75 ohms 5V C.7uF Ground Hold Composite Sync Backporch Clamp EL3 Vertical Sync C5.uF 7 Horizontal Sync 3 R7 K C.5 uf 5 FIGURE. APPLICATION CIRCUIT USING THE EL3 SYNC SEPARATOR TO GENERATE DCRESTORE HOLD CONTROL COMPOSITE VIDEO INPUT VDC COMPOSITE SYNC INPUT VDC DCRESTORED VIDEO OUTPUT VDC FIGURE 5. DCRESTORE USING COMPOSITE SYNC AND V REF = VDC FN9.

9 Small line Package Family (SO) A D h X 5 N (N/) A E E PIN # I.D. MARK c SEE DETAIL X (N/) B. M C A B L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) SYMBOL SO SO SO (.5 ) SO (.3 ) (SOL) SO (SOL) SO (SOL) SO (SOL) TOLERANCE NOTES A MAX A ±.3 A ±. b ±.3 c ±. D ±., 3 E ±. E ±., 3 e Basic L ±.9 L Basic h Reference N Reference Rev. L / NOTES:. Plastic or metal protrusions of. maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M99 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9 quality systems. Intersil Corporation s quality certifications can be viewed at Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see 9 FN9.