DATASHEET EL1503A. Features. Applications. Pinouts. High Power Differential Line Driver. FN7039 Rev 2.00 Page 1 of 17. March 26, FN7039 Rev 2.

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1 DATASHEET EL3A High Power Differential Line Driver The EL3A ADSL Line Driver contains two wideband high-voltage drivers which are ideally suited for both ADSL and HDSL2 applications. They can supply a 3.2V P-P signal into a 22 load while exhibiting very low distortion. The EL3A also has a number of power saving features. The I ADJ pin can be used to set the maximum supply current and the C and C pins can be used to digitally vary the supply current to one of four modes. These modes include full power, low power, terminate only and power down. The EL3A uses current-feedback type amplifiers, which achieve a high slew rate while consuming moderate power. They retain their frequency response over a wide range of externally set gains. The EL3A operates on ±V to ±2V supplies and consumes only 2.mA per amplifier. The device is supplied in a thermally-enhanced Ld SOIC (.3 ) and the small footprint (4xmm) 24 Ld QFN packages. Center pins on each side of the Ld and 6 Ld packages are used as ground connections and heat spreaders. The QFN package has the potential for a low JA (<4 C/W) and dissipates heat by means of a thermal pad that is soldered onto the PCB. All package options are specified for operation over the full -4 C to +8 C temperature range. Pinouts EL3A (24 LD QFN) TOP VIEW Features High power ADSL driver 3.2V P-P differential output drive into V P-P differential output drive into 6 Driver 2 nd /3 rd harmonics of -66dBc/-72dBc at 2V P-P into differential Supply current of 2.mA per amplifier Supply current control Power saving modes Standard surface-mount packages Ultra-small QFN package Pb-free plus anneal available (RoHS compliant) Applications ADSL line drivers HDSL2 line drivers Video distribution amplifiers EL3A [ LD SOIC (.3 )] TOP VIEW FN73 Rev 2. VOUTA 24 VIN-A 23 NC 22 VIN-B 2 VOUTB VIN-A VOUTA 2 VIN-B VOUTB NC NC 2 NC 8 NC VS- * 3 4 A B VS+ 7 * VS- 3 7 VS+ * 6 * NC NC 4 THERMAL PAD 6 NC NC * * 6 7 * 4 * NC 6 4 NC VIN+A 8 3 VIN+B C C POWER CONTROL LOGIC 2 IADJ NC VIN+A C C IADJ VIN+B * pins are heat spreaders FN73 Rev 2. Page of 7

2 Ordering Information PART NUMBER PART MARKING TAPE & REEL PACKAGE PKG. DWG. # EL3ACM EL3ACM - Ld SOIC (.3") MDP27 EL3ACM-T3 EL3ACM 3 Ld SOIC (.3") MDP27 EL3ACMZ (See Note) EL3ACMZ - Ld SOIC (.3") (Pb-Free) MDP27 EL3ACMZ-T3 (See Note) EL3ACMZ 3 Ld SOIC (.3") (Pb-Free) MDP27 EL3ACL 3ACL - 24 Ld QFN MDP46 EL3ACL-T7 3ACL 7 24 Ld QFN MDP46 EL3ACL-T3 3ACL 3 24 Ld QFN MDP46 EL3ACLZ (See Note) 3ACLZ - 24 Ld QFN (Pb-Free) MDP46 EL3ACLZ-T7 (See Note) 3ACLZ 7 24 Ld QFN (Pb-Free) MDP46 EL3ACLZ-T3 (See Note) 3ACLZ 3 24 Ld QFN (Pb-Free) MDP46 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN73 Rev 2. Page 2 of 7

3 s Absolute Maximum Ratings (T A = + C) V S + to V S - Supply Voltage V V S + Voltage to Ground V to +28V V S - Voltage to Ground V to.3v Input C /C to Ground V to +7V Driver V IN + Voltage V S - to V S + Current into any Input mA Output Current from Driver (static) ma Operating Temperature Range C to +8 C Storage Temperature Range C to + C Operating Junction Temperature C to + C Power Dissipation See Curves CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S = ±2V, R F =.k, R L = 6, I ADJ = C = C = V, T A = + C. Amplifiers tested separately. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT SUPPLY CHARACTERISTICS I S + (Full Power) Positive Supply Current per Amplifier All outputs at V, C = C = V 2. 6 ma I S - (Full Power) Negative Supply Current per Amplifier All outputs at V, C = C = V ma I S + (Low Power) Positive Supply Current per Amplifier All outputs at V, C = V, C = V 7. ma I S - (Low Power) Negative Supply Current per Amplifier All outputs at V, C =V, C = V ma I S + (Terminate) Positive Supply Current per Amplifier All outputs at V, C = V, C = V 4. 7 ma I S - (Terminate) Negative Supply Current per Amplifier All outputs at V, C = V, C = V ma I S + (Power Down) Positive Supply Current per Amplifier All outputs at V, C = C = V.7..7 ma I S - (Power Down) Negative Supply Current per Amplifier All outputs at V, C = C = V ma I Supply Current per Amplifier All outputs at V - ma INPUT CHARACTERISTICS V OS Input Offset Voltage -3 3 mv V OS V OS Mismatch - mv I B + Non-Inverting Input Bias Current - µa I B - Inverting Input Bias Current - µa I B - I B - Mismatch -3 3 µa R OL Transimpedance.4.8 M e N Input Noise Voltage 3. nv/ Hz i N -Input Noise Current 3 pa/ Hz V IH Input High Voltage C & C inputs 2.7 V V IL Input Low Voltage C & C inputs.8 V I IH Input High Current for C C = V. 8 µa I IH Input High Current for C C = V.7 4 µa I IL Input Low Current for C or C C = V, C = V - µa OUTPUT CHARACTERISTICS V OUT Loaded Output Swing R L = 6 ±.3 ±.6 V R L = 22 ±.3 ±.8 V I OL Linear Output Current A V =, R L =, f = khz, THD = --6dBc 4 ma I OUT Output Current V OUT = V, R L = A FN73 Rev 2. Page 3 of 7

4 Electrical Specifications V S = ±2V, R F =.k, R L = 6, I ADJ = C = C = V, T A = + C. Amplifiers tested separately. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT DYNAMIC PERFORMANCE BW -3dB Bandwidth A V = + 8 MHz HD2 2nd Harmonic Distortion f C = Hz, R L = V OUT = 2V P-P -76 dbc f C = Hz, R L = V OUT = 2V P-P -72 dbc HD3 3rd Harmonic Distortion f C = Hz, R L = V OUT = 2V P-P -76 dbc f C = Hz, R L = V OUT = 2V P-P -72 dbc SR Slewrate V OUT from -8V to +8V Measured at ±4V 7 V/µs Typical Performance Curves A V = R L = R F =.k R F =2.k R F =2.43k R F =.3k A V = R L = R F =.k R F =2.k R F =2.4k R F =.3k K M M K M M FIGURE. DIFFERENTIAL FREQUENCY RESPONSE vs R F (FULL POWER MODE) FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs R F (FULL POWER MODE) A V = R L = R F =.k R F =.3k A V = R L = R F =.3k R F =.k R F =2.k R F =2.k K R F =2.43k M M K R F =2.4k M M FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE vs R F (2/3 POWER MODE) FIGURE 4. DIFFERENTIAL FREQUENCY RESPONSE vs R F (2/3 POWER MODE) FN73 Rev 2. Page 4 of 7

5 Typical Performance Curves (Continued) R F =2.k R F =2.43k A V = R L = A V = R L = R F =.84k R F =2.k R F =2.43k M M K K M M FIGURE. DIFFERENTIAL FREQUENCY RESPONSE vs R F (TERMINATE MODE) FIGURE 6. DIFFERENTIAL FREQUENCY RESPONSE vs R F (TERMINATE MODE) R L = R F =.3k R F =.k R L = R F =.k 4 R F =2.k R F =2.4k 4 R F =2.k R F =2.4k R F =2.74k K M M K M M FIGURE 7. DIFFERENTIAL FREQUENCY RESPONSE vs R F (FULL POWER MODE) FIGURE 8. DIFFERENTIAL FREQUENCY RESPONSE vs R F (FULL POWER MODE) R L = R F =.3k R F =.k R L = R F =.k R F =2.k 4 R F =2.k R F =2.43k 4 R F =2.4k K M M K M M FIGURE. DIFFERENTIAL FREQUENCY RESPONSE vs R F (2/3 POWER MODE) FIGURE. DIFFERENTIAL FREQUENCY RESPONSE vs R F (2/3 POWER MODE) FN73 Rev 2. Page of 7

6 Typical Performance Curves (Continued) R F =2.k R F =2.43k R F =2.k 4 4 R F =2.4k R L = K M M R L = K M M FIGURE. DIFFERENTIAL FREQUENCY RESPONSE vs R F (TERMINATE MODE) FIGURE 2. DIFFERENTIAL FREQUENCY RESPONSE vs R F (TERMINATE MODE) I S + (FULL POWER) I S - (FULL POWER) e N (nv/ Hz) i N e N i N (pa/ Hz) I S (ma) I S + (2/3 POWER) I S - (2/3 POWER) I S + (TERMINATE) I S - (TERMINATE) K K K V S (V) FIGURE 3. INPUT VOLTAGE and FEEDBACK CURRENT NOISE vs FREQUENCY FIGURE 4. SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY REJECTION (db) LEFT RIGHT SUPPLY REJECTION (db) LEFT RIGHT - K K M M FIGURE. POSITIVE SUPPLY REJECTION vs FREQUENCY - K K M M FIGURE 6. NEGATIVE SUPPLY REJECTION vs FREQUENCY FN73 Rev 2. Page 6 of 7

7 Typical Performance Curves (Continued) OUTPUT IMPEDANCE ( ) A V = R L =.k TERMINATE 2/3 POWER FULL POWER OUTPUT IMPEDANCE ( ) A V = R L =.k TERMINATE 2/3 POWER FULL POWER K K M M K K M M FIGURE 7. OUTPUT IMPEDANCE vs FREQUENCY FIGURE 8. OUTPUT IMPEDANCE vs FREQUENCY -4 - R L = f C =Hz -4-4 R - L = f C =Hz - HD (db) -6-7 HD3 HD2 HD (db) HD3 HD FIGURE. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER) FIGURE. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER) R L = f C =Hz -4 - R L = f C =Hz HD (db) HD3 HD2 HD (db) -6-7 HD3 HD FIGURE 2. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER) FIGURE 22. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE FN73 Rev 2. Page 7 of 7

8 Typical Performance Curves (Continued) R L = f C =Hz -4 - R L = f C =Hz THD (db) /3 POWER THD (db) -6 FULL POWER -7-7 FULL POWER -7 2/3 POWER FIGURE 23. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE FIGURE 24. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE HD2-6 HD HD (db) HD (db) HD3 R L = f C =Hz HD3 R L = f C =Hz FIGURE. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER) FIGURE 26. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (FULL POWER) HD (db) R L = f C =Hz HD2 HD (db) R L = f C =Hz HD HD HD FIGURE 27. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER) FIGURE 28. DIFFERENTIAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE (2/3 POWER) FN73 Rev 2. Page 8 of 7

9 Typical Performance Curves (Continued) THD (dbc) R L = f C =Hz 2/3 POWER FULL POWER THD (dbc) R L = f C =Hz 2/3 POWER FULL POWER FIGURE 2. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE FIGURE 3. DIFFERENTIAL TOTAL HARMONIC DISTORTION vs OUTPUT AMPLITUDE BW (MHz) 3 3 ±V S (V) FULL POWER MODE 2/3 POWER MODE A V = TERMINATE MODE PEAKING (db) ±V S (V) A V = TERMINATE MODE 2/3 POWER MODE FULL POWER MODE FIGURE 3. DIFFERENTIAL BANDWIDTH vs SUPPLY VOLTAGE FIGURE 32. DIFFERENTIAL PEAKING vs SUPPLY VOLTAGE ±I S (ma) I S + (FULL POWER) I S - (FULL POWER) I S + 2/3 POWER) I S - 2/3 POWER) V S = ±2V R SET to I S + (TERMINATE) I S - (TERMINATE) ±I S (ma) I S + (FULL POWER) I S - (FULL POWER) I S + 2/3 POWER) V S = ±V R SET to I S - 2/3 POWER) I S + (TERMINATE) I S - (TERMINATE) R SET (k ) R SET (k ) FIGURE 33. I S vs R SET FIGURE 34. I S vs R SET FN73 Rev 2. Page of 7

10 Typical Performance Curves (Continued) ±I S (ma) V S = ±2V I S + (FULL POWER) I S - (FULL POWER) I S + (2/3 POWER) I S - (2/3 POWER) I S + (TERMINATE) I S - (TERMINATE) ±I S (ma) V S = ±2V I S + (FULL POWER) I S - (FULL POWER) I S + (2/3 POWER) I S - (2/3 POWER) I S + (TERMINATE) I S - (TERMINATE) 3 4 I SET (µa) 3 4 I SET (µa) FIGURE 3. I S vs I SET FIGURE 36. I S vs I SET POWER DISSIPATION (W) JA = 3 C/W JA = 43 C/W JA = 3 C/W JA = 8 C/W AMBIENT TEMPERATURE ( C) FIGURE 37. POWER DISSIPATION vs AMBIENT TEMPERATURE for VARIOUS MOUNTED JA s POWER DISSIPATION (W) POWER DISSIPATION & THERMAL RESISTANCE USING JEDEC JESD-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD- 2.73W QFN24 JA =37 C/W 7 8 AMBIENT TEMPERATURE ( C) FIGURE 38. POWER DISSIPATION vs AMBIENT TEMPERATURE FN73 Rev 2. Page of 7

11 Test Circuit V IN -A V IN -B 2 V OUT A V OUT B 3 V S - V S V IN +A V IN +B 3 C I ADJ 2 C NC R 3 6 /2W R S W R 4 6 /2W R R 6 LEFT OUT.k 2.k RIGHT OUT.µF µf 3 A - + B µf.µf V S + TANTALUM 4 7 TANTALUM C 2 6 C LEFT IN R R 7 RIGHT IN R SET C C FN73 Rev 2. Page of 7

12 Pin Descriptions Ld SOIC (.3") 24 Ld QFN PIN NAME FUNCTION CIRCUIT 23 V IN -A Channel A Inverting Input CIRCUIT 2 24 V OUT A Channel A Output (Reference Circuit ) 3 3 V S - Negative Supply 4,, 6, 7 7 Ground Connection 8 8 V IN +A Channel A Non-Inverting Input V S + V S - CIRCUIT 2 C Current Control Bit V S + 6.7V C Current Control Bit (Reference Circuit 3) CIRCUIT 3, 2, 4,, 6, 4,, 6, 8,, 22 NC Not Connected 2 I ADJ Supply Current Control Pin V S + CIRCUIT V IN +B Channel B Non-Inverting Input (Reference Circuit 2) 4,, 6, 7 3 Ground Connection 8 7 V S + Positive Supply V OUT B Channel B Output (Reference Circuit ) 2 V IN -B Channel B Inverting Input (Reference Circuit ) - 7 Reserve for Future Use Internally Unconnected FN73 Rev 2. Page 2 of 7

13 Applications Information The EL3A consists of two high-power line driver amplifiers that can be connected for full duplex differential line transmission. The amplifiers are designed to be used with signals up to 4MHz and produce low distortion levels. A typical interface circuit is shown in Figure 3 below. INPUT RECEIVE OUT - R G + - R F - + RECEIVE OUT + RECEIVE AMPLIFIERS R F R F R F R R IN R R IN R OUT R OUT LINE + FIGURE 3. TYPICAL LINE INTERFACE CONNECTION Z LINE LINE - The amplifiers are wired with one in positive gain and the other in a negative gain configuration to generate a differential output for a single-ended input. They will exhibit very similar frequency responses for gains of three or greater and thus generate very small common-mode outputs over frequency, but for low gains the two drivers R F 's need to be adjusted to give similar frequency responses. The positive-gain driver will generally exhibit more bandwidth and peaking than the negative-gain driver. If a differential signal is available to the drive amplifiers, they may be wired so: 2R G + - R F - + FIGURE 4. S WIRED FOR DIFFERENTIAL INPUT Each amplifier has identical positive gain connections, and optimum common-mode rejection occurs. Further, DC input errors are duplicated and create common-mode rather than differential line errors. Input Connections The EL3A amplifiers are somewhat sensitive to source impedance. In particular, they do not like being driven by inductive sources. More than nh of source impedance R F can cause ringing or even oscillations. This inductance is equivalent to about 4 of unshielded wiring, or 6 of unterminated transmission line. Normal high-frequency construction obviates any such problem. Power Supplies & Dissipation Due to the high power drive capability of the EL3A, much attention needs to be paid to power dissipation. The power that needs to be dissipated in the EL3A has two main contributors. The first is the quiescent current dissipation. The second is the dissipation of the output stage. The quiescent power in the EL3A is not constant with varying outputs. In reality, 7mA of the 2.mA needed to power each driver is converted in to output current. Therefore, in the equation below we should subtract the average output current, I O, or 7mA, whichever is the lowest. We ll call this term I X. Therefore, we can determine a quiescent current with the equation: P Dquiescent = V S I S 2I X where: V S is the supply voltage (V S + to V S -) I S is the maximum quiescent supply current (I S + + I S -) I X is the lesser of I O or 7mA (generally I X = 7mA) The dissipation in the output stage has two main contributors. Firstly, we have the average voltage drop across the output transistor and secondly, the average output current. For minimal power dissipation, the user should select the supply voltage and the line transformer ratio accordingly. The supply voltage should be kept as low as possible, while the transformer ratio should be selected so that the peak voltage required from the EL3A is close to the maximum available output swing. There is a trade of however with the selection of transformer ratio. As the ratio is increased, the receive signal available to the receivers is reduced. Once the user has selected the transformer ratio, the dissipation in the output stages can be selected with the following equation: V S P Dtransistors = 2 I O V 2 O where: V S is the supply voltage (V S + to V S -) V O is the average output voltage per channel I O is the average output current per channel The overall power dissipation (P DISS ) is obtained by adding P Dquiescent and P Dtransistor. FN73 Rev 2. Page 3 of 7

14 Then, the JA requirement needs to be calculated. This is done using the equation: T JUNCT T AMB JA = where: T JUNCT is the maximum die temperature ( C) T AMB is the maximum ambient temperature P DISS is the dissipation calculated above JA is the junction to ambient thermal resistance for the package when mounted on the PCB This JA value is then used to calculate the area of copper needed on the board to dissipate the power. The graph below show various JA for the SO mounted on different copper foil areas. MOUNTED DEVICE JA ( C/W) P DISS A separate application note details the 24 Ld QFN PCB design considerations. Single Supply Operation The EL3A can also be powered from a single supply voltage. When operating in this mode, the pins can still be connected directly to. To calculate power dissipation, the equations in the previous section should be used, with V S equal to half the supply rail. EL3A PCB Design Note: 2oz. COPPER USED TOP FOIL ONLY-WITH SOLDER MASK TOP FOIL-WITH.4IN 2 BOTTOM FOIL WITH MANY FEEDTHROUGHS TOP FOIL ONLY-NO SOLDER MASK AREA OF CIRCUIT BOARD HEAT SINK (in 2 ) FIGURE 4. THERMAL RESISTANCE of Ld SOIC (.3") EL3A vs BOARD COPPER AREA A separate application note details the 24 Ld QFN PCB design considerations. The SOIC power packages ( leads) are designed so that heat may be conducted away from the device in an efficient manner. To disperse this heat, the center leads (4 per side for the lead and 2 per side for the 6 lead) are internally connected to the mounting platform of the die. Heat flows through the leads into the circuit board copper, then spreads and convects to air. Thus, the ground plane on the component side of the board becomes the heatsink. This has proven to be a very effective technique, but several aspects of board layout should be noted. First, the heat should not be shunted to internal copper layers of the board nor backside foil, since the feedthroughs and fiberglass of the board are not very thermally conductive. To obtain the best thermal resistance of the mounted part, JA, the topside copper ground plane should have as much area as possible and be as thick as practical. If possible, the solder mask should be cut away from the EL3A to improve thermal resistance. Finally, metal heatsinks can be placed against the board close to the part to draw heat toward the chassis. Output Loading While the drive amplifiers can output in excess of ma transiently, the internal metallization is not designed to carry more than ma of steady DC current and there is no current-limit mechanism. This allows safely driving rms sinusoidal currents of 2 X ma, or ma. This current is more than that required to drive line impedances to large output levels, but output short circuits cannot be tolerated. The series output resistor will usually limit currents to safe values in the event of line shorts. Driving lines with no series resistor is a serious hazard. The amplifiers are sensitive to capacitive loading. More than pf will cause peaking of the frequency response. The same is true of badly terminated lines connected without a series matching resistor. Power Supplies The power supplies should be well bypassed close to the EL3A. A 3.3µF tantalum capacitor for each supply works well. Since the load currents are differential, they should not travel through the board copper and set up ground loops that can return to amplifier inputs. Due to the class AB output stage design, these currents have heavy harmonic content. If the ground terminal of the positive and negative bypass capacitors are connected to each other directly and then returned to circuit ground, no such ground loops will occur. This scheme is employed in the layout of the EL3A demonstration board, and documentation can be obtained from the factory. Feedback Resistor Value The bandwidth and peaking of the amplifiers varies with supply voltage somewhat and with gain settings. The feedback resistor values can be adjusted to produce an optimal frequency response. Here is a series of resistor values that produce an optimal driver frequency response (db peaking) for different supply voltages and gains: TABLE. OPTIMUM FEEDBACK RESISTOR for VARIOUS GAINS and SUPPLY VOLTAGES SUPPLY VOLTAGE ±V ±2V VOLTAGE GAIN k 2.2k 2.2k 2.k 2.k 2.k FN73 Rev 2. Page 4 of 7

15 Power Control Function The EL3A contains two forms of power control operation. Two digital inputs, C and C, can be used to control the supply current of the EL3A drive amplifiers. As the supply current is reduced, the EL3A will start to exhibit slightly higher levels of distortion and the frequency response will be limited. The 4 power modes of the EL3A are set up as shown in the table 2. TABLE 2. POWER MODES of the EL3A C C OPERATION I S full power mode (CO or CP) 2/3 I S power mode (CO or CP) /3 I S terminate only mode Another method for controlling the power consumption of the EL3A is to connect a resistor from the I ADJ pin to ground. When this pin is grounded (the normal state), the supply current per channel is as per the specifications table on page 3. When a resistor is inserted, the supply current is scaled according to the I S vs R SET graphs on page in the Performance Curves section. Both methods of power control can be used simultaneously. In this case, positive and negative supply currents (per amp) are given by the equations below: 2.mA I S + = ma + C R SET k 2.mA + C R SET k Power down 2.mA I S - = + C R SET k 2.mA + C R SET k Copyright Intersil Americas LLC 2-7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN73 Rev 2. Page of 7

16 Small Outline Package Family (SO) A D h X 4 N (N/2)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/2) L C e H A2 SEATING PLANE GAUGE PLANE..4 C. M C A B b A DETAIL X L 4 ±4 MDP27 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (.3 ) SO SO24 SO28 SYMBOL SO-8 SO-4 (. ) (SOL-6) (SOL-) (SOL-24) (SOL-28) TOLERANCE NOTES A MAX - A A b c D , 3 E E , 3 e Basic - L L Basic - h Reference - N Reference - Rev. M 2/7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included. 2. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.M-4 FN73 Rev 2. Page 6 of 7

17 QFN (Quad Flat No-Lead) Package Family A 2X.7 C (E2) C 2 3 SEATING PLANE N LEADS L N (N-) (N-2) b (N/2) e PIN # I.D. MARK TOP VIEW (N/2). M C A B (N-2) (N-) N BOTTOM VIEW A DETAIL X 2 3. C.8 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D2) 2 7 (L) NE N LEADS E B 2X.7 C PIN # I.D. 3 MDP46 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-2) MILLIMETERS SYMBOL QFN44 QFN3 QFN32 TOLERANCE NOTES A.... ±. - A /-.2 - b ±.2 - c.... Reference - D Basic - D /2.48 Reference 8 E Basic - E /3.4 Reference 8 e...8. Basic - L ±. - N Reference 4 ND Reference 6 NE 2 8 Reference MILLIMETERS TOLER- SYMBOL QFN28 QFN2 QFN QFN6 ANCE NOTES A..... ±. - A / b ±.2 - c..... Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±. - N Reference 4 ND 6 4 Reference 6 NE Reference Rev 2/7 NOTES:. Dimensioning and tolerancing per ASME Y4.M Tiebar view shown is a non-functional feature. 3. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN73 Rev 2. Page 7 of 7