DATASHEET EL2126. Features. Applications. Pinouts. Ultra-Low Noise, Low Power, Wideband Amplifier. FN7046 Rev 4.00 Page 1 of 19.

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1 DATASHEET EL6 Ultra-Low Noise, Low Power, Wideband Amplifier The EL6 is an ultra-low noise, wideband amplifier that runs on half the supply current of competitive parts. It is intended for use in systems such as ultrasound imaging where a very small signal needs to be amplified by a large amount without adding significant noise. Its low power dissipation enables it to be packaged in the tiny SOT-3 package, which further helps systems where many input channels create both space and power dissipation problems. The EL6 is stable for gains of and greater and uses traditional voltage feedback. This allows the use of reactive elements in the feedback loop, a common requirement for many filter topologies. It operates from ±.5V to ±5V supplies and is available in the 5 Ld SOT-3 and Ld SO packages. The EL6 is fabricated in Elantec s proprietary complementary bipolar process, and is specified for operation over the full - C to +5 C temperature range. Pinouts EL6 (5 LD SOT-3) TOP VIEW Features Voltage noise of only.3nv/ Hz Current noise of only.pa/ Hz µv offset voltage MHz -3dB BW for A V = Very low supply current -.7mA SOT-3 package ±.5V to ±5V operation Pb-free plus anneal available (RoHS compliant) Applications Ultrasound input amplifiers Wideband instrumentation Communication equipment AGC and PLL active filters Wideband sensors FN76 Rev. May, 7 OUT 5 VS+ VS- + - IN+ 3 IN- EL6 ( LD SOIC) TOP VIEW NC NC IN- IN VS+ OUT VS- 5 NC FN76 Rev. Page of 9 May, 7

2 Ordering Information PART NUMBER PART MARKING TEMP RANGE ( C) TAPE AND REEL PACKAGE PKG. DWG. # EL6CW-T7 G - to +5 7 (3k pcs) 5 Ld SOT-3 MDP3 EL6CW-T7A G - to +5 7 (5 pcs) 5 Ld SOT-3 MDP3 EL6CS 6CS - to +5 - Ld SOIC (5 mil) MDP7 EL6CS-T7 6CS - to +5 7 Ld SOIC (5 mil) MDP7 EL6CS-T3 6CS - to +5 3 Ld SOIC (5 mil) MDP7 EL6CSZ ( Note) 6CSZ - to +5 - Ld SOIC (5 mil) (Pb-free) EL6CSZ-T7 ( Note) 6CSZ - to +5 7 Ld SOIC (5 mil) (Pb-free) EL6CSZ-T3 ( Note) 6CSZ - to +5 3 Ld SOIC (5 mil) (Pb-free) EL6CWZ-T7 (Note) BAAH - to Ld SOT-3 (SC7) (.65mm) (Green) EL6CWZ-T7A (Note) BAAH - to Ld SOT-3 (SC7) (.65mm) (Green) MDP7 MDP7 MDP7 P5.6 P5.6 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-. FN76 Rev. Page of 9 May, 7

3 Absolute Maximum Ratings V S + to V S -) V Continuous Output Current ma Any Input V S + -.3V to V S - +.3V Thermal Information Operating Temperature C to +5 C Storage Temperature C to +5 C Maximum Die Junction Temperature C Power Dissipation See Curves Pb-free reflow profile see link below CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, R F =, R G =, R L = 5 Unless Otherwise Specified. Parameter Description Conditions Min Typ Max Unit DC PERFORMANCE V OS Input Offset Voltage (SO). mv Input Offset Voltage (SOT3-5) 3 mv T CVOS Offset Voltage Temperature Coefficient 7 µv/ C I B Input Bias Current - -7 µa I OS Input Bias Current Offset.6.6 µa T CIB Input Bias Current Temperature Coefficient.3 µa/ C C IN Input Capacitance. pf A VOL Open Loop Gain V O = -.5V to +.5V 7 db PSRR Power Supply Rejection Ratio (Note ) db CMRR Common Mode Rejection Ratio at CMIR 75 6 db CMIR Common Mode Input Range V V OUTH Positive Output Voltage Swing No load, R F = k V V OUTL Negative Output Voltage Swing No load, R F = k V V OUTH Positive Output Voltage Swing R L = V V OUTL Negative Output Voltage Swing R L = V I OUT Output Short Circuit Current (Note ) ma I SY Supply Current ma AC PERFORMANCE - R G =, C L = 3pF BW -3dB Bandwidth, R L = 5 MHz BW ±.db ±.db Bandwidth, R L = 5 7 MHz BW ±db ±db Bandwidth, R L = 5 MHz Peaking Peaking, R L = 5.6 db SR Slew Rate V OUT = V P-P, measured at % to % V/µs OS Overshoot, V P-P Output Square Wave Positive. % Negative -7 % t S Settling Time to.% of ±V Pulse 5 ns FN76 Rev. Page 3 of 9 May, 7

4 Electrical Specifications V S + = +5V, V S - = -5V, T A = +5 C, R F =, R G =, R L = 5 Unless Otherwise Specified. Parameter Description Conditions Min Typ Max Unit V N Voltage Noise Spectral Density.3 nv/ Hz I N Current Noise Spectral Density. pa/ Hz HD nd Harmonic Distortion (Note 3) -7 dbc HD3 3rd Harmonic Distortion (Note 3) -7 dbc NOTES:. Measured by moving the supplies from ±V to ±6V. Pulse test only and using a load 3. Frequency = MHz, V OUT = V P-P, into 5 and 5pF load Electrical Specifications V S + = +5V, V S - = -5V, T A = 5 C, R F =, R G =, R L = 5 unless otherwise specified. Parameter Description Conditions Min Typ Max Unit DC PERFORMANCE V OS Input Offset Voltage (SO).5 3 mv Input Offset Voltage (SOT3-5) 3 mv T CVOS Offset Voltage Temperature Coefficient.5 µv/ C I B Input Bias Current - -7 µa I OS Input Bias Current Offset..7 µa T CIB Input Bias Current Temperature Coefficient.6 µa/ C C IN Input Capacitance. pf A VOL Open Loop Gain 9 db PSRR Power Supply Rejection Ratio (Note ) 65 db CMRR Common Mode Rejection Ratio at CMIR 7 5 db CMIR Common Mode Input Range V V OUTH Positive Output Voltage Swing No load, R F = k V V OUTL Negative Output Voltage Swing No load, R F = k V V OUTH Positive Output Voltage Swing R L =, R F = k.. V V OUTL Negative Output Voltage Swing R L =, R F = k V I OUT Output Short Circuit Current (Note 5) ma I SY Supply Current 5 6 ma AC PERFORMANCE - R G =, C L = 3pF BW -3dB Bandwidth, R L = 5 35 MHz BW ±.db ±.db Bandwidth, R L = 5 6 MHz BW ±db ±db Bandwidth, R L = 5 6 MHz Peaking Peaking, R L = 5. db SR OS Slew Rate (±.5V Square Wave, Measured 5%-75%) Overshoot, V P-P Output Square Wave 3 5 V/µS Positive.6 % Negative -. % T S Settling Time to.% of ±V Pulse ns FN76 Rev. Page of 9 May, 7

5 Electrical Specifications V S + = +5V, V S - = -5V, T A = 5 C, R F =, R G =, R L = 5 unless otherwise specified. (Continued) Parameter Description Conditions Min Typ Max Unit V N Voltage Noise Spectral Density. nv/ Hz I N Current Noise Spectral Density. pa/ Hz HD nd Harmonic Distortion (Note 6) -7 dbc HD3 3rd Harmonic Distortion (Note 6) -73 dbc NOTES:. Measured by moving the supplies from ±3.5V to ±6.5V 5. Pulse test only and using a load 6. Frequency = MHz, V OUT = V P-P, into 5 and 5pF load Typical Performance Curves A V = R L = 5 R F = k R F = 5 R F = R F = A V = R L = 5 R F = k R F = 5 R F = R F = - M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS RF - M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS RF - - A V = - R L = 5 R F = 5 R F = k R F = 35 R F = R F = - - A V = - R L = 5 R F = k R F = 5 R F = 35 R F = R F = - M M M FIGURE 3. INVERTING FREQUENCY RESPONSE FOR VARIOUS RF - M M M FIGURE. INVERTING FREQUENCY RESPONSE FOR VARIOUS RF FN76 Rev. Page 5 of 9 May, 7

6 Typical Performance Curves (Continued) R G = R L = 5 A V = 5 A V = A V = R G = R L = 5 A V = 5 A V = A V = - M M M FIGURE 5. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS GAIN - M M M FIGURE 6. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS GAIN - - R G = 35 A V = -5 A V = - A V = R G = A V = -5 A V = - A V = - - M M M FIGURE 7. INVERTING FREQUENCY RESPONSE FOR VARIOUS GAIN - M M M FIGURE. INVERTING FREQUENCY RESPONSE FOR VARIOUS RF - - R L = 5 R F = A V = V O = 5V PP VO = 5mV PP V O =.5V PP V O = 3mV PP R L = 5 R F = A V = V O = V PP V O = 5V PP V O = 5mV PP V O = V PP V O = 3mV PP V O = V PP - M M M FIGURE 9. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS V O =.5V PP - M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS FN76 Rev. Page 6 of 9 May, 7

7 Typical Performance Curves (Continued) - - R L = 5 R F = 35 A V = V O = V PP V O = 3.V PP V O =.5V PP V O = 5mV PP V O = 3mV PP - - R L = 5 R F = A V = V O = 5mV PP V O = 3mV PP V O = V PP V O = 3.V PP V O V= O =.5V PPP - M M M FIGURE. INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS - M M M FIGURE. INVERTING FREQUENCY RESPONSE FOR VARIOUS OUTPUT SIGNAL LEVELS R F = 5 A V = R L = 5 C L = pf C L = pf C L = 6pF C L = pf R F = A V = R L = 5 C L = pf C L = pf C L = 6pF C L =.pf - M M M FIGURE 3. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS CL - M M M FIGURE. NON-INVERTING FREQUENCY RESPONSE FOR VARIOUS CL - - R F = 35 R L = 5 A V = - C L = pf C L = 6pF C L = pf C L =.pf - - R F = R L = 5 A V = - C L = pf C L = 6pF C L C= L =p pf C L =.pf - M M M FIGURE 5. INVERTING FREQUENCY RESPONSE FOR VARIOUS CL - M M M FIGURE 6. INVERTING FREQUENCY RESPONSE FOR VARIOUS CL FN76 Rev. Page 7 of 9 May, 7

8 Typical Performance Curves (Continued) 5 OPEN LOOP GAIN (db) 6 GAIN PHASE OPEN LOOP PHASE ( ) SUPPLY CURRENT (ma).6/div V S =±5V -5 k k M M M G.5/DIV SUPPLY VOLTAGE (V) FIGURE 7. OPEN LOOP GAIN AND OPEN LOOP PHASE FIGURE. SUPPLY CURRENT vs SUPPLY VOLTAGE -3dB BANDWIDTH 6 6 R G = R L = 5 A V = - A V = - A V = A V = - A V = -5 A V = PEAKING (db) R G = R L = 5 A V = A V = ±V S (V) SUPPLY VOLTAGE (V) FIGURE 9. BANDWIDTH vs Vs FIGURE. PEAKING vs Vs R F = R G = V O = V PP.5V/DIV mv/div R F = R G = V O = mv PP ns/div FIGURE. LARGE SIGNAL STEP RESPONSE ns/div FIGURE. SMALL SIGNAL STEP RESPONSE FN76 Rev. Page of 9 May, 7

9 Typical Performance Curves (Continued) HARUMONIC DISTORTION (dbc) V O = V P-P R F = A V = R L = 5 3rd HD nd HD HARMONIC DISTORTION (dbc) V O = V P-P R F = A V = R L = 5 nd HD 3rd HD V OUT (V P-P ) FIGURE 3. MHz HARMONIC DISTORTION vs OUTPUT SWING V OUT (V P-P ) FIGURE. MHz HARMONIC DISTORTION vs OUTPUT SWING - -3 V O = V P-P THD (dbc) k k k M M M I N (pa/ Hz), V N (nv/ Hz) I N, V N, V N, I N, k k k FIGURE 5. TOTAL HARMONIC DISTORTION vs FREQUENCY FIGURE 6. NOISE vs FREQUENCY SETTLING TIME (ns) , V O = 5V P-P, V O = 5V P-P, V O = V P-P, V O = V P-P GROUP DELAY (ns) 6 R L = 5 A V = A V = -... ACCURACY (%) FIGURE 7. SETTLING TIME vs ACCURACY - M M M M FIGURE. GROUP DELAY vs FREQUENCY FN76 Rev. Page 9 of 9 May, 7

10 Typical Performance Curves (Continued) - V S =±5V -3 9 PSRR- CMRR (db) -5-7 PSRR (db) 7 5 PSRR k k k M M M k k M M M FIGURE 9. CMRR vs FREQUENCY FIGURE 3. PSRR vs FREQUENCY CLOSED LOOP OUTPUT IMPEDANCE ( ).. k k M M M BANDWIDTH (MHz) BANDWIDTH 6 PEAKING PEAKING (db) TEMPERATURE ( C) FIGURE 3. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY FIGURE 3. BANDWIDTH AND PEAKING vs TEMPERATURE SLEW RATE (V/µs) 6 6-5V SR - 5V SR + 5V SR - 5V SR V OUT SWING (V PP ) FIGURE 33. SLEW RATE vs SWING I S (ma) 5. V S =±5V 5. 5 V S =±5V FIGURE 3. SUPPLY CURRENT vs TEMPERATURE FN76 Rev. Page of 9 May, 7

11 Typical Performance Curves (Continued) V OS (mv) - CMRR (db) FIGURE 35. OFFSET VOLTAGE vs TEMPERATURE FIGURE 36. CMRR vs TEMPERATURE.5 6 PSRR (db) 9 9 V OUTH (V) FIGURE 37. PSRR vs TEMPERATURE FIGURE 3. POSITIVE OUTPUT SWING vs TEMPERATURE V OUTH (V) V OUTL (V) FIGURE 39. POSITIVE OUTPUT SWING vs TEMPERATURE FIGURE. NEGATIVE OUTPUT SWING vs TEMPERATURE FN76 Rev. Page of 9 May, 7

12 Typical Performance Curves (Continued) V OUTL (V) SLEW RATE (V/µs) FIGURE. NEGATIVE OUTPUT SWING vs TEMPERATURE FIGURE. SLEW RATE vs TEMPERATURE SR (V/µs) 5 5 V OUTH (V) V O = V PP FIGURE 3. SLEW RATE vs TEMPERATURE FIGURE. POSITIVE LOADED OUTPUT SWING vs TEMPERATURE SR (V/µs).. V OUTL (V) FIGURE 5. POSITIVE LOADED OUTPUT SWING vs TEMPERATURE FIGURE 6. NEGATIVE LOADED OUTPUT SWING vs TEMPERATURE FN76 Rev. Page of 9 May, 7

13 Typical Performance Curves (Continued) V OUTL (V) V S =±5V Die Temperature ( C) FIGURE 7. NEGATIVE LOADED OUTPUT SWING vs TEMPERATURE POWER DISSIPATION (W) JEDEC JESD5-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD mW mw SO JA = +6 C/W SOT3-5 JA = +56 C/W AMBIENT Temperature ( C) FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD W 53mW SO JA = + C/W SOT3-5 JA = +3 C/W AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN76 Rev. Page 3 of 9 May, 7

14 Pin Descriptions EL6CW (5 Ld SOT-3) EL6CS ( Ld SOIC) PIN NAME PIN FUNCTION EQUIVALENT CIRCUIT 6 VOUT Output V S + V OUT Circuit VS- Supply 3 3 VINA+ Input V S + V IN + V IN - V S - Circuit VINA- Input Reference Circuit 5 7 VS+ Supply FN76 Rev. Page of 9 May, 7

15 Applications Information Product Description The EL6 is an ultra-low noise, wideband monolithic operational amplifier built on Elantec's proprietary high speed complementary bipolar process. It features.3nv/ Hz input voltage noise, µv typical offset voltage, and 73dB THD. It is intended for use in systems such as ultrasound imaging where very small signals are needed to be amplified. The EL6 also has excellent DC specifications: µv V OS, µa IB,.µA I OS, and 6dB CMRR. These specifications allow the EL6 to be used in DC-sensitive applications such as difference amplifiers. Gain-Bandwidth Product The EL6 has a gain-bandwidth product of 65MHz at ±5V. For gains less than, higher-order poles in the amplifier's transfer function contribute to even higher closed-loop bandwidths. For example, the EL6 has a -3dB bandwidth of MHz at a gain of and decreases to 33MHz at gain of. It is important to note that the extra bandwidth at lower gain does not come at the expenses of stability. Even though the EL6 is designed for gain. With external compensation, the device can also operate at lower gain settings. The RC network shown in Figure 5 reduces the feedback gain at high frequency and thus maintains the amplifier stability. R values must be less than RF divided by 9 and divided by RC must be less than MHz. V IN C R - + R F FIGURE 5. V OUT Choice of Feedback Resistor, RF The feedback resistor forms a pole with the input capacitance. As this pole becomes larger, phase margin is reduced. This increases ringing in the time domain and peaking in the frequency domain. Therefore, RF has some maximum value which should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few pf range in parallel with RF can help to reduce this ringing and peaking at the expense of reducing the bandwidth. Frequency response curves for various RF values are shown in the typical performance curves section of this data sheet. Noise Calculations The primary application for the EL6 is to amplify very small signals. To maintain the proper signal-to-noise ratio, it is essential to minimize noise contribution from the amplifier. Figure 5 shows all the noise sources for all the components around the amplifier. V IN V N is the amplifier input voltage noise I N + is the amplifier positive input current noise I N - is the amplifier negative input current noise V RX is the thermal noise associated with each resistor: V RX where: R 3 V R3 I N + I N - k is Boltzmann's constant =.365 x -3 V N V R T is temperature in degrees Kelvin (73 + C) The total noise due to the amplifier seen at the output of the amplifier can be calculated by using the Equation. As the equation shows, to keep noise at a minimum, small resistor values should be used. At higher amplifier gain configuration where R is reduced, the noise due to IN-, R, and R decreases and the noise caused by IN+, VN, and R 3 starts to dominate. Because noise is summed in a root-meansquares method, noise sources smaller than 5% of the largest noise source can be ignored. This can greatly simplify the formula and make noise calculation much easier to calculate. R V R FIGURE R V ON = ktrx (EQ. ) V ON = BW VN R IN- R R IN+ R 3 R R K T R R + K T R K T R R 3 R R (EQ. ) FN76 Rev. Page 5 of 9 May, 7

16 Output Drive Capability The EL6 is designed to drive low impedance load. It can easily drive 6V P-P signal into a load. This high output drive capability makes the EL6 an ideal choice for RF, IF, and video applications. Furthermore, the EL6 is current-limited at the output, allowing it to withstand momentary short to ground. However, the power dissipation with output-shorted cannot exceed the power dissipation capability of the package. Driving Cables and Capacitive Loads Although the EL6 is designed to drive low impedance load, capacitive loads will decreases the amplifier's phase margin. As shown in the performance curves, capacitive load can result in peaking, overshoot and possible oscillation. For optimum AC performance, capacitive loads should be reduced as much as possible or isolated with a series resistor between 5 to. When driving coaxial cables, double termination is always recommended for reflection-free performance. When properly terminated, the capacitance of the coaxial cable will not add to the capacitive load seen by the amplifier. Power Supply Bypassing And Printed Circuit Board Layout As with any high frequency devices, good printed circuit board layout is essential for optimum performance. Ground plane construction is highly recommended. Lead lengths should be kept as short as possible. The power supply pins must be closely bypassed to reduce the risk of oscillation. The combination of a.7µf tantalum capacitor in parallel with.µf ceramic capacitor has been proven to work well when placed at each supply pin. For single supply operation, where pin (V S -) is connected to the ground plane, a single.7µf tantalum capacitor in parallel with a.µf ceramic capacitor across pins 7 (V S +) and pin (V S -) will suffice. Supply Voltage Range and Single Supply Operation The EL6 has been designed to operate with supply voltage range of ±.5V to ±5V. With a single supply, the EL6 will operate from +5V to +3V. Pins and 7 are the power supply pins. The positive power supply is connected to pin 7. When used in single supply mode, pin is connected to ground. When used in dual supply mode, the negative power supply is connected to pin. As the power supply voltage decreases from +3V to +5V, it becomes necessary to pay special attention to the input voltage range. The EL6 has an input voltage range of.v from the negative supply to.v from the positive supply. So, for example, on a single +5V supply, the EL6 has an input voltage range which spans from.v to 3.V. The output range of the EL6 is also quite large, on a +5V supply, it swings from.v to 3.V. For good AC performance, parasitic capacitance should be kept to a minimum. Ground plane construction again should be used. Small chip resistors are recommended to minimize series inductance. Use of sockets should be avoided since they add parasitic inductance and capacitance which will result in additional peaking and overshoot. FN76 Rev. Page 6 of 9 May, 7

17 Small Outline Package Family (SO) A D h X 5 N (N/)+ E E PIN # I.D. MARK c A SEE DETAIL X B. M C A B (N/) L C e H A SEATING PLANE GAUGE PLANE.. C. M C A B b A DETAIL X L ± MDP7 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (.3 ) SO SO SO SYMBOL SO- SO- (.5 ) (SOL-6) (SOL-) (SOL-) (SOL-) TOLERANCE NOTES A MAX - A A b c D , 3 E E , 3 e Basic - L L Basic - h Reference - N 6 6 Reference - Rev. M /7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included.. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M-99 FN76 Rev. Page 7 of 9 May, 7

18 Small Outline Transistor Plastic Packages (SOT3-5) E A A SEATING PLANE 5 e D e 3 C L. (.) M C C L X X WITH PLATING c C b VIEW C A BASE METAL C L C L. (.) C L L b b R R VIEW C SEATING PLANE -C- c GAUGE PLANE L E C P5.6 5 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A A A b b c c D E E e.37 Ref.95 Ref - e.7 Ref.9 Ref - L L. Ref..6 Ref. L. Ref..5 Ref. N R R....5 o o o o - Rev. 9/3 NOTES:. Dimensioning and tolerance per ASME Y.5M-99.. Package conforms to EIAJ SC-7 and JEDEC MO7AA. 3. Dimensions D and E are exclusive of mold flash, protrusions, or gate burrs.. Footlength L measured at reference to gauge plane. 5. N is the number of terminal positions. 6. These Dimensions apply to the flat section of the lead between.mm and.5mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. FN76 Rev. Page of 9 May, 7

19 SOT-3 Package Family 3.5 C D X C 5 E SEATING PLANE. C NX e N.5 C A-B X (L) A 6 e 3 B. M C A-B D b NX D 3 H E A D. C X A MDP3 SOT-3 PACKAGE FAMILY MILLIMETERS SYMBOL SOT3-5 SOT3-6 TOLERANCE A.5.5 MAX A.. ±.5 A.. ±.5 b.. ±.5 c.. ±.6 D.9.9 Basic E.. Basic E.6.6 Basic e Basic e.9.9 Basic L.5.5 ±. L.6.6 Reference N 5 6 Reference Rev. F /7 NOTES:. Plastic or metal protrusions of.5mm maximum per side are not included.. Plastic interlead protrusions of.5mm maximum per side are not included. 3. This dimension is measured at Datum Plane H.. Dimensioning and tolerancing per ASME Y.5M Index area - Pin # I.D. will be located within the indicated zone (SOT3-6 only). 6. SOT3-5 version has no center lead (shown as a dashed line). A GAUGE PLANE.5 c L +3 - Copyright Intersil Americas LLC -7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN76 Rev. Page 9 of 9 May, 7