DATASHEET EL5420T. Features. Applications. Ordering Information. 12MHz Rail-to-Rail Input-Output Operational Amplifier. FN6838 Rev 1.

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1 DATASHEET EL542T 2MHz Rail-to-Rail Input-Output Operational Amplifier The EL542T is a low power, high voltage rail-to-rail input-output amplifier. The EL542T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability and is unity gain stable. The maximum operating voltage range is from 4.5V to 9V. It can be configured for single or dual supply operation, and typically consumes only 5µA per amplifier. The EL542T has an output short circuit capability of ±2mA and a continuous output current capability of ±7mA. The EL542T features a slew rate of 2V/µs. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 2MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. These features make the EL542T an ideal amplifier solution for use in TFT-LCD panels as a V COM or static gamma buffer, and in high speed filtering and signal conditioning applications. Other applications include battery power and portable devices, especially where low power consumption is important. The EL542T is available in a 4 Ld TSSOP package, 4 Ld SOIC package, and a space saving thermally enhanced 6 Ld QFN package. All feature a standard operational amplifier pin out. The devices operate over an ambient temperature range of -4 C to +85 C. Ordering Information PART NUMBER (Note) EL542TILZ* (No longer available or supported) PART MARKING PACKAGE (Pb-Free) PKG. DWG. # 542TIL Z 6 Ld QFN MDP46 EL542TIRZ* 542TIR Z 4 Ld TSSOP MDP44 EL542TISZ*(No longer 542TIS Z 4 Ld SOIC MDP27 available or supported) *Add -T7 or -T3 suffix for tape and reel.please refer to TB347 for details on reel specifications NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and % matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-2. Features 2MHz (-3dB) Bandwidth 4.5V to 9V Maximum Supply Voltage Range 2V/µs Slew Rate 5µA Supply Current (per Amplifier) ±7mA Continuous Output Current ±2mA Output Short Circuit Current Unity-gain Stable Beyond the Rails Input Capability Rail-to-rail Output Swing Built-in Thermal Protection -4 C to +85 C Ambient Temperature Range Pb-free (RoHS compliant) Applications TFT-LCD Panels V COM Amplifiers Static Gamma Buffers Electronics Notebooks Electronics Games Touch-screen Displays Personal Communication Devices Personal Digital Assistants (PDA) Portable Instrumentation Sampling ADC Amplifiers Wireless LANs Office Automation Active Filters ADC/DAC Buffer FN6838 Rev. FN6838 Rev. Page of 7

2 Pinouts EL542T (6 LD QFN) TOP VIEW EL542T (4 LD TSSOP) TOP VIEW VINA+ VS+ VINB NC 6 5 VOUTA 5 6 VOUTB VOUTD 4 THERMAL PAD 7 VOUTC NC 3 8 VIND+ VINA- VINB- VINC- 2 VIND- VS- 9 VINC+ NO LONGER AVAILABLE OR SUPPORTED 4 VOUTD 3 VIND- 2 VIND+ VS- VINC+ 9 VINC- 8 VOUTC VOUTA VINA- VINA+ VS+ VINB+ VINB- VOUTB THERMAL PAD CONNECTS TO VS- FN6838 Rev. Page 2 of 7

3 Absolute Maximum Ratings () Supply Voltage between V S + and V S V Input Voltage Range (V INx+, V INx- ) V S - -.5V, V S + +.5V Input Differential Voltage (V INx+ - V INx- )...(V S + +.5V)-(V S - -.5V) Maximum Continuous Output Current ±7mA ESD Rating Human Body Model V Thermal Information Thermal Resistance Junction-to-Ambient (Typical) JA ( C/W) 6 Ld QFN (Note ) Ld SOIC (Note 2) Ld TSSOP (Note 2) Thermal Resistance Junction-to-Case (Typical) JC ( C/W) 6 Ld QFN (Note 3) Storage Temperature C to +5 C Ambient Operating Temperature C to +85 C Maximum Junction Temperature C Power Dissipation Curves See Figures 3 and 3 Pb-free Reflow Profile see link below CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES:. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech Brief TB JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 3. For JC, the case temp location is the center of the exposed metal pad on the package underside. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S + = +5V, V S - = -5V, R L = k to V,, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = V 3 3 mv TCV OS Average Offset Voltage Drift (Note 4) 4 LD TSSOP, SOIC package 7 µv/ C 6 LD QFN package 2 µv/ C I B Input Bias Current V CM = V 2 5 na R IN Input Impedance G C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V INx from -5.5V to +5.5V 5 75 db A VOL Open Loop Gain -4.5V V OUTx 4.5V 75 5 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -5mA V V OH Output Swing High I L = +5mA V I SC Short Circuit Current V CM = V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ±2 ma I OUT Output Current ±7 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range V I S Supply Current (Per Amplifier) V CM = V, No load 5 75 µa PSRR Power Supply Rejection Ratio Supply is moved from ±2.25V to ±9.5V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 5) -4.V V OUTx 4.V, 2% to 8% 2 V/µs FN6838 Rev. Page 3 of 7

4 Electrical Specifications V S + = +5V, V S - = -5V, R L = k to V,, unless otherwise specified. (Continued) PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT t S Settling to +.% (Note 6) A V = +, V OUTx = 2V step, R L = k, C L = 8pF 5 ns BW -3dB Bandwidth R L = k, C L = 8pF 2 MHz GBWP Gain-Bandwidth Product A V = -5, R F = 5k R G = R L = k, C L = 8pF PM Phase Margin A V = -5, R F = 5k R G = R L = k, C L = 8pF 8 MHz 5 CS Channel Separation f = 5MHz 75 db Electrical Specifications V S + = +5V, V S - = V, R L = k to 2.5V,, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 2.5V 3 3 mv TCV OS Average Offset Voltage Drift (Note 4) 4 LD TSSOP, SOIC package 7 µv/ C 6 LD QFN package 2 µv/ C I B Input Bias Current V CM = 2.5V 2 5 na R IN Input Impedance G C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V INx from -.5V to +5.5V 45 7 db A VOL Open Loop Gain.5V V OUTx 4.5V 75 5 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -2.5mA 3 5 mv V OH Output Swing High I L = +2.5mA V I SC Short Circuit Current V CM = 2.5V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ±25 ma I OUT Output Current ±7 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range V I S Supply Current (Per Amplifier) V CM = 2.5V, No load 5 75 µa PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 9V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 5) V V OUTx 4V, 2% to 8% 2 V/µs t S Settling to +.% (Note 6) A V = +, V OUTx = 2V step, R L = k, C L = 8pF 5 ns BW -3dB Bandwidth R L = k, C L = 8pF 2 MHz GBWP Gain-Bandwidth Product A V = -5, R F = 5k R G = R L = k, C L = 8pF PM Phase Margin A V = -5, R F = 5k R G = R L = k, C L = 8pF 8 MHz 5 CS Channel Separation f = 5MHz 75 db FN6838 Rev. Page 4 of 7

5 Electrical Specifications V S + = +8V, V S - = V, R L = k to 9V,, unless otherwise specified. PARAMETER DESCRIPTION CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS V OS Input Offset Voltage V CM = 9V 4 5 mv TCV OS Average Offset Voltage Drift (Note 4) 4 LD TSSOP, SOIC package 7 µv/ C 6 LD QFN package 2 µv/ C I B Input Bias Current V CM = 9V 2 5 na R IN Input Impedance G C IN Input Capacitance 2 pf CMIR Common-Mode Input Range V CMRR Common-Mode Rejection Ratio For V INx from -.5V to +8.5V db A VOL Open Loop Gain.5V V OUTx 7.5V 75 9 db OUTPUT CHARACTERISTICS V OL Output Swing Low I L = -9mA 5 mv V OH Output Swing High I L = +9mA V I SC Short Circuit Current V CM = 9V, Source: V OUTx short to V S -, Sink: V OUTx short to V S + ±2 ma I OUT Output Current ±7 ma POWER SUPPLY PERFORMANCE (V S +) - (V S -) Supply Voltage Range V I S Supply Current (Per Amplifier) V CM = 9V, No load µa PSRR Power Supply Rejection Ratio Supply is moved from 4.5V to 9V 6 75 db DYNAMIC PERFORMANCE SR Slew Rate (Note 5) V V OUTx 7V, 2% to 8% 2 V/µs t S Settling to +.% (Note 6) A V = +, V OUTx = 2V step, R L = k, C L = 8pF 5 ns BW -3dB Bandwidth R L = k, C L = 8pF 2 MHz GBWP Gain-Bandwidth Product A V = -5, R F = 5k R G = R L = k, C L = 8pF PM Phase Margin A V = -5, R F = 5k R G = R L = k, C L = 8pF 8 MHz 5 CS Channel Separation f = 5MHz 75 db NOTES: 4. Measured over -4 C to +85 C ambient operating temperature range. See the typical TCV OS production distribution shown in the Typical Performance Curves on page 6 5. Typical slew rate is an average of the slew rates measured on the rising (2%-8%) and the falling (8%-2%) edges of the output signal. 6. Settling time measured as the time from when the output level crosses the final value on rising/falling edge to when the output level settles within a ±.% error band. The range of the error band is determined by: Final Value(V)±[Full Scale(V)*.%] FN6838 Rev. Page 5 of 7

6 Typical Performance Curves QUANTITY (AMPLIFIERS) TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE (mv) FIGURE. INPUT OFFSET VOLTAGE DISTRIBUTION QUANTITY (AMPLIFIERS) VS = ±5V -4 C TO +85 C TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE DRIFT ( µv / C) FIGURE 2. INPUT OFFSET VOLTAGE DRIFT (TSSOP, SOIC) QUANTITY (AMPLIFIERS) VS = ±5V -4 C to +85 C TYPICAL PRODUCTION DISTRIBUTION INPUT OFFSET VOLTAGE DRIFT ( µv / C) FIGURE 3. INPUT OFFSET VOLTAGE DRIFT (QFN) INPUT OFFSET VOLTAGE (mv) TEMPERATURE ( C) FIGURE 4. INPUT OFFSET VOLTAGE vs TEMPERATURE INPUT BIAS CURRENT (na) TEMPERATURE ( C) FIGURE 5. INPUT BIAS CURRENT vs TEMPERATURE OUTPUT HIGH VOLTAGE (V) I OUT = 5mA TEMPERATURE ( C) FIGURE 6. OUTPUT HIGH VOLTAGE vs TEMPERATURE FN6838 Rev. Page 6 of 7

7 Typical Performance Curves (Continued) OUTPUT LOW VOLTAGE (V) VS = ±5V IOUT = -5mA OPEN LOOP GAIN (db) VS = ±5V RL = k TEMPERATURE ( C) FIGURE 7. OUTPUT LOW VOLTAGE vs TEMPERATURE TEMPERATURE ( C) FIGURE 8. OPEN-LOOP GAIN vs TEMPERATURE SLEW RATE (V/µs) VS = ±5V R L = k SUPPLY CURRENT (µa) NO LOAD INPUTS AT GND TEMPERATURE ( C) FIGURE 9. SLEW RATE vs TEMPERATURE TEMPERATURE ( C) FIGURE. SUPPLY CURRENT PER AMPLIFIER vs TEMPERATURE SUPPLY CURRENT (µa) SLEW RATE (V/µs) R L = k C L = 8pF SUPPLY VOLTAGE (±V) FIGURE. SUPPLY CURRENT PER AMPLIFIER vs SUPPLY VOLTAGE SUPPLY VOLTAGE (±V) FIGURE 2. SLEW RATE vs SUPPLY VOLTAGE FN6838 Rev. Page 7 of 7

8 Typical Performance Curves (Continued) 25 5 OPEN LOOP GAIN (db) GAIN 2 PHASE 5 R L = k C L = 8pF -2 k k k M M -5 M FIGURE 3. OPEN LOOP GAIN AND PHASE vs FREQUENCY 2 5 PHASE ( ) GAIN (db) -5 - C L = 8pF 5 k k 56-5 k M M M FIGURE 4. FREQUENCY RESPONSE FOR VARIOUS R L GAIN (db) 2 - pf pf 5pF 8pF -2 R L = k -3 k M M M FIGURE 5. FREQUENCY RESPONSE FOR VARIOUS C L OUTPUT IMPEDANCE ( ) R L = OPEN V OUTx = +3dBm k k k M M FIGURE 6. CLOSED LOOP OUTPUT IMPEDANCE vs FREQUENCY MAXIMUM OUTPUT SWING (V P-P ) R L = k C L = 8pF k k M M FIGURE 7. MAXIMUM OUTPUT SWING vs FREQUENCY CMRR (db) VS = ±5V TA = +25 C VINx = -dbm k k k M M FIGURE 8. CMRR vs FREQUENCY FN6838 Rev. Page 8 of 7

9 Typical Performance Curves (Continued) PSRR (db) VS = ±5V TA = +25 C PSRR+ -7 PSRR- -8 k k k M M FIGURE 9. PSRR vs FREQUENCY VOLTAGE NOISE (nv/ Hz) TA = +25 C k k k M M M FIGURE 2. INPUT VOLTAGE NOISE SPECTRAL DENSITY vs FREQUENCY THD+N (%) R L = k V IN =.4V RMS.5 k k k FIGURE 2. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY XTALK(dB) MEASURED CH A TO D, OR B TO C OTHER COMBINATIONS YIELD IMPROVED REJECTION V INx = dbm k k M M FIGURE 22. CHANNEL SEPARATION vs FREQUENCY RESPONSE OVERSHOOT (%) R L = k V INx = ±5mV LOAD CAPACITANCE (pf) FIGURE 23. SMALL SIGNAL OVERSHOOT vs LOAD CAPACITANCE STEP SIZE (V) R L = k C L = 8pF.%.% SETTLING TIME (ns) FIGURE 24. STEP SIZE vs SETTLING TIME FN6838 Rev. Page 9 of 7

10 Typical Performance Curves (Continued) V/DIV R L = k C L =8pF 5mV/DIV R L = k C L =8pF 2ns/DIV mv STEP 6V STEP µs/div FIGURE 25. LARGE SIGNAL TRANSIENT RESPONSE FIGURE 26. SMALL SIGNAL TRANSIENT RESPONSE EL542T (4LD TSSOP) VOUTA VOUTA VOUTD 4 VOUTD CLA RLA 2 VINA- VIND- 3 RLD CLD VINA+ 3 VINA+ VIND+ 2 VIND VS µF 4 Vs+ Vs- VS-.µF.µF + 4.7µF 49.9 VINB+ 5 VINB+ VINC+ VINC VINB- VINC VOUTB 7 VOUTB VOUTC 8 VOUTC CLB RLB RLC CLC FIGURE 27. BASIC TEST CIRCUIT Pin Descriptions EL542T 4 LD TSSOP, 4 LD SOIC 6 LD QFN PIN NAME FUNCTION EQUIVALENT CIRCUIT 5 VOUTA Amplifier A Output (Reference Circuit ) 2 VINA- Amplifier A Inverting Input (Reference Circuit 2) 3 2 VINA+ Amplifier A Non-Inverting Input (Reference Circuit 2) 4 3 VS+ Positive Power Supply 5 4 VINB+ Amplifier B Non-Inverting Input (Reference Circuit 2) 6 5 VINB- Amplifier B Inverting Input (Reference Circuit 2) 7 6 VOUTB Amplifier B Output (Reference Circuit ) 8 7 VOUTC Amplifier C Output (Reference Circuit ) 9 8 VINC- Amplifier C Inverting Input (Reference Circuit 2) FN6838 Rev. Page of 7

11 Pin Descriptions (Continued) EL542T 4 LD TSSOP, 4 LD SOIC 6 LD QFN PIN NAME FUNCTION EQUIVALENT CIRCUIT 9 VINC+ Amplifier C Non-Inverting Input (Reference Circuit 2) VS- Negative Power Supply 2 VIND+ Amplifier D Non-Inverting Input (Reference Circuit 2) 3 2 VIND- Amplifier D Inverting Input (Reference Circuit 2) 4 4 VOUTD Amplifier D Output (Reference Circuit ) 3, 6 NC No Connect pad Thermal Pad Functions as a heat sink. Connects to most negative potential, VS- V S+ V S+ V OUTx V INx GND CIRCUIT V S- CIRCUIT 2 V S- FN6838 Rev. Page of 7

12 Applications Information Product Description The EL542T is a high voltage rail-to-rail input-output amplifier with low power consumption. The EL542T contains four amplifiers. Each amplifier exhibits beyond the rail input capability, rail-to-rail output capability, and is unity gain stable. The EL542T features a slew rate of 2V/µs. Also, the device provides common mode input capability beyond the supply rails, rail-to-rail output capability, and a bandwidth of 2MHz (-3dB). This enables the amplifiers to offer maximum dynamic range at any supply voltage. Operating Voltage, Input and Output Capability The EL542T can operate on a single supply or dual supply configuration. The EL542T operating voltage ranges from a minimum of 4.5V to a maximum of 9V. This range allows for a standard 5V (or ±2.5V) supply voltage to dip to -%, or a standard 8V (or ±9V) to rise by +5.5% without affecting performance or reliability. The input common-mode voltage range of the EL542T extends 5mV beyond the supply rails. Also, the EL542T is immune to phase reversal. However, if the common mode input voltage exceeds the supply voltage by more than.5v, electrostatic protection diodes in the input stage of the device begin to conduct. Even though phase reversal will not occur, to maintain optimal reliability it is suggested to avoid input overvoltage conditions. Figure 28 shows the input voltage driven 5mV beyond the supply rails and the device output swinging between the supply rails. The EL542T output typically swings to within 5mV of positive and negative supply rails with load currents of ±5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure 29 shows the input and output waveforms for the device in a unity-gain configuration. Operation is from ±5V supply with a k load connected to GND. The input is a V P-P sinusoid and the output voltage is approximately 9.9V P-P. Refer to the Electrical Specifications Table beginning on page 3 for specific device parameters. Parameter variations with operating voltage, loading and/or temperature are shown in the Typical Performance Curves on page 6. V/DIV FIGURE 28. OPERATION WITH BEYOND-THE-RAILS INPUT 5V/DIV V S = ±2.5V,,, V INx = 6V P-P, R L = k to GND Output Current INPUT OUTPUT µs/div,,, V INx = V P-P, R L = k to GND µs/div FIGURE 29. OPERATION WITH RAIL-TO-RAIL INPUT AND The EL542T is capable of output short circuit currents of 2mA (source and sink), and the device has built-in protection circuitry which limits the short circuit current to ±2mA (typical). To maintain maximum reliability the continuous output current should never exceed ±7mA. This ±7mA limit is determined by the characteristics of the internal metal interconnects. Also, see Power Dissipation on page 3 for detailed information on ensuring proper device operation and reliability for temperature and load conditions. Unused Amplifiers It is recommended that any unused amplifiers be configured as a unity gain follower. The inverting input should be directly connected to the output and the non-inverting input tied to the ground. Thermal Shutdown The EL542T has a built-in thermal protection which ensures safe operation and prevents internal damage to the device due to overheating. When the die temperature reaches +65 C (typical) the device automatically shuts OFF the outputs by putting them in a high impedance state. When the die cools by 5 C (typical) the device automatically turns INPUT OUTPUT FN6838 Rev. Page 2 of 7

13 ON the outputs by putting them in a low impedance (normal) operating state. Driving Capacitive Loads As load capacitance increases, the -3dB bandwidth will decrease and peaking can occur. Depending on the application, it may be necessary to reduce peaking and to improve device stability. To improve device stability a snubber circuit or a series resistor may be added to the output of the EL542T. A snubber is a shunt load consisting of a resistor in series with a capacitor. An optimized snubber can improve the phase margin and the stability of the EL542T. The advantage of a snubber circuit is that it does not draw any DC load current or reduce the gain. Another method to reduce peaking is to add a series output resistor (typically between to ). Depending on the capacitive loading, a small value resistor may be the most appropriate choice to minimize any reduction in gain. Power Dissipation With the high-output drive capability of the EL542T amplifiers, it is possible to exceed the +5 C absolute maximum junction temperature under certain load current conditions. It is important to calculate the maximum power dissipation of the EL542T in the application. Proper load conditions will ensure that the EL542T junction temperature stays within a safe operating region. The maximum power dissipation allowed in a package is determined according to Equation : T JMAX T AMAX P DMAX = JA where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature JA = Thermal resistance of the package P DMAX = Maximum power dissipation allowed The total power dissipation produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power dissipation in the IC due to the loads, or: when sourcing, and: (EQ. ) P = DMAX iv S I SMAX + V S + V OUT i I LOAD i (EQ. 2) P = DMAX iv S I SMAX + V OUT i V S - I LOAD i (EQ. 3) where: i = to 4 (, 2, 3, 4 corresponds to Channel A, B, C, D respectively) V S = Total supply voltage (V S + - V S -) V S + = Positive supply voltage V S - = Negative supply voltage I SMAX = Maximum supply current per amplifier (I SMAX = EL542T quiescent current 4) V OUT = Output voltage I LOAD = Load current Device overheating can be avoided by calculating the minimum resistive load condition, R LOAD, resulting in the highest power dissipation. To find R LOAD set the two P DMAX equations equal to each other and solve for V OUT /I LOAD. Reference the package power dissipation curves, Figures 3 and 3, for further information. Power Dissipation (W) JEDEC JESD5-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.4W 962mW 833mW SOIC4 JA = 2 C/W QFN6 JA = 3 C/W TSSOP4 JA = 5 C/W Ambient Temperature ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Power Dissipation (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL 2.66W.42W.25W QFN6 JA = 47 C/W SOIC4 JA = 88 C/W TSSOP4 JA = C/W when sinking, Ambient Temperature ( C) FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6838 Rev. Page 3 of 7

14 Power Supply Bypassing and Printed Circuit Board Layout The EL542T can provide gain at high frequency, so good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, trace lengths should be as short as possible and the power supply pins must be well bypassed to reduce any risk of oscillation. For normal single supply operation (the V S - pin is connected to ground) a 4.7µF capacitor should be placed from V S + to ground, then a parallel.µf capacitor should be connected as close to the amplifier as possible. One 4.7µF capacitor may be used for multiple devices. For dual supply operation the same capacitor combination should be placed at each supply pin to ground. For the QFN package, with exposed thermal pad, the pad should be connected to the lowest potential, V S -, to optimize thermal and operating performance. PCB vias should be placed below the device s exposed thermal pad to transfer heat to the V S - plane and away from the device. Revision History DATE REVISION CHANGE FN6838. Updated Ordering Information Table on page. Added About Intersil section. September 25, 29 FN6838. Initial Release About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at You may report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at FN6838 Rev. Page 4 of 7

15 Small Outline Package Family (SO) A D h X 45 N (N/2)+ E E PIN # I.D. MARK c A SEE DETAIL Äö B. M C A B (N/2) L C e H A2 SEATING PLANE GAUGE PLANE..4 C. M C A B b A DETAIL X L 4 MDP27 SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SO6 SO6 (.3 ) SO2 SO24 SO28 SYMBOL SO-8 SO-4 (.5 ) (SOL-6) (SOL-2) (SOL-24) (SOL-28) TOLERANCE NOTES A MAX - A A b c D , 3 E E , 3 e Basic - L L Basic - h Reference - N Reference - Rev. M 2/7 NOTES:. Plastic or metal protrusions of.6 maximum per side are not included. 2. Plastic interlead protrusions of. maximum per side are not included. 3. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.5M-994 FN6838 Rev. Page 5 of 7

16 QFN (Quad Flat No-Lead) Package Family A 2X.75 C (E2) C 2 3 SEATING PLANE N LEADS L N (N-) (N-2) b (N/2) e PIN # I.D. MARK TOP VIEW (N/2). M C A B (N-2) (N-) N BOTTOM VIEW A DETAIL X 2 3. C.8 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D2) 2 7 (L) NE N LEADS E B 2X.75 C PIN # I.D. 5 3 MDP46 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-22) MILLIMETERS SYMBOL QFN44 QFN38 QFN32 TOLERANCE NOTES A ±. - A /-.2 - b ±.2 - c Reference - D Basic - D /2.48 Reference 8 E Basic - E /3.4 Reference 8 e Basic - L ±.5 - N Reference 4 ND Reference 6 NE Reference 5 MILLIMETERS TOLER- SYMBOL QFN28 QFN24 QFN2 QFN6 ANCE NOTES A ±. - A / b ±.2 - c Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±.5 - N Reference 4 ND Reference 6 NE Reference 5 Rev 2/7 NOTES:. Dimensioning and tolerancing per ASME Y4.5M Tiebar view shown is a non-functional feature. 3. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN6838 Rev. Page 6 of 7

17 Thin Shrink Small Outline Package Family (TSSOP) C E.25 M C A B E B SEATING PLANE. C N LEADS e N D TOP VIEW b SIDE VIEW SEE DETAIL Äú (N/2)+ (N/2) A PIN # I.D..2 C B A 2X N/2 LEAD TIPS.5. M C A B H MDP44 THIN SHRINK SMALL OUTLINE PACKAGE FAMILY MILLIMETERS SYMBOL 4 LD 6 LD 2 LD 24 LD 28 LD TOLERANCE A Max A..... ±.5 A ±.5 b /-.6 c /-.6 D ±. E Basic E ±. e Basic L ±.5 L..... Reference Rev. F 2/7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.5mm per side. 2. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.25mm per side. 3. Dimensions D and E are measured at datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.5M-994. c END VIEW L A A2 A DETAIL X L - 8 GAUGE PLANE.25 Copyright Intersil Americas LLC All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN6838 Rev. Page 7 of 7