DATASHEET. Features. Applications. Related Literature EL5224, EL5324, EL MHz Rail-to-Rail Buffers + 100mA V COM Amplifier

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1 DATASHEET EL54, EL54, EL544 MHz Rail-to-Rail Buffers + ma V COM Amplifier The EL54, EL54, and EL544 feature 8,, and low power buffers, respectively, and one high power output amplifier. They are designed primarily for buffering column driver reference voltages in TFT-LCD applications as well as generation of the V COM supply. Each low power buffer features a -db bandwidth of MHz and features rail-to-rail input/output capability. The high power buffer can drive ma and swings to within V of each rail. The 8-channel EL54 is available in 4 Ld QFN and 4 Ld HTSSOP packages, the -channel EL54 is available in Ld QFN and 8 Ld HTSSOP packages, and the -channel EL544 is available in the Ld QFN package. They are specified for operation across the full -4 C to +85 C temperature range. Related Literature For a full list of related documents, visit our website - EL54, EL54, EL544 product pages Features 8,, and channel versions MHz -db buffer bandwidth 5mA V COM buffer Operating supply voltage from 4.5V to 6.5V Low supply current - 6mA total (8-channel version) Rail-to-rail input/output swing (buffers only) QFN package - just.9mm high Pb-free (RoHS compliant) Applications TFT-LCD column driver buffering and V COM supply Electronics notebooks Computer monitors Electronics games Touch-screen displays Portable instrumentation FN74 Rev.4. FN74 Rev.4. Page of 6

2 EL54, EL54, EL544 Ordering Information PART NUMBER (Notes, ) PACKAGE (RoHS COMPLIANT) TAPE & REEL SIZE/QTY PKG. DWG. # EL54ILZ (No longer available or supported) 4 Ld QFN - MDP46 EL54ILZ-T7 (No longer available or supported) 4 Ld QFN 7 /k MDP46 EL54ILZ-T (No longer available or supported) 4 Ld QFN /.5k MDP46 EL54IREZ (No longer available or supported) 4 Ld HTSSOP - MDP48 EL54IREZ-T7 (No longer available or supported) 4 Ld HTSSOP 7 /k MDP48 EL54IREZ-T (No longer available or supported) 4 Ld HTSSOP /.5k MDP48 EL54ILZ (No longer available or supported) Ld QFN - L.5x6B EL54ILZ-T7 (No longer available or supported) Ld QFN 7 /k L.5x6B EL54ILZ-T (No longer available or supported) Ld QFN /.5k L.5x6B EL54IREZ 8 Ld HTSSOP - MDP48 EL54IREZ-T7 8 Ld HTSSOP 7 /k MDP48 EL54IREZ-T 8 Ld HTSSOP /.5k MDP48 EL544ILZ (No longer available or supported) Ld QFN - L.5x6B EL544ILZ-T7(No longer available or supported) Ld QFN 7 /k L.5x6B EL544ILZ-T (No longer available or supported) Ld QFN /.5k L.5x6B NOTES:. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and % matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-.. For Moisture Sensitivity Level (MSL), see product information pages for EL54, EL54, EL544. For more information on MSL, refer to TB6. FN74 Rev.4. Page of 6

3 EL54, EL54, EL544 Pin Configurations EL54 (4 LD HTSSOP) TOP VIEW EL54 (8 LD HTSSOP) TOP VIEW VIN 4 VOUT VIN 8 VOUT VIN VOUT VIN 7 VOUT VIN VOUT VIN 6 VOUT VIN4 VS+ VIN THERMAL PAD VOUT4 VS- 9 VOUT5 VIN4 VIN5 VS THERMAL PAD 5 VOUT4 4 VOUT5 VS- VIN6 7 8 VOUT6 VIN6 7 VOUT6 VIN7 8 7 VOUT7 VIN7 8 VOUT7 VIN8 9 6 VOUT8 VIN8 9 VOUT8 VSA+ 5 VSA- VIN9 9 VOUT9 VINA+ 4 VINA- VIN 8 VOUT NC VOUTA VSA+ 7 VSA- VINA+ 6 VINA- NC 4 5 VOUTA EL54 & EL544 ( LD QFN) TOP VIEW EL54 (4 LD QFN) TOP VIEW VIN* VIN VIN NC VOUT VIN VIN4 VIN5 VS+ VIN6 VIN7 VIN8 VIN9 VIN VOUT 4 VOUT4 VOUT5 VS- VOUT6 VOUT7 9 VOUT8 8 VOUT9 7 VOUT VIN* VSA+ VINA+ VOUTA VINA- VSA- VOUT* VOUT VOUT* VIN VIN NC VOUT VOUT THERMAL PAD 6 6 VIN VIN4 VS+ VIN5 VIN6 VIN7 VIN VSA+ 9 VINA+ THERMAL PAD VOUTA 9 VOUT 8 VOUT4 7 VS- 6 VOUT5 5 VOUT6 4 VOUT7 VOUT8 VINA- VSA- *Not available in EL54 FN74 Rev.4. Page of 6

4 EL54, EL54, EL544 Pin Descriptions 4 Ld HTSSOP 4 Ld QFN Ld QFN 8 Ld HTSSOP PIN NAME PIN FUNCTION VIN Input 4 (Note ) VIN Input VIN Input 4 4 VIN4 Input VS+ Power VIN5 Input VIN6 Input VIN7 Input VIN8 Input 8 VSA+ Power 9 VINA+ Positive input of V COM 9 4 NC Not connected 5 VOUTA Output of V COM VINA- Negative input of V COM VSA- Power 6 9 VOUT8 Output 7 4 VOUT7 Output 8 5 VOUT6 Output VOUT5 Output 7 VS- Power VOUT4 Output VOUT Output 6 (Note ) 7 VOUT Output VOUT Output NOTE:. Not available in EL54IL 8 VIN9 Input 9 VIN Input (Note ) VIN Input 6 (Note ) VOUT Output 7 8 VOUT Output 8 9 VOUT9 Output 8 VOUT Output VIN Input FN74 Rev.4. Page 4 of 6

5 EL54, EL54, EL544 Absolute Maximum Ratings (T A = +5 C) Supply Voltage between V S + and V S V Input Voltage V S - -.5V, V S + +.5V Maximum Continuous Output Current (V OUT-9 ) ma Maximum Continuous Output Current (V OUTA ) mA Power Dissipation See Curves Maximum Die Temperature C Storage Temperature C to +5 C Ambient Operating Temperature C to +85 C CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: All parameters having Min/Max specifications are established. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: T J = T C = T A Electrical Specifications V S+ = +5V, V S- =, R L = kω, R F = R G = kω, C L = pf to V, Gain of V COM = -, and T A = +5 C, unless otherwise specified DESCRIPTION PARAMETER CONDITIONS MIN TYP MAX UNIT INPUT CHARACTERISTICS (REFERENCE BUFFERS) Input Offset Voltage V OS V CM = V 4 mv Average Offset Voltage Drift TCV OS (Note 4) 5 µv/ C Input Bias Current I B V CM = V 5 na Input Impedance R IN GΩ Input Capacitance C IN.5 pf Voltage Gain A V V V OUT 4V.99.8 V/V INPUT CHARACTERISTICS (V COM BUFFER) Input Offset Voltage V OS V CM = 7.5V 4 mv Average Offset Voltage Drift TCV OS (Note 4) µv/ C Input Bias Current I B V CM = 7.5V na Input Impedance R IN GΩ Input Capacitance C IN.5 pf Load Regulation V REG V COM = 6V, -ma < I L < ma - + mv OUTPUT CHARACTERISTICS (REFERENCE BUFFERS) Output Swing Low V OL I L = 7.5mA 5 5 mv Output Swing High V OH I L = 7.5mA V Short-Circuit Current I SC 4 ma OUTPUT CHARACTERISTICS (V COM BUFFER) Output Swing Low V OL 5Ω to 7.5V.5 V Output Swing High V OH 5Ω to 7.5V.5 4 V Short-Circuit Current I SC 6 ma POWER SUPPLY PERFORMANCE Power Supply Rejection Ratio PSRR Reference buffer V S from 5V to 5V 55 8 db V COM buffer, V S from 5V to 5V 6 db Total Supply Current I S EL54 (no load) ma EL54 (no load) ma EL544 (no load) ma DYNAMIC PERFORMANCE (BUFFER AMPLIFIERS) Slew Rate (Note 5) SR -4V V OUT 4V, % to 8% 7 5 V/µs Settling to +.% (A V = +) t S (A V = +), V O = V step 5 ns -db Bandwidth BW R L = kω, C L = pf MHz FN74 Rev.4. Page 5 of 6

6 EL54, EL54, EL544 Electrical Specifications V S+ = +5V, V S- =, R L = kω, R F = R G = kω, C L = pf to V, Gain of V COM = -, and T A = +5 C, unless otherwise specified (Continued) DESCRIPTION PARAMETER CONDITIONS MIN TYP MAX UNIT Gain-Bandwidth Product GBWP R L = kω, C L = pf 8 MHz Phase Margin PM R L = kω, C L = pf 5 Channel Separation CS f = 5MHz 75 db NOTES: 4. Measured across operating temperature range. 5. Slew rate is measured on rising and falling edges. Typical Performance Curves NORMALIZED MAGNITUDE (db) - - C L = pf 5Ω kω 56Ω kω NORMALIZED MAGNITUDE (db) - - R L = kω 47pF pf pf pf - k M M M - k M M M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE. FREQUENCY RESPONSE FOR VARIOUS R L (BUFFER) FIGURE. FREQUENCY RESPONSE FOR VARIOUS C L (Buffer) PSRR (db) PSRR- PSRR+ OUTPUT IMPEDANCE (Ω) T A = +5 C k k k M M FREQUENCY (Hz) FIGURE. PSRR vs FREQUENCY (BUFFER) k M M M FREQUENCY (Hz) FIGURE 4. OUTPUT IMPEDANCE vs FREQUENCY (BUFFER) FN74 Rev.4. Page 6 of 6

7 EL54, EL54, EL544 Typical Performance Curves (Continued) VOLTAGE NOISE (nv/ Hz) OVERSHOOT (%) R L = kω V IN = mv k k M M M FREQUENCY (Hz) K CAPACITANCE (pf) FIGURE 5. INPUT NOISE SPECIAL DENSITY vs FREQUENCY (BUFFER) FIGURE 6. OVERSHOOT vs LOAD CAPACITANCE (BUFFER) 8 6 R L = kω C L = pf.8.6 V S = ±5V R L = kω V IN = V P-P STEP SIZE (V) THD + NOISE (%) k k k SETTLING TIME (ns) FREQUENCY (Hz) FIGURE 7. SETTLING TIME vs STEP SIZE (BUFFER) FIGURE 8. TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY (BUFFER) V OP-P (V) V S = ±5V R L = kω k k M M NORMALIZED MAGNITUDE (db) 4 - A V = 5-4 C L = µf -6 k k k A V = M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 9. OUTPUT SWING vs FREQUENCY (BUFFER) FIGURE. FREQUENCY RESPONSE (V COM ) FN74 Rev.4. Page 7 of 6

8 EL54, EL54, EL544 Typical Performance Curves (Continued) ma 5mA/DIV 5mA 5mA/DIV 5mA V R S = Ω C L = pf R S = Ω C L = 4.7nF R S = Ω C L = nf M = µs/div V IN = V 5mV/DIV ma V M = µs/div V IN = V R S = Ω C L = pf R S = Ω C L = nf R S = Ω C L = 4.7nF 5mV/DIV FIGURE. TRANSIENT LOAD REGULATION - SOURCING (BUFFER) FIGURE. TRANSIENT LOAD REGULATION - SINKING (BUFFER) M = 4µs/DIV,, V IN = V M = 4µs/DIV,, V IN = V ma ma/div ma -ma ma ma/div V C L = µf mv/div V C L = µf mv/div FIGURE. TRANSIENT LOAD REGULATION - SOURCING (V COM ) FIGURE 4. TRANSIENT LOAD REGULATION - SINKING (V COM ), R L = kω C L = pf 5mV/DIV V/DIV ns/div FIGURE 5. SMALL SIGNAL TRANSIENT RESPONSE (BUFFER) µs/div FIGURE 6. LARGE SIGNAL TRANSIENT RESPONSE (BUFFER) FN74 Rev.4. Page 8 of 6

9 EL54, EL54, EL544 Typical Performance Curves (Continued) POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY (4-LAYER) TEST BOARD, QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD5-5.7W.857W QFN4 JA = 7 C/W QFN JA = 5 C/W POWER DISSIPATION (W) JEDEC JESD5- AND SEMI G4-88 (SINGLE LAYER) TEST BOARD 74mW 758mW QFN4 JA = 4 C/W QFN JA = C/W AMBIENT TEMPERATURE ( C) AMBIENT TEMPERATURE ( C) FIGURE 7. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 8. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE POWER DISSIPATION (W) JEDEC JESD5-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD. HTSSOP EXPOSED DIEPAD SOLDERED TO PCB PER JESD5-5.W.W HTSSOP4 JA = C/W HTSSOP8 JA = C/W POWER DISSIPATION (W) JEDEC JESD5- LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD.9 99mW mW HTSSOP4 JA = C/W HTSSOP8 JA = C/W AMBIENT TEMPERATURE ( C) AMBIENT TEMPERATURE ( C) FIGURE 9. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN74 Rev.4. Page 9 of 6

10 EL54, EL54, EL544 Applications Information Product Description The EL54, EL54, and EL544 unity gain buffers and ma V COM amplifier are fabricated using a high voltage CMOS process. The buffers exhibit rail-to-rail input and output capability and has low power consumption (6µA per buffer). When driving a load of kω and pf, the buffers have a -db bandwidth of MHz and exhibits 8V/µs slew rate. The V COM amplifier exhibits rail-to-rail input. The output can be driving to within V of each supply rail. With a µf capacitance load, the GBWP is about MHz. Correct operation is ensured for a supply range of 4.5V to 6.5V. The Use of the Buffers The output swings of the buffers typically extend to within mv of positive and negative supply rails with load currents of 5mA. Decreasing load currents will extend the output voltage range even closer to the supply rails. Figure shows the input and output waveforms for the device. Operation is from ±5V supply with a kω load connected to GND. The input is a V P-P sinusoid. The output voltage is approximately 9.985V P-P. 5V 5V µs V S = ±5V T A = +5 C V IN = V P-P SHORT-CIRCUIT CURRENT LIMIT The buffers will limit the short-circuit current to ±ma if the output is directly shorted to the positive or the negative supply. If an output is shorted indefinitely, the power dissipation could easily increase such that the device may be damaged. Maximum reliability is maintained if the output continuous current never exceeds ±ma. This limit is set by the design of the internal metal interconnects. OUTPUT PHASE REVERSAL The buffers are immune to phase reversal as long as the input voltage is limited from V S - -.5V to V S + +.5V. Figure shows a photo of the output of the device with the input voltage driven beyond the supply rails. Although the device's output will not change phase, the input's overvoltage should be avoided. If an input voltage exceeds supply voltage by more than.6v, electrostatic protection diodes placed in the input stage of the device begin to conduct and overvoltage damage could occur. OUTPUT INPUT FIGURE. Operation with Rail-to-Rail Input and Output V V µs UNUSED BUFFERS It is recommended that any unused buffers have their inputs tied to the ground plane. DRIVING CAPACITIVE LOADS The buffers can drive a wide range of capacitive loads. As load capacitance increases, however, the -db bandwidth of the device will decrease and the peaking increase. The buffers drive pf loads in parallel with kω with just.5db of peaking, and pf with 6.4dB of peaking. If less peaking is desired in these applications, a small series resistor (usually between 5Ω and 5Ω) can be placed in series with the output. However, this will obviously reduce the gain slightly. Another method of reducing peaking is to add a snubber circuit at the output. A snubber is a shunt load consisting of a resistor in series with a capacitor. Values of 5Ω and nf are typical. The advantage of a snubber is that it does not draw any DC load current or reduce the gain. The Use of V COM Amplifier V S = ±.5V T A = +5 C V IN = 6V P-P FIGURE. Operation with Beyond-the-Rails Input The V COM amplifier is designed to control the voltage on the back plate of an LCD display. This plate is capacitively coupled to the pixel drive voltage which alternately cycles positive and negative at the line rate for the display. Thus, the amplifier must be capable of sourcing and sinking capacitive pulses of current, which can occasionally be quite large (a few ma for typical applications). A simple use of the V COM amplifier is as a voltage follower, as illustrated in Figure on page. Here, a voltage, corresponding to the mid-dac potential, is generated by a resistive divider and buffered by the amplifier. The amplifier's stability is designed to be dominated by the load capacitance, thus for very short duration pulses (<µs) the output capacitor supplies the current. For longer pulses the V COM amplifier supplies the current. By virtue of its high transconductance which progressively increases as more current is drawn, it can maintain regulation within 5mV as currents up to ma are drawn, while consuming only ma of quiescent current. FN74 Rev.4. Page of 6

11 EL54, EL54, EL544 R R IPCOM + INCOM - V BOOST V SSCOM V DDCOM V COM V COM µf CERAMIC LOW ESR FIGURE. V COM Used as a Voltage Buffer Alternatively, the back plate potential can be generated by a DAC and the V COM amplifier used to buffer the DAC voltage, with gain if necessary. This is shown in Figure 4. In this case, the effective transconductance of the feedback is reduced, thus the amplifier will be more stable, but regulation will be degraded by the feedback factor. FROM DAC V BOOST + - R R V COM µf CERAMIC LOW ESR FIGURE 4. V COM Used as a Buffer with Gain CHOICE OF OUTPUT CAPACITOR A µf ceramic capacitor with low ESR is recommended for this amplifier. (For example, GRM4_ 6X7R5K6.) This capacitor determines the stability of the amplifier. Reducing it will make the amplifier less stable, and should be avoided. With a µf capacitor, the unity gain bandwidth of the amplifier is close to MHz when reasonable currents are being drawn. (For lower load currents, the gain and hence bandwidth progressively decreases.) This means the active trans-conductance is: F MHz = 6.8S This high transconductance indicates why it is important to have a low ESR capacitor. If ESR x 6.8 >, then the capacitor will not force the gain to roll off below unity, and subsequent poles can affect stability. The recommended capacitor has an ESR of mω, but to this must be added the resistance of the board trace between the capacitor and the sense connection - therefore this should be kept short, as illustrated in Figure, by the diagonal line to the capacitor. Also ground resistance between the capacitor and the base of R must be kept to a minimum. These constraints should be considered when laying out the PCB. If the capacitor is increased above µf, stability is generally improved and short pulses of current will cause a smaller perturbation on the V COM voltage. The speed of response of the amplifier is however degraded as its bandwidth is decreased. At capacitor values around µf, a subtle interaction with internal DC gain boost circuitry will decrease the phase margin and may give rise to some overshoot in the response. The amplifier will remain stable though. RESPONSE TO HIGH CURRENT SPIKES The V COM amplifier's output current is limited to 5mA. This limit level, which is roughly the same for sourcing and sinking, is included to maintain reliable operation of the part. It does not necessarily prevent a large temperature rise if the current is maintained. (In this case the whole chip may be shut down by the thermal trip to protect functionality.) If the display occasionally demands current pulses higher than this limit, the reservoir capacitor will provide the excess and the amplifier will top the reservoir capacitor back up once the pulse has stopped. This will happen on the µs time scale in practical systems and for pulses or times the current limit, the V COM voltage will have settled again before the next line is processed. Power Dissipation With the high-output drive capability of the EL54, EL54, and EL544 buffer, it is possible to exceed the +5 C absolute-maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if load conditions need to be modified for the buffer to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to: T P JMAX - T AMAX DMAX = JA where: T JMAX = Maximum junction temperature T AMAX = Maximum ambient temperature JA = Thermal resistance of the package P DMAX = Maximum power dissipation in the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the loads, or: P DMAX = i V S I SMAX + V S + - V OUT i I LOAD i + V SA I SAA + V SA + - V OUTA I LA when sourcing, and: P DMAX = i V S I SMAX + V OUT i - V S - I LOAD i + V SA I SAA + V SA + - V OUTA I LA when sinking. FN74 Rev.4. Page of 6

12 EL54, EL54, EL544 where: i = to total number of buffers V S = Total supply voltage of buffer V SA = Total supply voltage of V COM I SMAX = Maximum quiescent current per channel I SA = Maximum quiescent current of V COM V OUT i = Maximum output voltage of the application V OUTA = Maximum output voltage of V COM I LOAD i = Load current of buffer I LA = Load current of V COM If we set the two P DMAX equations equal to each other, we can solve for the R LOAD 's to avoid device overheat. The package power dissipation curves provide a convenient way to see if the device will overheat. The maximum safe power dissipation can be found graphically, based on the package type and the ambient temperature. By using the previous equation, it is a simple matter to see if P DMAX exceeds the device's power derating curves. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, good printed circuit board layout is necessary for optimum performance. Ground plane construction is highly recommended, lead lengths should be as short as possible, and the power supply pins must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the V S - and V SA - pins are connected to ground, two.µf ceramic capacitors should be placed from V S + and V SA + pins to ground. A 4.7µF tantalum capacitor should then be connected from V S + and V SA + pins to ground. One 4.7µF capacitor may be used for multiple devices. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. Internally, V S + and V SA + are shorted together and V S - and V SA - are shorted together. To avoid high current density, the V S + pin and V SA + pin must be shorted in the PCB layout. Also, the V S - pin and V SA - pin must be shorted in the PCB layout. Important Note: The metal plane used for heat sinking of the device is electrically connected to the negative supply potential (V S - and V SA -). If V S - and V SA - are tied to ground, the thermal pad can be connected to ground. Otherwise, the thermal pad must be isolated from any other power planes. FN74 Rev.4. Page of 6

13 EL54, EL54, EL544 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please visit our website to make sure you have the latest revision. DATE REVISION CHANGE FN74.4 Applied new header/footer. Updated Ordering Information table. Added Note. Added Revision History and About Intersil sections. Added POD L.5X6B. Updated POD MDP46 to the latest revision changes are as follows: -cosmetic edit added dimensions over appropriate columns. Updated POD MDP48 to the latest revision changes are as follows: -Added dimensions (MILLIMETERS) to table About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing, and high-end consumer markets. For the most updated datasheet, application notes, related documentation, and related parts, see the respective product information page found at For a listing of definitions and abbreviations of common terms used in our documents, visit You can report errors or suggestions for improving this datasheet by visiting Reliability reports are also available from our website at Copyright Intersil Americas LLC -7. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see Intersil products are manufactured, assembled and tested utilizing ISO9 quality systems as noted in the quality certifications found at Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see FN74 Rev.4. Page of 6

14 EL54, EL54, EL544 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) A X.75 C (E) N LEADS L N (N-) (N-) b (N/) D PIN # I.D. MARK TOP VIEW (N/). M C A B (D) (N-) (N-) N 7 NE E B X.75 C PIN # I.D. 5 L.5x6B (One of Packages in MDP46) LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A A D 5. BSC - D.6 REF - E 6. BSC - E 4.6 REF - L b c. REF - e.5 BSC - N REF 4 ND 7 REF 6 NE 9 REF 5 Rev 9/5 NOTES:. Dimensioning and tolerancing per ASME Y4.5M Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/) as shown. BOTTOM VIEW C SEATING PLANE e. C C A (c).8 C N LEADS & EXPOSED PAD SEE DETAIL "X" SIDE VIEW A DETAIL X (L) N LEADS For the most recent package outline drawing, see L.5x6B. FN74 Rev.4. Page 4 of 6

15 EL54, EL54, EL544 QFN (Quad Flat No-Lead) Package Family A X.75 C (E) C SEATING PLANE N LEADS L N (N-) (N-) b (N/) e PIN # I.D. MARK TOP VIEW (N/). M C A B (N-) (N-) N BOTTOM VIEW A DETAIL X. C.8 C SEE DETAIL "X" N LEADS & EXPOSED PAD SIDE VIEW C A (c) D (D) 7 (L) NE N LEADS E B X.75 C PIN # I.D. 5 MDP46 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-) MILLIMETERS SYMBOL QFN44 QFN8 QFN TOLERANCE NOTES A ±. - A /-. - b ±. - c.... Reference - D Basic - D /.48 Reference 8 E Basic - E /.4 Reference 8 e Basic - L ±.5 - N 44 8 Reference 4 ND Reference 6 NE 8 9 Reference 5 MILLIMETERS TOLER- SYMBOL QFN8 QFN4 QFN QFN6 ANCE NOTES A ±. - A / -. - b ±. - c..... Reference - D Basic - D Reference - E Basic - E Reference - e Basic - L ±.5 - N Reference 4 ND Reference 6 NE Reference 5 Rev /7 NOTES:. Dimensioning and tolerancing per ASME Y4.5M Tiebar view shown is a non-functional feature.. Bottom-side pin # I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the E side of the package (or Y-direction). 6. ND is the number of terminals on the D side of the package (or X-direction). ND = (N/)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. For the most recent package outline drawing, see MDP46. FN74 Rev.4. Page 5 of 6

16 EL54, EL54, EL544 HTSSOP (Heat-Sink TSSOP) Family E C.5 M C A B E B N EXPOSED THERMAL PAD SEATING PLANE. C N LEADS e TOP VIEW b D SIDE VIEW (N/)+ D (N/) BOTTOM VIEW.5 A. M C A B PIN # I.D.. C B A X N/ LEAD TIPS E H MDP48 HTSSOP (HEAT-SINK TSSOP) FAMILY MILLIMETERS SYMBOL 4 LD LD 4 LD 8 LD 8 LD TOLERANCE A..... Max A ±.75 A /-. b /-.6 c /-.6 D ±. D Reference E Basic E ±. E..... Reference e Basic L ±.5 L..... Reference N Reference Rev. /7 NOTES:. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed.5mm per side.. Dimension E does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed.5mm per side.. Dimensions D and E are measured at Datum Plane H. 4. Dimensioning and tolerancing per ASME Y4.5M-994. SEE DETAIL X END VIEW c L A A A DETAIL X L - 8 GAUGE PLANE.5 For the most recent package outline drawing, see MDP48. FN74 Rev.4. Page 6 of 6